Patents/Inventors

Brian T. Pecha

Boise, IDUS3 patents

3 Patents

US125370412026
Memory with Programmable Refresh Order and Stagger Time
0 cites
US119673532024
Memory with Programmable Refresh Order and Stagger Time
0 cites
US119343262024
Memory with Improved Command/address Bus Utilization
0 cites