4 Patents
- US125507092026Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Adeia Semiconductor Solutions LLC
0 cites - US120338922024Structure and Method to Improve FAV RIE Process Margin and Electromigration
TESSERA LLC
0 cites - US119554242024Semiconductor Device Including a Porous Dielectric Layer, and Method of Forming the Semiconductor Device
Adeia Semiconductor Solutions LLC
0 cites - US117106582023Structure and Method to Improve FAV RIE Process Margin and Electromigration
TESSERA LLC
0 cites