Patents/Inventors

Ashutosh Garg

Mountain View, CAUS24 patents

20 Patents

US125969242026
System and Method for Machine-readable Electronic Document
Eightfold AI Inc.
0 cites
US124301282025
Sharing Register File Usage Between Fused Processing Resources
Intel Corporation
0 cites
US124057872025
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US122934312025
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US121982222025
Architecture for Block Sparse Operations on a Systolic Array
Intel Corporation
0 cites
US121417572024
System, Method, and Computer Program for Automatically Predicting the Job Candidates Most Likely to Be Hired and Successful in a Job
0 cites
US120457792024
System, Method, and Computer Program for Automatically Removing Data from Candidate Profiles That May Influence Bias
0 cites
US120390012024
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites
US120079352024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US120080672024
Sparse Matrix Multiplication Acceleration Mechanism
Intel Corporation
0 cites
US119778852024
Utilizing Structured Sparsity in Systolic Arrays
INTEL CORPORATION
0 cites
US119540632024
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US119005022024
Compiler Assisted Register File Write Reduction
Intel Corporation
0 cites
US118424232023
Dot Product Operations on Sparse Matrix Elements
Intel Corporation
0 cites
US117272012023
Annotation Framework for Video
Google LLC
0 cites
US117097932023
Graphics Processors and Graphics Processing Units Having Dot Product Accumulate Instruction for Hybrid Floating Point Format
Intel Corporation
0 cites
US116762392023
Sparse Optimizations for a Matrix Accelerator Architecture
Intel Corporation
0 cites
US116693292023
Instructions and Logic for Vector Multiply Add with Zero Skipping
Intel Corporation
0 cites
US116402972023
Instruction and Logic for Systolic Dot Product with Accumulate
Intel Corporation
0 cites
US116361742023
Scalable Sparse Matrix Multiply Acceleration Using Systolic Arrays with Feedback Inputs
Intel Corporation
0 cites