Patents/Inventors

Anton J. Devilliers

Albany, NYUS47 patents

37 Patents

US125999222026
System and Method for Liquid Dispense and Coverage Control
Tokyo Electron Limited
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US125640272026
Top-down Self-alignment of Vias in a Semiconductor Device for Sub-22nm Pitch Metals
Tokyo Electron Limited
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US125411552026
Coaxial See-through Inspection System
Tokyo Electron Limited
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US125299652026
Method for Selective Exposure of Wafer to Corrective Irradiation at a Per-die Level
Tokyo Electron Limited
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US125059982025
Method for Chuck Compensation via Wafer Shape Control
Tokyo Electron Limited
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US125000852025
Wet-dry Bilayer Resist
Tokyo Electron Limited
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US124889892025
Method to Form Narrow Slot Contacts
Tokyo Electron Limited
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US124555112025
In-situ Lithography Pattern Enhancement with Localized Stress Treatment Tuning Using Heat Zones
Tokyo Electron Limited
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US123931252025
Coaxial See-through Inspection System
Tokyo Electron Limited
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US123810932025
Hybrid Patterning-bonding Semiconductor Tool
Tokyo Electron Limited
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US123745622025
Wafer Shape Control for W2W Bonding
Tokyo Electron Limited
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US123277262025
Wet-dry Bilayer Resist Dual Tone Exposure
Tokyo Electron Limited
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US122769222025
Backside Deposition Tuning of Stress to Control Wafer Bow in Semiconductor Processing
Tokyo Electron Limited
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US122495082025
Selective Patterning with Wet-dry Bilayer Resist
Tokyo Electron Limited
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US120402712024
Power Delivery Network for CFET with Buried Power Rails
Tokyo Electron Limited
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US120209902024
Method for Threshold Voltage Tuning Through Selective Deposition of High-k Metal Gate (HKMG) Film Stacks
Tokyo Electron Limited
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US120011472024
Precision Multi-axis Photolithography Alignment Correction Using Stressor Film
Tokyo Electron Limited
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US119903342024
Method for Tuning Stress Transitions of Films on a Substrate
Tokyo Electron Limited
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US119661712024
Method for Producing Overlay Results with Absolute Reference for Semiconductor Manufacturing
Tokyo Electron Limited
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US119013602024
Architecture Design and Process for Manufacturing Monolithically Integrated 3D CMOS Logic and Memory
Tokyo Electron Limited
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US118838372024
System and Method for Liquid Dispense and Coverage Control
Tokyo Electron Limited
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US118624972024
Method for Die-level Unique Authentication and Serialization of Semiconductor Devices Using Electrical and Optical Marking
Tokyo Electron Limited
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US118548062023
Method for Pattern Reduction Using a Staircase Spacer
Tokyo Electron Limited
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US118416172023
Method of Forming a Narrow Trench
Tokyo Electron Limited
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US118108542023
Multi-dimensional Vertical Switching Connections for Connecting Circuit Elements
Tokyo Electron Limited
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US117768122023
Method for Pattern Reduction Using a Staircase Spacer
Tokyo Electron Limited
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US117215512023
Localized Stress Regions for Three-dimension Chiplet Formation
Tokyo Electron Limited
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US116949572023
Programmable Connection Segment and Method of Forming the Same
Tokyo Electron Limited
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US116886422023
Localized Stress Regions for Three-dimension Chiplet Formation
Tokyo Electron Limited
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US116825592023
Method to Form Narrow Slot Contacts
Tokyo Electron Limited
0 cites
US116769682023
Coaxial Contacts for 3D Logic and Memory
Tokyo Electron Limited
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US116401182023
Method of Pattern Alignment for Field Stitching
Tokyo Electron Limited
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US116409372023
Horizontal Programmable Conducting Bridges Between Conductive Lines
Tokyo Electron Limited
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US116303972023
Method for Producing Overlay Results with Absolute Reference for Semiconductor Manufacturing
Tokyo Electron Limited
0 cites
US116316712023
3D Complementary Metal Oxide Semiconductor (CMOS) Device and Method of Forming the Same
Tokyo Electron Limited
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US116160202023
Power Distribution Network for 3D Logic and Memory
Tokyo Electron Limited
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US116160532023
Method to Vertically Route a Logic Cell Incorporating Stacked Transistors in a Three Dimensional Logic Device
Tokyo Electron Limited
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