15 Patents
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- US125060192025Wafer Chuck Designs and Methods for Retaining a Processing Liquid on a Surface of a Semiconductor Wafer
Tokyo Electron Limited
0 cites - US1238111820253D Multiple Location Compressing Bonded Arm for Advanced Integration
Tokyo Electron Limited
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- US123362742025Self-aligned Method for Vertical Recess for 3D Device Integration
Tokyo Electron Limited
0 cites - US120992992024Method of Patterning a Substrate Using a Sidewall Spacer Etch Mask
Tokyo Electron Limited
0 cites - US120149842024Method of Manufacturing a Semiconductor Apparatus Having Stacked Devices
Tokyo Electron Limited
0 cites - US118482362023Method for Recessing a Fill Material Within Openings Formed on a Patterned Substrate
Tokyo Electron Limited
0 cites - US117823462023Method of Patterning a Substrate Using a Sidewall Spacer Etch Mask
Tokyo Electron Limited
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- US117641132023Method of 3D Logic Fabrication to Sequentially Decrease Processing Temperature and Maintain Material Thermal Thresholds
Tokyo Electron Limited
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- US117215822023Method of Making 3D Circuits with Integrated Stacked 3D Metal Lines for High Density Circuits
Tokyo Electron Limited
0 cites - US115748452023Apparatus and Method for Simultaneous Formation of Diffusion Break, Gate Cut, and Independent N and P Gates for 3D Transistor Devices
TOKYO ELECTRON LIMITED
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