Anthony Schepis

5 Patents

• US125123562025

  Apparatus and Method for Wafer Alignment

  Tokyo Electron Limited

  0 cites
• US123811182025

  3D Multiple Location Compressing Bonded Arm for Advanced Integration

  Tokyo Electron Limited

  0 cites
• US120992992024

  Method of Patterning a Substrate Using a Sidewall Spacer Etch Mask

  Tokyo Electron Limited

  0 cites
• US118624972024

  Method for Die-level Unique Authentication and Serialization of Semiconductor Devices Using Electrical and Optical Marking

  Tokyo Electron Limited

  0 cites
• US117823462023

  Method of Patterning a Substrate Using a Sidewall Spacer Etch Mask

  Tokyo Electron Limited

  0 cites