29 Patents
- US125751842026CMOS Architecture with Thermally Stable Silicide Gate Workfunction Metal
Intel Corporation
0 cites - US122551372025Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites - 0 cites
- 0 cites
- US121070852024Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites - 0 cites
- US120338962024Isolation Wall Stressor Structures to Improve Channel Stress and Their Methods of Fabrication
Intel Corporation
0 cites - 0 cites
- 0 cites
- 0 cites
- US119424162024Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites - 0 cites
- US118943722024Stacked Trigate Transistors with Dielectric Isolation and Process for Forming Such
Intel Corporation
0 cites - US118698942024Metallization Structures for Stacked Device Connectivity and Their Methods of Fabrication
Intel Corporation
0 cites - US118309332023Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
Intel Corporation
0 cites - US117768982023Sidewall Interconnect Metallization Structures for Integrated Circuit Devices
Intel Corporation
0 cites - 0 cites
- US117642632023Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approaches
Intel Corporation
0 cites - US117423462023Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites - US116996372023Vertically Stacked Transistor Devices with Isolation Wall Structures Containing an Electrical Conductor
Intel Corporation
0 cites - US116769662023Stacked Transistors Having Device Strata with Different Channel Widths
Intel Corporation
0 cites - 0 cites
- US116409612023III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites - 0 cites
- US116160602023Techniques for Forming Gate Structures for Transistors Arranged in a Stacked Configuration on a Single Fin Structure
Intel Corporation
0 cites - 0 cites
- US115945332023Stacked Trigate Transistors with Dielectric Isolation Between First and Second Semiconductor Fins
Intel Corporation
0 cites - US115737982023Stacked Transistors with Different Gate Lengths in Different Device Strata
Intel Corporation
0 cites - US115521042023Stacked Transistors with Dielectric Between Channels of Different Device Strata
Intel Corporation
0 cites