Alexandre Isoard

3 Patents

• US124881662025

  Implementing Burst Transfers for Predicated Memory Accesses in Loop Bodies for High-level Synthesis

  Xilinx, Inc.

  0 cites
• US118364262023

  Early Detection of Sequential Access Violations for High Level Synthesis

  Xilinx, Inc.

  0 cites
• US117627622023

  Static and Automatic Inference of Inter-basic Block Burst Transfers for High-level Synthesis

  Xilinx, Inc.

  0 cites