24 Patents
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- US125478042026Computing and Displaying a Predicted Overlap Shape in an IC Design Based on Predicted Manufacturing Contours
D2S, Inc.
0 cites - 0 cites
- US125416342026Routing Non-preferred Direction Wiring Layers of an Integrated Circuit by Minimizing Vias Between These Layers
D2S, Inc.
0 cites - 0 cites
- US124881752025Methods and Systems to Determine Parasitics for Semiconductor or Flat Panel Display Fabrication
D2S, Inc.
0 cites - US124752832025Generating and Display an Animation of a Predicted Overlap Shape in an IC Design
D2S, Inc.
0 cites - 0 cites
- US123728642025Methods and Systems to Determine Shapes for Semiconductor or Flat Panel Display Fabrication
D2S, Inc.
0 cites - US123401642025Methods and Systems for Reticle Enhancement Technology of a Design Pattern to Be Manufactured on a Substrate
D2S, Inc.
0 cites - 0 cites
- US122482422025Methods and Systems for Reticle Enhancement Technology of a Design Pattern to Be Manufactured on a Substrate
D2S, Inc.
0 cites - US122437122025Method and System for Determining a Charged Particle Beam Exposure for a Local Pattern Density
D2S, Inc.
0 cites - US120199732024Method for Reticle Enhancement Technology of a Design Pattern to Be Manufactured on a Substrate
D2S, Inc.
0 cites - US119538242024Method for Reticle Enhancement Technology of a Design Pattern to Be Manufactured on a Substrate
D2S, Inc.
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- US117831102023Method for Reticle Enhancement Technology of a Design Pattern to Be Manufactured on a Substrate
D2S, Inc.
0 cites - US117567652023Method and System for Determining a Charged Particle Beam Exposure for a Local Pattern Density
D2S, Inc.
0 cites - US116933062023Method for Reticle Enhancement Technology of a Design Pattern to Be Manufactured on a Substrate
D2S, Inc.
0 cites - 0 cites
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