Ajay Sharma

5 Patents

• US125005802025

  System and Method for Validating Critical Paths of Integrated Circuits

  NXP B.V.

  0 cites
• US121644012024

  Method and Apparatus to Inject Errors in a Memory Block and Validate Diagnostic Actions for Memory Built-in-self-test (MBIST) Failures

  NXP B.V.

  0 cites
• US121375172024

  Surface Wave Launcher for High-speed Data Links Over High-voltage Power Lines with Loss Compensation Structure

  Intel Corporation

  0 cites
• US119430502024

  PHY Error Indication Messaging

  Parallel Wireless, Inc.

  0 cites
• US118253402023

  Mitigation of Negative Delay via Half CP Shift

  Parallel Wireless, Inc.

  0 cites