Patents/Inventors

Abhishek Raja

Niagara Falls, NYUS22 patents

25 Patents

US124989302025
Store to Load Forwarding Using Hashes
Arm Limited
0 cites
US124750472025
Filtering Invalidation Requests
Arm Limited
0 cites
US124750482025
Linefill Delegation in a Cache Hierarchy
Arm Limited
0 cites
US124751082025
Fulfilment of Transaction Requests
Arm Limited
0 cites
US124231092025
Storing Load Predictions
Arm Limited
0 cites
US124232232025
Access Requests to Local Storage Circuitry
Arm Limited
0 cites
US124232332025
Order Enforcement for Delegable Memory Accesses
Arm Limited
0 cites
US124058982025
Memory Synchronisation Subsequent to a Page Table Walk
Arm Limited
0 cites
US122232022025
Store Buffer
Arm Limited
0 cites
US121973402025
Apparatus and Method for Cache Invalidation
Arm Limited
0 cites
US121824272024
Controlling Data Allocation to Storage Circuitry
Arm Limited
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US121752512024
Compression of Entries in a Reorder Buffer
Arm Limited
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US120936922024
Apparatus and Method with Prediction for Load Operation
Arm Limited
0 cites
US120615462024
Technique for Processing Lookup Requests, in a Cache Storage Able to Store Data Items of Multiple Supported Types, in the Presence of a Pending Invalidation Request
Arm Limited
0 cites
US120508052024
Control of Bulk Memory Instructions
Arm Limited
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US119891322024
Early Cache Querying
Arm Limited
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US119895832024
Circuitry and Method
Arm Limited
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US119777382024
Allocation of Store Requests
Arm Limited
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US119480132024
Apparatus and Method with Value Prediction for Load Operation
Arm Limited
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US117828452023
Faulting Address Prediction for Prefetch Target Address
Arm Limited
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US117626642023
Determining a Restart Point in Out-of-order Execution
Arm Limited
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US117481012023
Handling of Single-copy-atomic Load/store Instruction with a Memory Access Request Shared by Micro-operations
Arm Limited
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US117146442023
Predicated Vector Load Micro-operation for Performing a Complete Vector Load When Issued Before a Predicate Operation Is Available and a Predetermined Condition Is Unsatisfied
Arm Limited
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US117097822023
Memory Address Translation
Arm Limited
0 cites
US116630142023
Speculatively Executing Instructions That Follow a Status Updating Instruction
ARM LIMITED
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