Patents/Inventors

Aaron Lilak

Beaverton, ORUS29 patents

28 Patents

US125139842025
Double-sided Integrated Circuit Transistor Structures with Depopulated Bottom Channel Regions
Intel Corporation
0 cites
US123288642025
3D 1T1C Stacked Dram Structure and Method to Fabricate
Intel Corporation
0 cites
US122888072025
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
Intel Corporation
0 cites
US122551372025
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US122242022025
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US121488062024
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US121006232024
Vertically Stacked Finfets and Shared Gate Patterning
Intel Corporation
0 cites
US120209292024
Epitaxial Layer with Substantially Parallel Sides
Intel Corporation
0 cites
US119424162024
Sideways Vias in Isolation Areas to Contact Interior Layers in Stacked Devices
Intel Corporation
0 cites
US119358912024
Non-silicon N-type and P-type Stacked Transistors for Integrated Circuit Devices
Intel Corporation
0 cites
US119161182024
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US118943722024
Stacked Trigate Transistors with Dielectric Isolation and Process for Forming Such
Intel Corporation
0 cites
US118495722023
3D 1T1C Stacked DRAM Structure and Method to Fabricate
Intel Corporation
0 cites
US118309332023
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Bottom-up Oxidation Approach
Intel Corporation
0 cites
US117988382023
Capacitance Reduction for Semiconductor Devices Based on Wafer Bonding
Intel Corporation
0 cites
US117989912023
Amorphization and Regrowth of Source-drain Regions from the Bottom-side of a Semiconductor Assembly
Intel Corporation
0 cites
US117768982023
Sidewall Interconnect Metallization Structures for Integrated Circuit Devices
Intel Corporation
0 cites
US117698142023
Device Including Air Gapping of Gate Spacers and Other Dielectrics and Process for Providing Such
Intel Corporation
0 cites
US117641042023
Forming an Oxide Volume Within a Fin
Intel Corporation
0 cites
US117642632023
Gate-all-around Integrated Circuit Structures Having Depopulated Channel Structures Using Multiple Bottom-up Oxidation Approaches
Intel Corporation
0 cites
US117215542023
Stress Compensation for Wafer to Wafer Bonding
Intel Corporation
0 cites
US117217352023
Thin Film Transistors Having U-shaped Features
Intel Corporation
0 cites
US116643732023
Isolation Walls for Vertically Stacked Transistor Structures
Intel Corporation
0 cites
US116463522023
Stacked Source-drain-gate Connection and Process for Forming Such
Intel Corporation
0 cites
US116055652023
Three Dimensional Integrated Circuits with Stacked Transistors
Intel Corporation
0 cites
US115945332023
Stacked Trigate Transistors with Dielectric Isolation Between First and Second Semiconductor Fins
Intel Corporation
0 cites
US115749102023
Device with Air-gaps to Reduce Coupling Capacitance and Process for Forming Such
Intel Corporation
0 cites
US115692382023
Vertical Memory Cells
Intel Corporation
0 cites