Patents/Inventors

Aaron D. Lilak

Beaverton, ORUS29 patents

32 Patents

US125751512026
Gate-all-around Integrated Circuit Structures Having Doped Subfin
Intel Corporation
0 cites
US125751842026
CMOS Architecture with Thermally Stable Silicide Gate Workfunction Metal
Intel Corporation
0 cites
US125384702026
Structures and Methods for Memory Cells
Intel Corporation
0 cites
US122888102025
Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites
US122888132025
Gate-all-around Integrated Circuit Structures Having Insulator Fin on Insulator Substrate
Intel Corporation
0 cites
US121990982025
Fin Doping and Integrated Circuit Structures Resulting Therefrom
Intel Corporation
0 cites
US121070852024
Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites
US120806052024
Backside Contacts for Semiconductor Devices
Intel Corporation
0 cites
US120574942024
Stacked Transistors
Intel Corporation
0 cites
US120517232024
Pn-body-tied Field Effect Transistors
Intel Corporation
0 cites
US120338962024
Isolation Wall Stressor Structures to Improve Channel Stress and Their Methods of Fabrication
Intel Corporation
0 cites
US119964082024
Leave-behind Protective Layer Having Secondary Purpose
Intel Corporation
0 cites
US119359332024
Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites
US118942622024
Back Side Processing of Integrated Circuit Structures to Form Insulation Structure Between Adjacent Transistor Structures
Intel Corporation
0 cites
US118698942024
Metallization Structures for Stacked Device Connectivity and Their Methods of Fabrication
Intel Corporation
0 cites
US118627022024
Gate-all-around Integrated Circuit Structures Having Insulator FIN on Insulator Substrate
Intel Corporation
0 cites
US117842392023
Subfin Leakage Suppression Using Fixed Charge
Intel Corporation
0 cites
US117423462023
Interconnect Techniques for Electrically Connecting Source/drain Regions of Stacked Transistors
Intel Corporation
0 cites
US116996372023
Vertically Stacked Transistor Devices with Isolation Wall Structures Containing an Electrical Conductor
Intel Corporation
0 cites
US116769662023
Stacked Transistors Having Device Strata with Different Channel Widths
Intel Corporation
0 cites
US116721332023
Vertically Stacked Memory Elements with Air Gap
Intel Corporation
0 cites
US116643772023
Forksheet Transistor Architectures
Intel Corporation
0 cites
US116580722023
Vertically Stacked Transistors in a Fin
Intel Corporation
0 cites
US116581832023
Metallization Structures Under a Semiconductor Device Layer
Intel Corporation
0 cites
US116582212023
Backside Contact Structures and Fabrication for Metal on Both Sides of Devices
Intel Corporation
0 cites
US116409612023
III-V Source/drain in Top NMOS Transistors for Low Temperature Stacked Transistor Contacts
Intel Corporation
0 cites
US116160562023
Vertical Diode in Stacked Transistor Architecture
Intel Corporation
0 cites
US116160602023
Techniques for Forming Gate Structures for Transistors Arranged in a Stacked Configuration on a Single Fin Structure
Intel Corporation
0 cites
US116055562023
Back Side Processing of Integrated Circuit Structures to Form Insulation Structure Between Adjacent Transistor Structures
Intel Corporation
0 cites
US115737982023
Stacked Transistors with Different Gate Lengths in Different Device Strata
Intel Corporation
0 cites
US115631192023
Etchstop Regions in Fins of Semiconductor Devices
Intel Corporation
0 cites
US115521042023
Stacked Transistors with Dielectric Between Channels of Different Device Strata
Intel Corporation
0 cites