- US11811404utility2023Latch Circuit, Memory Device and Method0 cites
- US11799008utility2023Semiconductor Device and Method of Using0 cites
- US11769539utility2023Integrated Circuit with Asymmetric Arrangements of Memory Arrays0 cites
- US11769772utility2023Integrated Circuit with Active Region Jogs0 cites
- US11764288utility2023Semiconductor Device and Manufacturing Method Thereof0 cites
- US11764297utility2023LDMOS with Enhanced Safe Operating Area and Method of Manufacture0 cites
- US11764572utility2023Device and Method for Electrostatic Discharge Protection0 cites
- US11748550utility2023Integrated Circuit with Constrained Metal Line Arrangement0 cites
- US11742207utility2023Semiconductor Device and Manufacturing Method Thereof0 cites
- US11735251utility2023Timing Control Circuit of Memory Device with Tracking Word Line and Tracking Bit Line0 cites
- US11721374utility2023Control Circuit of Memory Device0 cites
- US11715505utility2023Memory Circuit and Method of Operating the Same0 cites
- US11705174utility2023Integrated Circuit with Asymmetric Arrangements of Memory Arrays0 cites
- US11705175utility2023Shared Decoder Circuit and Method0 cites
- US11699015utility2023Circuit Arrangements Having Reduced Dependency on Layout Environment0 cites
- US11699752utility2023Laterally Diffused MOSFET and Method of Fabricating the Same0 cites
- US11695339utility2023Dual Mode Supply Circuit and Method0 cites
- US11651134utility2023Method of Certifying Safety Levels of Semiconductor Memories in Integrated Circuits0 cites
- US11652348utility2023Integrated Circuit and an Operation Method Thereof0 cites
- US11568126utility2023Integrated Circuit Device Design Method and System0 cites