- US11908731utility2024Via-first Self-aligned Interconnect Formation Process0 cites
- US11908719utility2024Rounded Vertical Wafer Vessel Rods0 cites
- US11908708utility2024Laser De-bonding Carriers and Composite Carriers Thereof0 cites
- US11908702utility2024Gate Structures in Semiconductor Devices0 cites
- US11908742utility2024Semiconductor Device Having Merged Epitaxial Features with Arc-like Bottom Surface and Method of Making the Same0 cites
- US11908942utility2024Transistors Having Nanostructures0 cites
- US11908685utility2024Methods of Reducing Gate Spacer Loss During Semiconductor Manufacturing0 cites
- US11908681utility2024Semiconductor Fabricating System Having Hybrid Brush Assembly0 cites
- US11906897utility2024Method for Extreme Ultraviolet Lithography Mask Treatment0 cites
- US11908748utility2024Semiconductor Devices and Methods of Forming the Same0 cites
- US11908919utility2024Multi-gate Devices with Multi-layer Inner Spacers and Fabrication Methods Thereof0 cites
- US11908751utility2024Transistor Isolation Regions and Methods of Forming the Same0 cites
- US11908818utility2024Semiconductor Device0 cites
- US11908829utility2024Integrated Circuit Package and Method of Forming Same0 cites
- US11908836utility2024Semiconductor Package and Method of Manufacturing Semiconductor Package0 cites
- US11909312utility2024Regulated Voltage Systems and Methods Using Intrinsically Varied Process Characteristics0 cites
- US11910585utility2024Well Pick-up Region Design for Improving Memory Macro Performance0 cites
- US11908921utility2024Transistor Isolation Structures0 cites
- US11908853utility2024Integrated Circuit and Method of Generating Integrated Circuit Layout0 cites
- US11908859utility2024Semiconductor Device Including Transistors Sharing Gates with Structures Having Reduced Parasitic Circuit0 cites