- US11937515utility2024MRAM Structure for Balanced Loading0 cites
- US11934239utility2024Discrete Time Loop Based Thermal Control0 cites
- US11935620utility2024Memory Devices with Improved Refreshing Operation0 cites
- US11935624utility2024Memory Array Test Structure and Method of Forming the Same0 cites
- US11935722utility2024Machine Learning on Wafer Defect Review0 cites
- US11935746utility2024Pattern Formation Through Mask Stress Management and Resulting Structures0 cites
- US11935752utility2024Device of Dielectric Layer0 cites
- US11935754utility2024Transistor Gate Structure and Method of Forming0 cites
- US11935761utility2024Semiconductor Package and Method of Forming Thereof0 cites
- US11935781utility2024Integrated Circuit Structure with Backside Dielectric Layer Having Air Gap0 cites
- US11935783utility2024Selective Deposition for Integrated Circuit Interconnect Structures0 cites
- US11935793utility2024Dual Dopant Source/drain Regions and Methods of Forming Same0 cites
- US11935795utility2024Method for Forming a Crystalline Protective Polysilicon Layer0 cites
- US11935826utility2024Capacitor Between Two Passivation Layers with Different Etching Rates0 cites
- US11935885utility2024Device Including Integrated Electrostatic Discharge Protection Component0 cites
- US11935890utility2024Method for Forming Integrated Semiconductor Device with 2D Material Layer0 cites
- US11935894utility2024Integrated Circuit Device with Improved Layout0 cites
- US11930628utility2024Semiconductor Device and Manufacturing Method Thereof0 cites
- US11929425utility2024Nanowire Stack GAA Device with Inner Spacer0 cites
- US11929424utility2024Semiconductor Device and Method for Forming the Same0 cites