- US12153801utility2024Non-volatile Memory with Optimized Operation Sequence0 cites
- US12154625utility2024Variable Programming Clocks During a Multi- Stage Programming Operation in a NAND Memory Device0 cites
- US12154630utility2024Non-volatile Memory with Tuning of Erase Process0 cites
- US12148459utility2024Cross-point Array IHOLD Read Margin Improvement0 cites
- US12148478utility2024Erase Method for Non-volatile Memory with Multiple Tiers0 cites
- US12148489utility2024Early Detection of Programming Failure for Non-volatile Memory0 cites
- US12150302utility2024Memory Device Including Mixed Oxide Charge Trapping Materials and Methods for Forming the Same0 cites
- US12147695utility2024Non-volatile Memory with Adapting Erase Process0 cites
- US12142315utility2024Low Power Multi-level Cell (MLC) Programming in Non-volatile Memory Structures0 cites
- US12142323utility2024Foggy-fine Drain-side Select Gate Re-program for On-pitch Semi-circle Drain Side Select Gates0 cites
- US12142325utility2024Pre-read Cycle Timing Shrink by SGD Bias Control and Page and Wordline Control0 cites
- US12135542utility2024Modelling and Prediction of Virtual Inline Quality Control in the Production of Memory Devices0 cites
- US12137554utility2024Three-dimensional Memory Device with Word-line Etch Stop Liners and Method of Making Thereof0 cites
- US12137565utility2024Three-dimensional Memory Device with Vertical Word Line Barrier and Methods for Forming the Same0 cites
- US12124247utility2024Implementation of Deep Neural Networks for Testing and Quality Control in the Production of Memory Devices0 cites
- US12125814utility2024Bonded Assembly Containing Different Size Opposing Bonding Pads and Methods of Forming the Same0 cites