- US12387796utility2025Memory Assembly with Body Biasing and Related Methods0 cites
- US12388015utility2025E-fuse with Metal Fill0 cites
- US12388427utility2025Retention Flip-flop with Multiple Positive Supply Voltage Domains0 cites
- US12389616utility2025Transistors with Multiple Silicide Layers0 cites
- US12389627utility2025Silicon Germanium Fins and Integration Methods0 cites
- US12386379utility2025Non-volatile Current Mirror Circuit with Programmable Transistor0 cites
- US12381129utility2025Liner-free Through-silicon-vias Formed by Selective Metal Deposition0 cites
- US12381513utility2025IQ Phase Imbalance Calibration Using Sampling Clock Delay Adjustment0 cites
- US12376315utility2025Resistive Memory Element Arrays with Shared Electrode Strips0 cites
- US12376385utility2025Integrated Circuit Structures with Conductive Pathway Through Resistive Semiconductor Material0 cites
- US12372720utility2025Optical Power Splitters Incorporating One or More Spiral Elements0 cites
- US12372717utility2025Structure Including Hybrid Plasmonic Waveguide Using Metal Silicide Layer0 cites
- US12366873utility2025Low Drop-out (LDO) Regulator Circuit0 cites
- US12362172utility2025Integration of Compound-semiconductor-based Devices and Silicon-based Devices0 cites
- US12364000utility2025Device Structures for a High-voltage Semiconductor Device0 cites
- US12355431utility2025Switch with Back Gate-connected Compensation Capacitors0 cites
- US12356644utility2025Gate Tunnel Current-triggered Semiconductor Controlled Rectifier0 cites
- US12356675utility2025Planar Transistor Device Comprising at Least One Layer of a Two-dimensional (2D) Material0 cites
- US12353004utility2025Waveguide Escalators for a Photonics Chip0 cites
- US12353817utility2025Pcell Verification0 cites