Patents/Assignees

Ampere Computing LLC

42 patents in portfolio

US12613803utility2026
Cache Memory System Employing a Multiple-level Hierarchy Cache Coherency Architecture
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US12554640utility2026
Apparatuses, Systems, and Methods for Controlling Cache Allocations in a Configurable Combined Private and Shared Cache in a Processor-based System
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US12549479utility2026
Apparatus and Method of Routing a Request in a Mesh Network
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US12493552utility2025
Performing Snoop Filter Replacement Based on History-augmented Victimization Priority Values of Snoop Filter Entries in Processor-based Devices
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US12474848utility2025
Techniques for Memory Resource Control Using Memory Resource Partitioning and Monitoring
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US12451206utility2025
Extending Functionality of Memory Controllers Using a Loopback Mode for Testing in a Processor-based Device
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US12423108utility2025
Devices Transferring Cache Lines, Including Metadata on External Links
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US12411778utility2025
Advanced Initialization Bus (AIB)
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US12399998utility2025
Computing Systems Employing Measurement of Boot Components, Such as Prior to Trusted Platform Module (TPM) Availability, for Enhanced Boot Security, and Related Methods
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US12385975utility2025
Integrated Circuits Including Error Protection of Fields in Transferred Information and Field-based Error Signals and Related Methods
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US12379931utility2025
Mechanism for Instruction Fusion
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US12346264utility2025
Performing Instruction Fetch Pipeline Synchronization (IFPS) in Processor-based Devices
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US12333001utility2025
Mitigation of Return Stack Buffer Side Channel Attacks in a Processor
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US12314130utility2025
Parity Protected Memory Blocks Merged with Error Correction Code (ECC) Protected Blocks in a Codeword for Increased Memory Utilization
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US12282064utility2025
Component Die Validation Built-in Self-test (VBIST) Engine
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US12241932utility2025
Method and System for Testing Semiconductor Circuits
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US12228994utility2025
Method, Apparatus, and System for Calibrating a Processor Power Level Estimate
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US12204410utility2025
Integrated Error Correction Code (ECC) and Parity Protection in Memory Control Circuits for Increased Memory Utilization
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US12182417utility2024
Address-range Memory Mirroring in a Computer System, and Related Methods
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US12175243utility2024
Hardware Micro-fused Memory Operations
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