- US11900161utility2024Memory Allocation for Processing-in-memory Operations0 cites
- US11900123utility2024Marker-based Processor Instruction Grouping0 cites
- US11893502utility2024Dynamic Hardware Selection for Experts in Mixture-of-experts Model0 cites
- US11886224utility2024Core Selection Based on Usage Policy and Core Constraints0 cites
- US11880277utility2024Selecting an Error Correction Code Type for a Memory Device0 cites
- US11880683utility2024Packed 16 Bits Instruction Pipeline0 cites
- US11880715utility2024Method and System for Opportunistic Load Balancing in Neural Networks Using Metadata0 cites
- US11880769utility2024Using Multiple Functional Blocks for Training Neural Networks0 cites
- US11881450utility2024High Voltage Tolerant Capacitors0 cites
- US11881393utility2024Cross Field Effect Transistor Library Cell Architecture Design0 cites
- US11880260utility2024Instruction Subset Implementation for Low Power Operation0 cites
- US11880248utility2024Secondary External Cooling for Mobile Computing Devices0 cites
- US11880924utility2024Synchronization Free Cross Pass Binning Through Subpass Interleaving0 cites
- US11880312utility2024Data as Compute0 cites
- US11880610utility2024Storage Location Assignment at a Cluster Compute Server0 cites
- US11880310utility2024Cache Access Measurement Deskew0 cites
- US11875425utility2024Implementing Heterogeneous Wavefronts on a Graphics Processing Unit (GPU)0 cites
- US11876718utility2024Graded Throttling for Network-on-chip Traffic0 cites
- US11875875utility2024Variable Tick for DRAM Interface Calibration0 cites
- US11875197utility2024Management of Thrashing in a GPU0 cites