Shift Register, Driving Method Thereof, Gate Driving Circuit, and Display Device

CROSS REFERENCE TO RELATED APPLICATIONS

This patent application application is a reissue application of U.S. Pat. No. 11,302,257 B2, which was filed as U.S. patent application Ser. No. 16/645,733 on Mar. 9, 2020 and issued on Apr. 12, 2022, and which is a National Stage Entry of PCT/CN2019/070966 filed on Jan. 9, 2019, the disclosure disclosures of which is are incorporated by reference herein in its their entirety as part of the present application.

BACKGROUND

The present disclosure relates to the field of display technologies, and in particular, to a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.

With the development of display technology, compared with traditional Liquid Crystal Display (LCD) devices, the new generation of Organic Light Emitting Diode (OLED) display devices has advantages, such as, lower manufacturing costs, faster response speeds, higher contrast, wider viewing angle, larger operating temperature range, no need for a backlight unit, colorful and thin, and so on. Therefore, the OLED display technology has become the fastest growing display technology.

In order to improve process integration of an OLED display panel and reduce costs, a gate driving circuit with thin film transistors (TFTs) is usually integrated on an array substrate of the display panel by using Gate Driver on Array (GOA) technology, thereby performing scan driving for the display panel. Such gate driving circuit integrated on the array substrate using GOA technology can also be called a GOA unit or a shift register. Since the display device using the GOA circuit eliminates the need of binding a driving circuit, the cost can be reduced in terms of material costs and manufacturing processes.

BRIEF DESCRIPTION

Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.

A first aspect of the present disclosure provides a shift register. The shift register may include a blanking input circuit, a blanking control circuit, a blanking pull-down circuit, and a shift register circuit. The blanking input circuit may provide a blanking input signal from a blanking input signal terminal to a first control node according to a second clock signal from a second clock signal terminal. The blanking control circuit may provide a first clock signal from a first clock signal terminal to a second control node and maintain a voltage difference between the first control node and the second control node, according to a voltage of the first control node. The blanking pull-down circuit may provide a voltage of the second control node to a pull-down node according to the first clock signal. The shift register circuit may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal according to a voltage of the pull-down node.

In an embodiment of the present disclosure, the blanking control circuit may include a second transistor and a first capacitor. A control electrode of the second transistor is coupled to the first control node, a first electrode of the second transistor is coupled to the first clock signal terminal, and a second electrode of the second transistor is coupled to the second control node. The first capacitor is coupled between the first control node and the second control node.

In an embodiment of the present disclosure, the blanking input circuit may include a first transistor. A control electrode of the first transistor is coupled to the second clock signal terminal, a first electrode of the first transistor is coupled to the blanking input signal terminal, and a second electrode of the first transistor is coupled to the first control node.

In an embodiment of the present disclosure, the blanking pull-down circuit may include a third transistor. A control electrode of the third transistor is coupled to the first clock signal terminal, a first electrode of the third transistor is coupled to the second control node, and a second electrode of the third transistor is coupled to the pull-down node.

In an embodiment of the present disclosure, the shift register may further include a display input circuit and an output circuit. The display input circuit may provide a first voltage from a first voltage terminal to the pull-down node according to a display input signal from a display input signal terminal. The output circuit may output the shift signal from the shift signal output terminal and output the first drive signal from the first drive signal output terminal according to the voltage of the pull-down node.

In an embodiment of the present disclosure, the display input circuit may include a fourth transistor. A control electrode of the fourth transistor is coupled to the display input signal terminal, a first electrode of the fourth transistor is coupled to the first voltage terminal, and a second electrode of the fourth transistor is coupled to the pull-down node.

In an embodiment of the present disclosure, the output circuit may include a nineteenth transistor, a twenty-second transistor, and a second capacitor. A control electrode of the nineteenth transistor is coupled to the pull-down node, a first electrode of the nineteenth transistor is coupled to a fourth clock signal terminal to receive a fourth clock signal, and a second electrode of the nineteenth transistor is coupled to the shift signal output terminal. A control electrode of the twenty-second transistor is coupled to the pull-down node, a first electrode of the twenty-second transistor is coupled to the fourth clock signal terminal to receive the fourth clock signal, and a second electrode of the twenty-second transistor is coupled to the first drive signal output terminal. The second capacitor is coupled between the pull-down node and the shift signal output terminal.

In an embodiment of the present disclosure, the shift register circuit may further include a first control circuit, a pull-up circuit, and a second control circuit. The first control circuit may control a voltage of a pull-up node according to the voltage of the pull-down node. The pull-up circuit may provide a second voltage from a second voltage terminal to the pull-down node, the shift signal output terminal, and the drive signal output terminal according to the voltage of the pull-up node. The second control circuit may control the voltage of the pull-up node according to the first clock signal and the voltage of the first control node, and control the voltage of the pull-up node according to the display input signal.

In an embodiment of the present disclosure, the pull-up node may include a first pull-up node. A control electrode and a first electrode of the seventh transistor are coupled to a third voltage terminal, and a second electrode of the seventh transistor is coupled to the first pull-up node. A control electrode of the eighth transistor is coupled to the pull-down node, a first electrode of the eighth transistor is coupled to the first pull-up node, and a second electrode of the eighth transistor is coupled to the second voltage terminal. The pull-up circuit may include a ninth transistor, a twentieth transistor, and a twenty-third transistor. A control electrode of the ninth transistor is coupled to the first pull-up node, a first electrode of the ninth transistor is coupled to the pull-down node, and a second electrode of the ninth transistor is coupled to the second voltage terminal. A control electrode of the twentieth transistor is coupled to the first pull-up node, a first electrode of the twentieth transistor is coupled to the shift signal output terminal, and a second electrode of the twentieth transistor is coupled to the second voltage terminal. A control electrode of the twenty-third transistor is coupled to the first pull-up node, a first electrode of the twenty-third transistor is coupled to the first drive signal output terminal, and a second electrode of the twenty-third transistor is coupled to the second voltage terminal. A control electrode of the thirteenth transistor is coupled to the first clock signal terminal, and a first electrode of the thirteenth transistor is coupled to the first pull-up node. A control electrode of the fourteenth transistor is coupled to the first control node, a first electrode of the fourteenth transistor is coupled to a second electrode of the thirteenth transistor, and a second electrode of the fourteenth transistor is coupled to the second voltage terminal. A control electrode of the fifteenth transistor is coupled to the display input signal terminal, a first electrode of the fifteenth transistor is coupled to the first pull-up node, and a second electrode of the fifteenth transistor is coupled to the second voltage terminal.

In an embodiment of the present disclosure, the pull-up node may further include a second pull-up node. The first control circuit further includes a tenth transistor and an eleventh transistor. A control electrode and a first electrode of the tenth transistor are coupled to a fourth voltage terminal, and a second electrode of the tenth transistor is coupled to the second pull-up node. A control electrode of the eleventh transistor is coupled to the pull-down node, a first electrode of the eleventh transistor is coupled to the second pull-up node, and a second electrode of the eleventh transistor is coupled to the second voltage terminal. The pull-up circuit may further include a twelfth transistor, a twenty-first transistor, and a twenty-fourth transistor. A control electrode of the twelfth transistor is coupled to the second pull-up node, a first electrode of the twelfth transistor is coupled to the pull-down node, and a second electrode of the twelfth transistor is coupled to the second voltage terminal. A control electrode of the twenty-first transistor is coupled to the second pull-up node, a first electrode of the twenty-first transistor is coupled to the shift signal output terminal, and a second electrode of the twenty-first transistor is coupled to the second voltage terminal. A control electrode of the twenty-fourth transistor is coupled to the second pull-up node, a first electrode of the twenty-fourth transistor is coupled to the first drive signal output terminal, and a second electrode of the twenty-fourth transistor is coupled to the second voltage terminal. The second control circuit may further include a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. A control electrode of the sixteenth transistor is coupled to a first clock signal terminal, and a first electrode of the sixteenth transistor is coupled to the second pull-up node. A control electrode of the seventeenth transistor is coupled to the first control node, a first electrode of the seventeenth transistor is coupled to a second electrode of the sixteenth transistor, and a second electrode of the seventeenth transistor is coupled to the second voltage terminal. A control electrode of the eighteenth transistor is coupled to the display input signal terminal, a first electrode of the eighteenth transistor is coupled to the second pull-up node, and a second electrode of the eighteenth transistor is coupled to the second voltage terminal.

In an embodiment of the present disclosure, the shift register circuit may further include a reset circuit. The reset circuit may reset the pull-down node according to a blanking reset signal from a blanking reset signal terminal, and reset the pull-down node according to a display reset signal from a display reset signal terminal.

In an embodiment of the present disclosure, the reset circuit may include a fifth transistor and a sixth transistor. A control electrode of the fifth transistor is coupled to the blanking reset signal terminal, a first electrode of the fifth transistor is coupled to the pull-down node, and a second electrode of the fifth transistor is coupled to the second voltage terminal. A control electrode of the sixth transistor is coupled to the display reset signal terminal, a first electrode of the sixth transistor is coupled to the pull-down node, and a second electrode of the sixth transistor is coupled to the second voltage terminal.

In an embodiment of the present disclosure, the output circuit may further include a twenty-fifth transistor and a third capacitor. A control electrode of the twenty-fifth transistor is coupled to the pull-down node, a first electrode of the twenty-fifth transistor is coupled to a fifth clock signal terminal to receive a fifth clock signal, and a second electrode of the twenty-fifth transistor. The transistor is coupled to the second drive signal output terminal. The third capacitor is coupled between the pull-down node and the second drive signal output terminal.

In an embodiment of the present disclosure, the pull-up circuit may further include a twenty-sixth transistor and a twenty-seventh transistor. A control electrode of the twenty-sixth transistor is coupled to the first pull-up node, a first electrode of the twenty-sixth transistor is coupled to the second drive signal output terminal, and a second electrode of the twenty-sixth transistor is coupled to the second voltage terminal. A control electrode of the twenty-seventh transistor is coupled to the second pull-up node, a first electrode of the twenty-seventh transistor is coupled to the second drive signal output terminal, and a second electrode of the twenty-seventh transistor is coupled to the second voltage terminal.

A second aspect of the present disclosure provides a gate driving circuit. The gate driving circuit may include N cascaded shift registers as provided in the first aspect of the present disclosure, a first sub-clock signal line, and a second sub-clock signal line. A blanking input signal terminal of the shift register at the (i+1) th stage is coupled to a shift signal output terminal of the shift register at the i th stage. A first clock signal terminal of each of the shift registers is coupled to the first sub-clock signal line. A second clock signal terminal of each of the shift registers is coupled to the second sub-clock signal line.

In an embodiment of the present disclosure, the gate driving circuit may further include a blanking reset signal line, a first sub-clock signal line, and a second sub-clock signal line. A display input signal terminal of the shift register at the (i+2) th stage is coupled to the shift signal output terminal of the shift register at the i th stage. A blanking reset signal terminal of each of the shift registers is coupled to the blanking reset signal line. A display reset signal terminal of the shift register at the i th stage is coupled to the shift signal output terminal of the shift register at the (i+3) th stage.

In an embodiment of the present disclosure, the gate driving circuit may further include a third sub-clock signal line, a fourth sub-clock signal line, a fifth sub-clock signal line, and a sixth sub-clock signal line. A fourth clock signal terminal of the shift register at the (4i−3) th stage is coupled to the third sub-clock signal line. A fourth clock signal terminal of the shift register at the (4i−2) th stage is coupled to the fourth sub-clock signal line. A fourth clock signal terminal of the shift register at the (4i−1) th stage is coupled to the fifth sub-clock signal line. A fourth clock signal terminal of the shift register at the (4i) th stage is coupled to the sixth sub-clock signal line.

In an embodiment of the present disclosure, the gate driving circuit may further include a seventh sub-clock signal line, an eighth sub-clock signal line, a ninth sub-clock signal line, and a tenth sub-clock signal line. A fifth clock signal terminal of the shift register at the (4i−3) th stage is coupled to the seventh sub-clock signal line. A fifth clock signal terminal of the shift register at the (4i−2) th stage is coupled to the eighth sub-clock signal line. A fifth clock signal terminal of the shift register at the (4i−1) th stage is coupled to the ninth sub clock signal line. A fifth clock signal terminal of the shift register at the (4i) th stage is coupled to the tenth sub-clock signal line.

A third aspect of the present disclosure provides a display device. The display device includes a gate driving circuit provided according to a second aspect of the present disclosure.

A fourth aspect of the present disclosure provides a method for driving a shift register provided by the first aspect of the present disclosure. In the method, a blanking input signal may be provided to a first control node, and a voltage difference between a first control node and a second control node may be maintained. A first clock signal may be provided to the second control node according to a voltage of the first control node, and the voltage of the first control node is controlled via the voltage difference. A voltage of the second control node may be provided to a pull-down node according to a first clock signal. A shift signal and a first drive signal may be outputted according to a voltage of the pull-down node.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to illustrate the technical solutions of the present disclosure more clearly, the drawings of the embodiments will be briefly described below. It can be understood that the drawings described below are only related to some of the embodiments of the present disclosure, rather than limiting the present disclosure, wherein like reference signs indicate like elements or signals, in which:

FIG. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure;

FIG. 2 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure;

FIGS. 3 A and 3 B illustrate an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure;

FIGS. 4 A, 4 B, and 4 C respectively show exemplary circuit diagrams of a display input circuit according to some embodiments of the present disclosure;

FIGS. 5 A and 5 B respectively show exemplary circuit diagrams of a second control circuit according to some embodiments of the present disclosure;

FIGS. 6 A and 6 B illustrate an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure;

FIG. 7 illustrates a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 8 shows a timing chart of signals during an operation of a gate driving circuit according to an embodiment of the present disclosure; and

FIG. 9 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are merely part of the embodiments of the present disclosure, rather than all of the embodiments. According to the described embodiments, all the other embodiments obtained by those of ordinary skill in the art without creative labor also fall within the scope of protection of the present disclosure.

Unless otherwise stated, the technical or scientific terms used in the present disclosure shall have the ordinary meanings understood by those having ordinary skills in the art to which the present disclosure belongs. The terms “first”, “second”, and the like used in the present disclosure do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, “a”, “an”, or “the” and the like do not indicate a limit on quantity, but rather indicate that there is at least one. Words such as “including” or “comprising” mean that the element or item appearing before the word covers the element or item appearing after the word and the equivalent thereof, without excluding other elements or items. Words such as “connected” or “coupled” are not limited to physical or mechanical connections, but may include electrical connections, and may be direct connections or indirect connections through intermediate media. “Up”, “down”, “left”, “right”, or the like are only used to indicate the relative position relationship. In a case that the absolute position of the described object changes, the relative position relationship may also change accordingly.

In the display field, especially the organic light emitting diode OLED display technology, a gate driving circuit is usually integrated in an integrated circuit IC. The area of a chip in integrated circuit IC design is a major factor affecting chip cost. Generally, the gate driving circuit includes a detection circuit, a display circuit, and a connection circuit (or gate circuit) that outputs a composite pulse of both. This type of circuit structure is very complicated, thus it is difficult to meet the requirements of high-resolution narrow bezels.

When compensating a sub-pixel in an OLED display panel, in addition to providing a pixel compensation circuit in the sub-pixel for internal compensation, external compensation can also be performed by providing a sensing transistor. When external compensation is performed, a gate driving circuit including shift registers needs to provide a drive signal for a scanning transistor and a sensing transistor, respectively, to a sub-pixel in a display panel. For example, the display drive signal for the scanning transistor can be provided in a display period of a frame, and the sense drive signal for the sensing transistor can be provided in a blanking period of the frame.

In an embodiment of the present disclosure, “a frame”, “each frame”, or “a certain frame” includes a display period and a blanking period sequentially. For example, during the display period, the gate driving circuit outputs a display output signal. The display output signal can be used to drive the scanning transistors in the display panel to scan from the first line to the last line, such that the display panel may perform display. During the blanking period, the gate driving circuit outputs a blanking output signal. The blanking output signal can be used to drive the sensing transistors in a row of sub-pixels in the display panel to sense the driving current of the row of sub-pixels, such that compensation can be performed based on the sensed driving current.

Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device. The embodiments of the present disclosure and examples thereof will be described in details below with reference to the drawings.

FIG. 1 illustrates a schematic block diagram of a shift register according to an embodiment of the present disclosure. As shown in FIG. 1 , the shift register 10 may include a blanking input circuit 100 , a blanking control circuit 200 , a blanking pull-down circuit 300 , and a shift register circuit 1000 .

In the embodiment of the present disclosure, the blanking input circuit 100 may provide a blanking input signal STU 1 from a blanking input signal terminal to a first control node H according to a second clock signal CLKB from a second clock signal terminal, to control a voltage of the first control at node H. For example, the blanking input circuit 100 may be coupled to the second clock signal terminal to receive the second clock signal CLKB, and coupled to the blanking input signal terminal to receive the blanking input signal STU 1 .

The blanking control circuit 200 may provide a first clock signal CLKA from a first clock signal terminal to a second control node N according to the voltage of the first control node H, to control the voltage of the second control node N. The blanking control circuit 200 may also maintain a voltage difference between the first control node H and the second control node N. For example, the blanking control circuit 200 may be coupled to the first clock signal terminal to receive the first clock signal CLKA.

The blanking pull-down circuit 300 may provide the voltage of the second control node N to a pull-down node Q according to the first clock signal CLKA, to control a voltage of the pull-down node Q. For example, the blanking pull-down circuit 300 may be coupled to the first clock signal terminal to receive the first clock signal CLKA.

In the embodiment, since the blanking control circuit 200 can maintain the voltage difference between the first control node H and the second control node N, when the voltage of the second control node N changes, the voltage of the first control node H correspondingly changes. Therefore, the first clock signal CLKA can be provided to the second control node N in a lossless manner. In this case, the blanking pull-down circuit 300 may provide the first clock signal CLKA (i.e., the voltage of the second control node N) to the pull-down node Q without loss. Therefore, when a low potential voltage is written to the pull-down node Q during the blanking period, the threshold voltage loss of the transistor can be eliminated.

In addition, as the blanking control circuit 200 and the blanking pull-down circuit 300 are provided between the first control node H and the pull-down node Q, it prevents the voltage of the first control node H and the second control node N from affecting the voltage of the pull-down node Q.

The shift register circuit 1000 may provide a shift signal via a shift signal output terminal and a first drive signal via a first drive signal output terminal under the control of a voltage of the pull-down node Q. In a display period of one frame, the shift signal may be configured to, for example, perform shift scanning of the shift register units from upper to lower stages. The drive signal can be configured to drive the scanning transistors in the display panel, thereby driving the display panel for display. In the blanking period of one frame, the shift signal can also be configured to performing shift scanning of the shift register units from upper to lower stages, for example. The drive signal can be configured to drive the sensing transistors in the sub-pixels in the display panel, thereby performing the external compensation for the sub-pixels in the row.

FIG. 2 shows a schematic block diagram of a shift register according to another embodiment of the present disclosure. As shown in FIG. 2 , the shift register 20 may include a blanking input circuit 100 , a blanking control circuit 200 , a blanking pull-down circuit 300 , and a shift register circuit 1000 . In an embodiment, the shift register circuit 1000 may include a display input circuit 400 and an output circuit 500 . In addition, in other embodiments, the shift register circuit 1000 may further include a first control circuit 600 , a pull-up circuit 700 , and a second control circuit 800 . Further, in other embodiments, the shift register circuit 1000 may further include a reset circuit 900 .

FIG. 2 shows an example in which the shift register circuit 1000 includes a display input circuit 400 , an output circuit 500 , a first control circuit 600 , a pull-up circuit 700 , a second control circuit 800 , and a reset circuit 900 . The blanking input circuit 100 , the blanking control circuit 200 , and the blanking pull-down circuit 300 have been described in detail above, and are not repeated here. The following mainly describes the respectively circuits in the shift register circuit 1000 .

As shown in FIG. 2 , the display input circuit 400 may provide a first voltage V 1 from a first voltage terminal to the pull-down node Q according to a display input signal STU 2 from the display input signal terminal to control a voltage of the pull-down node Q. For example, the display input circuit 400 may be coupled to the display input signal terminal to receive the display input signal STU 2 , and coupled to the first voltage terminal to receive the first voltage V 1 . In an embodiment, the first voltage terminal may provide a direct current low-level signal, that is, the first voltage V 1 is at a low level.

The output circuit 500 may output a shift signal from the shift signal output terminal CR and a first drive signal from the first drive signal output terminal OUT 1 according to the voltage of the pull-down node Q. For example, the output circuit 500 may be coupled to the fourth clock signal terminal to receive the fourth clock signal CLKD. The output circuit 500 may provide the fourth clock signal CLKD to the shift signal output terminal CR according to the voltage of the pull-down node Q, to output the fourth clock signal CLKD as the shift signal, and provide the fourth clock signal CLKD to the first drive signal output terminal OUT 1 , to output the fourth clock signal CLKD as the first drive signal.

In an embodiment, the output circuit 500 may also output a second drive signal from a second drive signal output terminal OUT 2 according to the voltage of the pull-down node Q. For example, the output circuit 500 may be coupled to a fifth clock signal terminal to receive a fifth clock signal CLKE. In an embodiment, the output circuit 500 may further provide the fifth clock signal CLKE to the second drive signal output terminal OUT 2 according to the voltage of the pull-down node Q, to output the fifth clock signal CLKE as the second drive signal. Those skilled in the art can understand that the number of drive signal output terminals is not limited to two, but may be more than two. The output circuit may output the respective drive signals according to the respective clock signals. In the embodiment, during the display period, the shift signal and the corresponding drive signal may also be collectively referred to as a display output signal. Moreover, during the blanking period, the shift signal and the corresponding drive signal may also be collectively referred to as a blanking output signal.

The first control circuit 600 may control the voltage of the pull-up node QB according to the voltage of the pull-down node Q. For example, the first control circuit 600 may be coupled to a second voltage terminal to receive a second voltage V 2 , and coupled to a third voltage terminal to receive a third voltage V 3 . In an embodiment, the second voltage terminal may provide a DC high-level signal, that is, the second voltage V 2 is at a high level. The first control circuit 600 may control the voltage of the pull-up node QB according to the second voltage V 2 and the third voltage V 3 , under the control of the voltage of the pull-down node Q.

Further, the first control circuit 600 may be coupled to a fourth voltage terminal to receive a fourth voltage V 4 . The third voltage terminal and the fourth voltage terminal may alternately provide a DC low-level signal. For example, one of the third voltage V 3 and the fourth voltage V 4 is at a low level, and the other is at a high level. In an embodiment, the first control circuit 600 may control the voltage of the pull-up node QB according to the second voltage V 2 and the third voltage V 3 (or the fourth voltage), under the control of the voltage of the pull-down node Q.

The pull-up circuit 700 may provide the second voltage V 2 from the second voltage terminal to the pull-down node Q, the shift signal output terminal CR, the first drive signal output terminal OUT 1 and the second drive signal output terminal OUT 2 according to the voltage of the pull-up node QB. For example, the pull-up circuit 700 may be coupled to the second voltage terminal to receive the second voltage V 2 . Therefore, the pull-up circuit 700 pulls down the pull-down node Q, the shift signal output terminal CR, and the respective drive signal output terminal to reduce noise at each terminal.

The second control circuit 800 may control the voltage of the pull-up node QB according to the first clock signal CLKA and the voltage of the first control node H. For example, the second control circuit 800 may be coupled to the first clock signal terminal to receive the first clock signal CLKA, and coupled to the second voltage terminal to receive the second voltage. In an embodiment, the second control circuit 800 may provide the second voltage to the pull-up node QB under the control of the first clock signal CLKA and the voltage of the first control node H. In addition, the second control circuit 800 may control the voltage of the pull-up node QB according to a display input signal STU 2 . For example, the second control circuit 800 may be coupled to the display input signal terminal to receive the display input signal STU 2 . In an embodiment, the second control circuit 800 may provide the second voltage to the pull-up node QB under the control of the display input signal STU 2 . Therefore, the second control circuit 800 may pull up the pull-up node QB.

In addition, the reset circuit 900 may reset the pull-down node Q according to a blanking reset signal TRST from a blanking reset signal terminal, and reset the pull-down node Q according to a display reset signal STD from a display reset signal terminal. For example, the reset circuit 900 may be coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, coupled to the display reset signal terminal to receive the display reset signal STD, and coupled to the second voltage terminal to receive the second voltage V 2 . In an embodiment, the reset circuit 900 may provide the second voltage V 2 to the pull-down node Q according to the blanking reset signal TRST, and provide the second voltage V 2 to the pull-down node Q according to the display reset signal STD.

Those skilled in the art can understand that, while, as FIG. 2 shows, the shift register circuit 1000 includes the display input circuit 400 , the output circuit 500 , the first control circuit 600 , the pull-up circuit 700 , the second control circuit 800 , and the reset circuit 900 , the above examples do not limit the protection scope of the present disclosure. In actual practice, a technician may choose to use or not use one or more of the above circuits according to the situation. Various combinations and modifications based on the foregoing circuits are not deviated from the principles of the present disclosure. The details can be omitted here.

The shift register provided by the embodiments of the present disclosure are described below with exemplary circuit structures.

FIGS. 3 A and 3 B illustrate an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure. The shift register is, for example, the shift register 20 shown in FIG. 2 . As shown in FIGS. 3 A and 3 B , the shift register may include a first transistor M 1 to a twenty-seventh transistor M 27 , and a first capacitor C 1 to a third capacitor C 3 .

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with like characteristics. In the embodiments of the present disclosure, the thin film transistor is taken as an example for description. A source and a drain of the transistor herein can be symmetrical in structure, thus there can be no difference in structure of the source and the drain of the transistor. In an embodiment of the present disclosure, in order to distinguish the two electrodes of the transistor other than a gate, one electrode can be referred to as a first electrode and the other electrode can be referred to as a second electrode. The gate of the transistor can be referred to as a control electrode. In addition, the transistors can be classified into N-type and P-type transistors according to the characteristics of the transistors. If the transistor is a P-type transistor, an ON voltage is a low-level voltage, for example, 0V, −5V, −10V, or other suitable voltage, and an OFF voltage is a high-level voltage, for example, 5V, 10V, or other suitable voltage. If the transistor is an N-type transistor, an ON voltage is a high-level voltage, for example, 5V, 10V, or other suitable voltage, and an OFF voltage is a low-level voltage, for example, 0V, −5V, −10V, or other suitable voltage.

In addition, it should be noted that, in the embodiments of the present disclosure, the transistors in the shift register can be described by taking P-type transistors as an example. The embodiments of the present disclosure may also include, but are not limited to, for example, employing N-type transistors for at least part of the transistors in the shift register. In such cases, the potentials of the voltages, such as, the first voltage, the second voltage, or the like, may change correspondingly.

In an embodiment of the present disclosure, the pull-up node QB may include at least one of a first pull-up node QB_A and a second pull-up node QB_B. FIGS. 3 A and 3 B show a case where the pull-up node QB includes both the first pull-up node QB_A and the second pull-up node QB_B. It can be understood that the pull-up node QB may also include only one of the first pull-up node QB_A and the second pull-up node QB_B, and the associated circuits may only be adjusted accordingly.

As shown in FIGS. 3 A and 3 B , the blanking input circuit 100 includes a first transistor M 1 . A control electrode of the first transistor M 1 is coupled to the second clock signal terminal to receive the second clock signal CLKB. A first electrode of the first transistor M 1 is coupled to the blanking input signal terminal to receive the blanking input signal STU 1 . A second electrode of the first transistor M 1 is coupled to the first control node H. In an embodiment, when the second clock signal CLKB is at a low level, the first transistor M 1 is turned on, such that the blanking input signal can be provided to the first control node H to control the voltage of the first control node H.

The blanking control circuit 200 includes a second transistor M 2 and a first capacitor C 1 . A control electrode of the second transistor M 2 is coupled to the first control node H. A first electrode of the second transistor M 2 is coupled to the first clock signal terminal to receive the first clock signal CLKA. A second electrode of the second transistor M 2 is coupled to the second control node N. A first end of the first capacitor is coupled to the first control node H, and the second end of the first capacitor is coupled to the second control node N. In an embodiment, in a case that the voltage of the first control node H is at a low level, the second transistor M 2 is turned on, and the first clock signal CLKA is provided to the second control node N to control the voltage of the second control node N. When the voltage of the second control node N changes, as the first capacitor C 1 maintains the voltage difference between the first control node H and the second control node N, the voltage of the first control node H also changes accordingly.

The blanking pull-down circuit 300 includes a third transistor M 3 . A control electrode of the third transistor M 3 is coupled to the first clock signal terminal to receive the first clock signal CLKA. A first electrode of the third transistor M 3 is coupled to the second control node N. A second electrode of the third transistor M 3 is coupled to the pull-down node Q. In an embodiment, in a case that the first clock signal CLKA is at a low level, the third transistor M 3 is turned on, such that the voltage of the second control node N is provided to the pull-down node Q.

The display input circuit 400 includes a fourth transistor M 4 . A control electrode of the fourth transistor M 4 is coupled to the display input signal terminal to receive the display input signal STU 2 . A first electrode of the fourth transistor M 4 is coupled to the first voltage terminal to receive the first voltage V 1 . A second electrode of the fourth transistor M 4 is coupled to the pull-down node Q. In an embodiment, in a case that the display input signal STU 2 is at a low level, the fourth transistor M 4 is turned on, to provide the first voltage V 1 to the pull-down node Q, such that the voltage of the pull-down node Q is at a low level.

The output circuit 500 includes a nineteenth transistor M 19 , a twenty-second transistor M 22 , and a second capacitor C 2 . A control electrode of the nineteenth transistor M 19 is coupled to the pull-down node Q. A first electrode of the nineteenth transistor M 19 is coupled to a fourth clock signal terminal to receive a fourth clock signal CLKD. A second electrode of the nineteenth transistor M 19 is coupled to the shift signal output terminal CR. A control electrode of the twenty-second transistor M 22 is coupled to the pull-down node Q. A first electrode of the twenty-second transistor M 22 is coupled to the fourth clock signal terminal to receive the fourth clock signal CLKD. A second electrode of the twenty-second transistor M 22 is coupled to the first drive signal output terminal OUT 1 . A first end of the second capacitor C 2 is coupled to the pull-down node Q, and the second end of the second capacitor C 2 is coupled to the shift signal output terminal CR.

In addition, the output circuit 500 may further include a twenty-fifth transistor M 25 and a third capacitor C 3 . A control electrode of the twenty-fifth transistor M 25 is coupled to the pull-down node Q. A first electrode of the twenty-fifth transistor M 25 is coupled to a fifth clock signal terminal to receive a fifth clock signal CLKE. A second electrode of the twenty-fifth transistor M 25 is coupled to the second drive signal output terminal OUT 2 . A first end of the third capacitor C 3 is coupled to the pull-down node Q, and a second end of the third capacitor C 3 is coupled to the second drive signal output terminal OUT 2 .

In the embodiment, when the pull-down node Q is at a low level, the nineteenth transistor M 19 , the twenty-second transistor M 22 , and the twenty-fifth transistor M 25 are turned on, to provide the fourth clock signal CLKD to the shift signal output terminal CR and the first drive signal output terminal OUT 1 , and to provide the fifth clock signal CLKE to the second drive signal output terminal OUT 2 .

The first control circuit 600 includes a seventh transistor M 7 , an eighth transistor M 8 , a tenth transistor M 10 , and an eleventh transistor M 11 . A control electrode and a first electrode of the seventh transistor M 7 are coupled to a third voltage terminal to receive the third voltage V 3 . A second electrode of the seventh transistor M 7 is coupled to the first pull-up node QB_A. A control electrode of the eighth transistor M 8 is coupled to the pull-down node Q. A first electrode of the eighth transistor M 8 is coupled to the first pull-up node QB_A. A second electrode of the eighth transistor M 8 is coupled to the second voltage terminal to receive the second voltages V 2 . A control electrode and a first electrode of the tenth transistor M 10 is coupled to a fourth voltage terminal V 4 . A second electrode of the tenth transistor M 10 is coupled to the second pull-up node QB_B. A control electrode of the eleventh transistor M 11 is coupled to the pull-down node Q. A first electrode of the eleventh transistor M 11 is coupled to the second pull-up node QB_B. A second electrode of the eleventh transistor M 11 is coupled to the second voltage terminal V 2 to receive the second voltage V 2 .

It can be understood, in a case that the pull-up node QB includes only the first pull-up node QB_A (or the second pull-up node QB_B), the first control circuit 600 may include a seventh transistor M 7 and an eighth transistor M 8 (or a tenth transistor M 10 and eleventh transistor M 11 ). In this situation, the specific circuit structure is similar and will not be repeated here.

In an embodiment, the third voltage terminal V 3 and the fourth voltage terminal V 4 may be configured to alternately provide a low level voltage. That is, when the third voltage terminal V 3 provides a high level voltage, the fourth voltage terminal V 4 provides a low level voltage, and the tenth transistor M 10 is turned on. When the third voltage terminal V 3 provides a low level voltage, the fourth voltage terminal V 4 provides a high level voltage, and the seventh transistor M 7 is turned on. Therefore, only one of the seventh transistor M 7 and the tenth transistor M 10 is in an ON state. This can avoid performance drift caused by long-term conduction of transistor.

When the seventh transistor M 7 is turned on, the first pull-up node QB_A can be charged via the third voltage V 3 . When the tenth transistor M 10 is turned on, the second pull-up node QB_B can be charged via the fourth voltage V 4 . Therefore pulling the voltage of the first pull-up node QB_A or the second pull-up node QB_B can be controlled to a low level. When the voltage of the pull-down node Q is at a low level, the eighth transistor M 8 and the eleventh transistor M 11 are turned on. For example, in the design for the transistors, the seventh transistor M 7 and the eighth transistor M 8 may be configured (for example, by setting the size ratio, the threshold voltage, or the like, of the two transistors) such that when both M 7 and M 8 are turned on, the voltage of the first pull-up node QB_A can be pulled up to a high level, which can maintain the twentieth transistor M 20 , the twenty-third transistor M 23 , and the twenty-sixth transistor M 26 in an OFF state. On the other hand, the tenth transistor M 10 and the eleventh transistor M 11 may be configured (for example, by setting the size ratio, the threshold voltage, or the like, of the two transistors) such that when both M 10 and M 11 are turned on, the voltage of the second pull-up node QB_B may be pulled up to a high level, which can maintain the twenty-first transistor M 21 , the twenty-fourth transistor M 24 , and the twenty-seventh transistor M 27 in an OFF state.

As shown in FIGS. 3 A and 3 B , the pull-up circuit 700 includes a ninth transistor M 9 , a twentieth transistor M 20 , a twenty-third transistor M 23 , a twelfth transistor M 12 , a twenty-first transistor M 21 , a twenty-fourth transistor M 24 , a twenty-sixth transistor M 26 , and a twenty-seventh transistor M 27 .

A control electrode of the ninth transistor M 9 is coupled to the first pull-up node QB_A, a first electrode of the ninth transistor M 9 is coupled to the pull-down node Q, and a second electrode of the ninth transistor M 9 is coupled to the second voltage terminal V 2 . A control electrode of the twentieth transistor M 20 is coupled to the first pull-up node QB_A, a first electrode of the twentieth transistor M 20 is coupled to the shift signal output terminal CR, and a second electrode of the twentieth transistor M 20 is coupled to the second voltage terminal V 2 . A control electrode of the twenty-third transistor M 23 is coupled to the first pull-up node QB_A, a first electrode of the twenty-third transistor M 23 is coupled to the first drive signal output terminal OUT 1 , and a second electrode of the twenty-third transistor M 23 is coupled to the second voltage terminal V 2 . A control electrode of the twenty-sixth transistor M 26 is coupled to the first pull-up node QB_A, a first electrode of the twenty-sixth transistor is coupled to the second drive signal output terminal OUT 2 , and a second electrode of the twenty-sixth transistor is coupled to the second voltage terminals V 2 . In an embodiment, when the voltage of the first pull-up node QB_A is at a low level, the ninth transistor M 9 , the twentieth transistor M 20 , the twenty-third transistor M 23 , and the twenty-sixth transistor are turned on, such that the pull-down node Q, the shift signal output terminal CR, the first drive signal output terminal OUT 1 , and the second drive signal output terminal OUT 2 are pulled up.

A control electrode of the twelfth transistor M 12 is coupled to the second pull-up node QB_B, a first electrode of the twelfth transistor M 12 is coupled to the pull-down node Q, and a second electrode of the twelfth transistor M 12 is coupled to the second voltage terminal V 2 . A control electrode of the twenty-first transistor M 21 is coupled to the second pull-up node QB_B, a first electrode of the twenty-first transistor M 21 is coupled to the shift signal output terminal CR, and a second electrode of the twenty-first transistor M 21 is coupled to the second voltage terminal V 2 . A control electrode of the twenty-fourth transistor M 24 is coupled to the second pull-up node QB_B, a first electrode of the twenty-fourth transistor M 24 is coupled to the first drive signal output terminal OUT 1 , and a second electrode of the twenty-fourth transistor M 24 is coupled to the second voltage terminal V 2 . A control electrode of the twenty-seventh transistor M 27 is coupled to the second pull-up node QB_B, a first electrode of the twenty-seventh transistor is coupled to the second drive signal output terminal OUT 2 , and a second electrode of the twenty-seventh transistor is coupled to the second voltage terminals V 2 . In an embodiment, when the voltage of the second pull-up node QB_B is at a low level, the twelfth transistor M 12 , the twenty-first transistor M 21 , the twenty-fourth transistor M 24 , and the twenty-seventh transistor M 27 are turned on, such that the pull-down node Q, the shift signal output terminal CR, the first drive signal output terminal OUT 1 , and the second drive signal output terminal OUT 2 are pulled up.

It can be understood that when the pull-up node QB only includes the first pull-up node QB_A (or the second pull-up node QB_B), the pull-up circuit 700 may include the ninth transistor M 9 , the twentieth transistor M 20 , the twenty-third transistor M 23 , and the twenty-sixth transistor (or, the twelfth transistor M 12 , the twenty-first transistor M 21 , the twenty-fourth transistor M 24 , and the twenty-seventh transistor M 27 ). The specific circuit structure is the same and will not be repeated here.

As shown in FIGS. 3 A and 3 B , the second control circuit 800 may include a thirteenth transistor M 13 , a fourteenth transistor M 14 , a fifteenth transistor M 15 , a sixteenth transistor M 16 , a seventeenth transistor M 17 , and an eighteenth transistor M 18 .

A control electrode of the thirteenth transistor M 13 is coupled to the first clock signal terminal to receive the first clock signal CLKA, and a first electrode of the thirteenth transistor M 13 is coupled to the first pull-up node QB_A. A control electrode of the fourteenth transistor M 14 is coupled to the first control node H, a first electrode of the fourteenth transistor M 14 is coupled to a second electrode of the thirteenth transistor M 13 , and a second electrode of the fourteenth transistor M 14 is coupled to the second voltage terminals V 2 . A control electrode of the fifteenth transistor M 15 is coupled to the display input signal terminal to receive the display input signal STU 2 . A first electrode of the fifteenth transistor M 15 is coupled to the first pull-up node QB_A, and a second electrode of the fifteenth transistor M 15 is coupled to the second voltage terminal to receive the second voltage V 2 . In an embodiment, when the voltages of the first clock signal CLKA and the first control node H are both at a low level, the second voltage can be provided to the first pull-up node QB_A. In addition, when the display input signal STU 2 is at a low level, the second voltage can be provided to the first pull-up node QB_A.

A control electrode of the sixteenth transistor M 16 is coupled to the first clock signal terminal to receive the first clock signal CLKA, and a first electrode of the sixteenth transistor M 16 is coupled to the second pull-up node QB_B. A control electrode of the seventeenth transistor M 17 is coupled to the first control node H, a first electrode of the seventeenth transistor M 17 is coupled to a second electrode of the sixteenth transistor M 16 , and a second electrode of the seventeenth transistor M 17 is coupled to the second voltage terminal to receive the second voltage V 2 . A control electrode of the eighteenth transistor M 18 is coupled to the display input signal terminal to receive the display input signal STU 2 . A first electrode of the eighteenth transistor M 18 is coupled to the second pull-up node QB_B, and a second electrode of the eighteenth transistor M 18 is coupled to the second voltage terminal to receive the second voltage V 2 . In an embodiment, when the voltages of the first clock signal CLKA and the first control node H are both at a low level, a second voltage can be provided to the second pull-up node QB_B. In addition, when the display input signal STU 2 is at a low level, the second voltage can be provided to the second pull-up node QB_B.

It can be understood that when the pull-up node QB only includes the first pull-up node QB_A (or the second pull-up node QB_B), the pull-up circuit 700 may include the thirteenth transistor M 13 , the fourteenth transistor M 14 , and the fifteenth transistor M 15 (or, the sixteenth transistor M 16 , the seventeenth transistor M 17 , and the eighteenth transistor M 18 ). The specific circuit structure is the same and will not be repeated here.

In addition, as shown in FIGS. 3 A and 3 B , the reset circuit 900 may include a fifth transistor M 5 and a sixth transistor M 6 . A control electrode of the fifth transistor M 5 is coupled to the blanking reset signal terminal to receive the blanking reset signal TRST, a first electrode of the fifth transistor M 5 is coupled to the pull-down node Q, and a second electrode of the fifth transistor M 5 is coupled to the second voltage terminal to receive the second voltage V 2 . In an embodiment, when the blanking reset signal TRST is at a low level, the fifth transistor M 5 is turned on, such that the second voltage V 2 can be provided to the pull-down node Q. A control electrode of the sixth transistor M 6 is coupled the display reset signal terminal to receive the display reset signal STD. A first electrode of the sixth transistor M 6 is coupled to the pull-down node Q. A second electrode of the sixth transistor M 6 is coupled to the second voltage terminal V 2 . In an embodiment, when the display reset signal STD is at a low level, the sixth transistor M 6 is turned on, such that the second voltage V 2 can be provided to the pull-down node Q.

It can be understood that the respective circuit in the shift register in the embodiment of the present disclosure is not limited to the above circuit structure. Some circuit modifications are described schematically below with reference to the accompanying drawings. The modifications are not limitative.

FIGS. 4 A, 4 B, and 4 C show exemplary circuit diagrams of the display input circuit 410 , the display input circuit 420 , and the display input circuit 430 , respectively, according to embodiments of the present disclosure.

As shown in FIG. 4 A , the display input circuit 410 may include a fourth transistor M 4 and a fourth leakage-preventive transistor M 4 _b. A control electrode and a first electrode of the fourth transistor M 4 and a control electrode of the fourth leakage-preventive transistor M 4 _b are coupled to the display input signal terminal to receive the display input signal STU 2 . A second electrode of the fourth transistor M 4 is coupled to a first electrode of the fourth leakage-preventive transistor M 4 _b. A second electrode of the fourth leakage-proof transistor M 4 _b is coupled to the pull-down node Q.

As shown in FIG. 4 B , the display input circuit 420 may include a fourth transistor M 4 and a fourth leakage-preventive transistor M 4 _b. A control electrode of the fourth transistor M 4 is coupled to the display input signal terminal to receive the display input signal STU 2 . A first electrode of the fourth transistor M 4 is coupled to the first voltage terminal to receive the first voltage V 1 . A control electrode and a first electrode of the fourth leakage preventive transistor M 4 _b are coupled to a second electrode of the fourth transistor M 4 , and a second electrode of the fourth transistor M 4 is coupled to the pull-down node Q.

As shown in FIG. 4 C , the display input circuit 430 may include a fourth transistor M 4 . A control electrode and a first electrode of the fourth transistor are coupled to the display input signal terminal to receive the display input signal STU 2 . A second electrode of the fourth transistor is coupled to the pull-down node Q.

FIGS. 5 A and 5 B show an exemplary circuit diagram of a second control circuit 800 , respectively, according to an embodiment of the present disclosure.

As shown in FIG. 5 A , the second control circuit 810 includes a thirteenth transistor M 13 , a fifteenth transistor M 15 , a sixteenth transistor M 16 , and an eighteenth transistor M 18 . A control electrode of the thirteenth transistor M 13 is coupled to the first clock signal terminal CLKA, a first electrode of the thirteenth transistor M 13 is coupled to the first pull-up node QB_A, and a second electrode of the thirteenth transistor M 13 is coupled to the second voltage terminal V 2 . A control electrode of the fifteenth transistor M 15 is coupled to the display input signal terminal STU 2 , a first electrode of the fifteenth transistor M 15 is coupled to the first pull-up node QB_A, and a second electrode of the fifteenth transistor M 15 is coupled to the second voltage terminal V 2 . A control electrode of the sixteenth transistor M 16 is coupled to the first clock signal terminal CLKA, a first electrode of the sixteenth transistor M 16 is coupled to the second pull-up node QB_B, and a second electrode of the sixteenth transistor M 16 is coupled to the second voltage terminal V 2 . A control electrode of the eighteenth transistor M 18 is coupled to the display input signal terminal, a first electrode of the eighteenth transistor M 18 is coupled to the second pull-up node QB_B, and a second electrode of the eighteenth transistor M 18 is coupled to the second voltage terminal V 2 . Compared with the second control circuit 800 of the shift register 20 in FIGS. 3 A and 3 B , the second control circuit 810 does not include the fourteenth transistor M 14 and the seventeenth transistor M 17 .

As shown in FIG. 5 B , the second control circuit 820 includes a fifteenth transistor M 15 and an eighteenth transistor M 18 . A control electrode of the fifteenth transistor M 15 is coupled to the display input signal terminal STU 2 , a first electrode of the fifteenth transistor M 15 is coupled to the first pull-up node QB_A, and a second electrode of the fifteenth transistor M 15 is coupled to the second voltage terminal V 2 . A control electrode of the eighteenth transistor M 18 is coupled to the display input signal terminal, a first electrode of the eighteenth transistor M 18 is coupled to the second pull-up node QB_B, and a second electrode of the eighteenth transistor M 18 is coupled to the second voltage terminal V 2 . Compared with the second control circuit 800 of the shift register 20 in FIGS. 3 A and 3 B , the second control circuit 820 does not include the thirteenth transistor M 13 , the fourteenth transistor M 14 , the sixteenth transistor M 16 , and the seventeenth transistor M 17 .

FIGS. 6 A and 6 B illustrate an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure. The difference between the shift register shown in FIGS. 6 A and 6 B and the shift register in FIGS. 3 A and 3 B is that the second control circuit 800 is replaced with the second control circuit 810 , and a first leakage-preventive transistor M 1 _b, a third leakage-preventive transistor M 3 _b, a fifth leakage-preventive transistor M 5 _b, a sixth leakage-preventive transistor M 6 _b, a ninth leakage-preventive transistor M 9 _b, a twelfth leakage-preventive transistor M 12 _b, a twenty-eighth transistor M 28 , and a twenty-ninth transistor M 29 are added. Working principle of leakage prevention will be described below using the first leakage-preventive transistor M 1 _b as an example.

A control electrode of the first leakage-preventive transistor M 1 _b is coupled to the second clock signal terminal CLKB, a first electrode of the first leakage-preventive transistor M 1 _b is coupled to a second electrode of the twenty-eighth transistor M 28 , and a second electrode of the first leakage-preventive transistor M 1 _b is coupled to the first control node H. A control electrode of the twenty-eighth transistor M 28 is coupled to the first control node H, and a first electrode of the twenty-eighth transistor M 28 is coupled to the fifth voltage terminal V 5 to receive a fifth voltage at a low level. When the first control node H is at a low level, the twenty-eighth transistor M 28 is turned on under the control of the voltage of the first control node H. Therefore, a low-level signal from the fifth voltage terminal V 5 can be input to the first electrode of the leakage-preventive transistor M 1 _b, such that both the first electrode and the second electrode of the first leakage-preventive transistor M 1 _b are in a low-level state, preventing the charge at the first control node H from leaking through the first leakage-preventive transistor M 1 _b. In this case, since the control electrode of the first leakage-preventive transistor M 1 _b and the control electrode of the first transistor M 1 are coupled, the combination of the first transistor M 1 and the first leakage-preventive transistor M 1 _b can achieve the same function as the first transistor M 1 discussed above, while it can also preventing leakage of charge.

Similarly, the third leakage-preventive transistor M 3 _b, the fifth leakage-preventive transistor M 5 _b, the sixth leakage-preventive transistor M 6 _b, the ninth leakage-preventive transistor M 9 _b, and the twelfth leakage-preventive transistor M 12 _b can be combined, respectively, with the twenty-ninth transistor M 29 to achieve leakage prevention structure, thereby preventing leakage of charge at the pull-down node Q. The working principle of preventing charge leakage of the pull-down node Q is the same as the above-mentioned working principle of preventing charge leakage of the first control node H. Details can be omitted herein.

As shown in FIG. 6A, the blanking pull-down circuit 310 may include the third transistor M3 and the third leakage-preventive transistor M3_b. A control electrode of the third transistor M3 is coupled to the first clock signal terminal CLKA, a first electrode of the third transistor M3 is coupled to the second control node N, and a second electrode of the third transistor M3 is coupled to a first electrode of the third leakage-preventive transistor M3_B. A control electrode of the third leakage-preventive transistor M3_b is coupled to the first clock signal terminal CLKA, and a second electrode of the third leakage-preventive transistor M3_b is counted to the pull-down node Q.

A control electrode of the twenty-ninth transistor M29 is coupled to the pull-down node Q, a first electrode of the twenty-ninth transistor M29 is coupled to the first voltage terminal V1, and a second electrode of the twenty-ninth transistor M29 is coupled to the second electrode of the third transistor M3.

Embodiments of the present disclosure also provide a gate driving circuit including a shift register. As shown in FIG. 7 , the gate driving circuit 30 may include multiple (for example, N) cascaded shift registers. Any one or more of the shift registers may adopt the shift register provided by the embodiments of the present disclosure, for example, the structure of the shift register 10 or the shift register 20 or a modification thereof. It can be noted that FIG. 7 only schematically illustrates the first four stages of the shift register (A 1 , A 2 , A 3 , and A 4 ) of the gate driving circuit 30 .

As shown in FIG. 7 , a blanking input signal terminal STU 1 and a display input signal terminal STU 2 of the first-stage shift register A 1 and a display input signal terminal STU 2 of the second-stage shift register A 2 respectively receives an input signal STU. Otherwise, a blanking input signal terminal STU 1 of the shift register at the (i+1) th stage is coupled to a shift signal output terminal CR of the shift register at the i th stage. A display input signal terminal STU 2 of the shift register at the (i+2) th stage is coupled to the shift signal output terminal CR of the shift register at the i th stage. In addition to the shift registers at the last three stages, a display reset signal terminal STD of the shift register at the i th stage is connected to the shift signal output terminal CR of the shift register at the (i+3) th stage. Furthermore, a blanking reset signal terminal TRST of each of the shift registers is coupled to the blanking reset signal line TRST.

In an embodiment, the gate driving circuit 30 may further include a first sub-clock signal line CLK_ 1 and a second sub-clock signal line CLK_ 2 . As shown in FIG. 7 , a first clock signal terminal CLKA of each of the shift registers is coupled to the first sub-clock signal line CLK_ 1 . A second clock signal terminal CLKB of each of the shift registers is coupled to the second sub-clock signal line CLK_ 2 .

As shown in FIG. 7 , the gate driving circuit 30 may further include a third sub-clock signal line CLKD_ 1 , a fourth sub-clock signal line CLKD_ 2 , a fifth sub-clock signal line CLKD_ 3 , and a sixth sub-clock signal line CLKD_ 4 . In the case where the shift register includes a fourth clock signal terminal CLKD, a fourth clock signal terminal CLKD of the shift register at the (4i−3) th stage is coupled to the third sub-clock signal line CLKD_ 1 , a fourth clock signal terminal CLKD of the shift register at the (4i−2) th stage is coupled to the fourth sub-clock signal line CLKD_ 2 , a fourth clock signal terminal CLKD of the shift register at the (4i−1) th stage is coupled to the fifth sub-clock signal line CLKD_ 3 , and a fourth clock signal terminal CLKD of the shift register at the (4i) th stage is coupled to the sixth sub-clock signal line CLKD_ 4 . For example, the third sub-clock signal line CLKD_ 1 provides the fourth clock signal to the first-stage shift register, the fourth sub-clock signal line CLKD_ 2 provides the fourth clock signal to the second-stage shift register, the fifth sub-clock signal line CLKD_ 3 provides the fourth clock signal to the third-stage shift register, and the sixth sub-clock signal line CLKD_ 4 provides the fourth clock signal to the fourth-stage shift register.

In addition, the gate driving circuit 30 may further include a seventh sub-clock signal line CLKE_ 1 , an eighth sub-clock signal line CLKE_ 2 , a ninth sub-clock signal line CLKE_ 3 , and a tenth sub-clock signal line CLKE_ 4 . In the case where the shift register includes a fifth clock signal terminal CLKE, a fifth clock signal terminal CLKE of the shift register at the (4i−3) th stage is coupled to the seventh sub-clock signal line CLKE_ 1 , a fifth clock signal terminal CLKE of the shift register at the (4i−2) th stage is coupled to the seventh sub-clock signal line CLKE_ 2 , a fifth clock signal terminal CLKE of the shift register at the (4i−1) th stage is coupled to the ninth sub clock signal line CLKE_ 3 , and a fifth clock signal terminal CLKE of the shift register at the (4i) th stage is coupled to the tenth sub-clock signal line CLKE_ 4 . For example, the seventh sub-clock signal line CLKE_ 1 provides the fifth clock signal to the first-stage shift register, the eighth sub-clock signal line CLKE_ 2 provides the fifth clock signal to the second-stage shift register, and the ninth sub-clock signal line CLKE_ 3 provides the fifth clock signal to the third-stage shift register provides, and the tenth sub-clock signal line CLKE_ 4 provides the fifth clock signal to the fourth-stage shift register.

The working process of the gate driving circuit 30 shown in FIG. 7 are described below with reference to the schematic signal timing diagram in FIG. 8 . The shift register in the gate driving circuit 30 can be, for example, the shift register shown in FIGS. 3 A and 3 B .

FIG. 8 shows a schematic diagram for illustrating signal timing sequence for the gate driving circuit 30 shown in FIG. 7 for sequential compensation. In FIG. 9 , 1 F and 2 F indicate the first frame and the second frame, respectively. Display indicates the display period in a frame, and Blank indicates the blanking period in a frame.

The signal STU represents the input signal STU. TRST indicates a signal provided to the blanking reset signal line TRST. The signals V 3 and V 4 represent signals provided to the third voltage terminal and the fourth voltage terminal of the shift register in the gate driving circuit 30 , respectively. The signals CLK_ 1 and CLK_ 2 represent signals provided to the first sub-clock signal line CLK_ 1 and the second sub-clock signal line CLK_ 2 , respectively. The signals CLKD_ 1 , CLKD_ 2 , CLKD_ 3 , and CLKD_ 4 respectively represent signals provided to the third sub-clock signal line CLKD_ 1 , the fourth sub-clock signal line CLKD_ 2 , the fifth sub-clock signal line CLKD_ 3 , and the sixth sub-clock signal line CLKD_ 4 . The signals CLKE_ 1 , CLKE_ 2 , CLKE_ 3 , and CLKE_ 4 respectively represent signals provided to the seventh sub-clock signal line CLKE_ 1 , the eighth sub-clock signal line CLKE_ 2 , the ninth sub-clock signal line CLKE_ 3 , and the tenth sub-clock signal line CLKE_ 4 .

H < 1 > and H < 2 > represent the voltages of the first control nodes H in the first-stage shift register A 1 and the second-stage shift register A 2 in the gate driving circuit 30 , respectively. N < 1 > and N < 2 > represent the voltages of the second control nodes N in the first-stage shift register A 1 and the second-stage shift register A 2 , respectively. Q < 1 > and Q < 2 > represent the voltages of the pull-down nodes Q in the first-stage shift register A 1 and the second-stage shift register A 2 in the gate driving circuit 30 , respectively. OUT 1 < 1 >, OUT 1 < 2 >, OUT 1 < 3 >, and OUT 1 < 4 > represent the first drive signal output terminals OUT 1 of the first-stage shift register A 1 , the second-stage shift register A 2 , the third-stage shift register A 3 , and the fourth-stage shift register A 4 in the gate driving circuit 30 , respectively. OUT 2 < 1 > and OUT 2 < 2 > represent the second drive signal output terminals OUT 2 of the first-stage shift register A 1 and the second-stage shift register A 2 in the gate driving circuit 30 , respectively. It can be noted that as the voltages of the shift signal output terminal CR and the drive signal output terminal OUT 1 in each of the shift registers are the same, the shift signal output terminal CR is not shown in FIG. 8 .

It can be noted that the voltage level of the signals in the signal timing diagram shown in FIG. 8 are only schematic and do not represent the real values of the voltage level.

The working principle of the gate driving circuit 30 shown in FIG. 7 can be described below in conjunction with the signal timing diagram in FIG. 8 , in which the gate driving circuit 30 is configured for line-by-line sequential compensation. For example, the shift register in the gate driving circuit 30 in FIG. 7 may be implemented with the shift register shown in FIGS. 3 A and 3 B .

Before the start of the first frame 1 F, the blanking reset signal line TRST and the second sub-clock signal line CLK_ 2 both provide a low level voltage, to provide the blanking reset signal terminal TRST and the second clock signal terminal CLKB of the shift registers at each stage. Therefore, the first transistor M 1 and the fifth transistor M 5 in each of the shift registers can be turned on. The blanking input signal STU 1 (i.e., the input signal STU at a high level) is provided to the first control node H, such that the voltage of the first control node H is at a high level. The second voltage V 2 (at a high level) is provided to the pull-down node Q, such that the voltage of the pull-down node Q is at a high level. As a result, the first control node H and the pull-down node Q at each stage are reset, implementing a global reset.

Then, the first frame 1 F starts, the third voltage V 3 is at a high level, and the fourth voltage V 4 is at a low level. The signal provided by the blanking reset signal line TRST changes to high level, thus the fifth transistor M 5 is turned off.

In the display period Display of the first frame 1 F, the working process of the shift register at the first stage A 1 is described as follows.

In the first period (1), the blanking input signal terminal STU 1 and the display input signal terminal STU 2 of the first-stage shift register are both coupled to the input signal line STU, such that the blanking input signal terminal STU 1 and the display input signal terminal STU 2 both provide low level signals. The second clock signal terminal CLKB provides a low-level signal, such that the first transistor M 1 is turned on, thereby providing the blanking input signal STU 1 to the first control node H < 1 >. In this case, the voltage of the first control node H < 1 > is at a low level, the first clock signal CLKA (coupled to the first sub-clock signal line CLK_ 1 ) is at a high level. Thus, the second transistor M 2 is turned on, to provide the first clock signal CLKA to the second control node N < 1 >, such that the voltage of the second control node N < 1 > is at a high level. In addition, because the first clock signal CLKA is at a high level, the third transistor M 3 is turned off, to isolate the first control node H < 1 > and the second control node N < 1 > from the pull-down node Q < 1 >. The first capacitor C 1 maintains the voltage difference between the first control node H < 1 > and the second control node N < 1 > until the blanking period.

On the other hand, the fourth voltage V 4 is at a low level. Thus the tenth transistor M 10 is turned on to control the voltage of the control electrode of the twelfth transistor M 12 to be a low level. Therefore, the twelfth transistor M 12 is turned on, to provide the second voltage V 2 to the pull-down node Q < 1 >, such that the voltage of the pull-down node Q < 1 > is at a high level. Because the display input signal STU 2 is at a low level in the first period, the fourth transistor M 4 is turned on, to provide the first voltage V 1 to the pull-down node Q < 1 >, such that the voltage of the pull-down node Q < 1 > is at a low level. Therefore, the eighth transistor M 8 and the eleventh transistor M 11 are turned on, such that the first pull-up node QB_A and the second pull-up node QB_B are pulled high. Further, the pull-down node Q < 1 > is at a low level, such that the nineteenth transistor M 19 , the twenty-second transistor M 22 , and the twenty-fifth transistor M 25 are turned on, to provide, respectively, the fourth clock signal CLKD (coupled to the third sub-clock signal line CLKD_ 1 ) and the fifth clock signal CLKE (coupled to the seventh sub-clock signal line CLKE_ 1 ) to the shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminals OUT 2 < 1 >, thereby outputting high-level signals respectively.

Moreover, as the display input signal STU 2 is at a low level, the fifteenth transistor M 15 and the eighteenth transistor M 18 are turned on, to provide the second voltage V 2 at a high-level to the first pull-up node QB_A and the second pull-up node, respectively QB_B. Therefore, the first pull-up node QB_A and the second pull-up node QB_B can be pulled-up accordingly.

In the second period (2), a low-level signal can be provided to the fourth clock signal terminal CLKD via the third sub-clock signal line CLKD_ 1 . A low-level signal can be provided to the fifth clock signal terminal CLKE via the seventh sub-clock signal line CLKE_ 1 . The voltage of the pull-down node Q < 1 > can be further pulled down due to the bootstrap effect for the second capacitor C 2 . The nineteenth transistor M 19 , the twenty-second transistor M 22 , and the twenty-fifth transistor M 25 are maintained in an ON state, such that the shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 > output low-level signals respectively. For example, the low-level signal from the shift signal output terminal can be configured for scanning shift of the upper to lower shift registers. Therefore, the low-level signal from the two drive signal output terminals can be configured to drive the sub-pixels in the display panel for display.

In the third period (3), the pull-down node Q < 1 > remains at low. Therefore, the nineteenth transistor M 19 , the twenty-second transistor M 22 , and the twenty-fifth transistor M 25 remain in the ON state. A high-level signal is provided to the fourth clock signal terminal CLKD via the third sub-clock signal line CLKD_ 1 . Moreover, a high-level signal is provided to the fifth clock signal terminal CLKE via the seventh sub-clock signal line CLKE_ 1 . Therefore, the shift signal output terminals CR, the first drive signal output terminal OUT 1 , and the second drive signal output terminal OUT 2 output high-level signals respectively. Because the shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 > are reset to a high level, the voltage of the pull-down node Q < 1 > may rise by a magnitude due to the coupling effect between the transistors. Moreover, as the display reset signal terminal STD of the first stage shift register A 1 is coupled to the shift signal output terminal CR < 4 > (i.e., OUT 1 < 4 >) of the fourth stage shift register A 4 , and the shift signal output terminal CR < 4 > of the fourth stage shift register A 4 has not yet output a low-level signal, thus the pull-down node Q < 1 > may not be pulled up. Therefore, the pull-down node Q < 1 > can be maintained at a lower level.

In the fourth period (4), the shift signal output terminal CR < 4 > of the fourth-stage shift register A 4 outputs a low-level signal, to provide a low-level signal to the display reset signal terminal STD of the first-stage shift register A 1 . In this case, the sixth transistor M 6 is turned on, and the voltage of the pull-down node Q < 1 > becomes a high level. That is, the pull-down node Q < 1 > can be reset. Further, as the voltage of the pull-down node Q < 1 > is at a high level, the eleventh transistor M 11 is turned off, and the voltage of the second pull-up node QB_B is pulled down to a low level via the tenth transistor M 10 . Hence, the twelfth transistor M 12 is turned on, to eliminate the noise of the pull-down node Q < 1 >. In addition, the twenty-first transistor M 21 , the twenty-fourth transistor M 24 , and the twenty-seventh transistor M 27 are turned on to provide the second voltage V 2 to the shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 >, thereby outputting high-level signals, respectively.

In the display period of the first frame described above, as the first clock signal CLKA has been maintained at a low level, the third transistor M 3 is turned off. The third transistor M 3 can isolate the influence of the voltage at the first control node H < 1 > and the second control node N < 1 > on the pull-down node Q < 1 > in the display period.

After the shift register at the first stage drives the sub-pixels in the first row of the display panel to display, the shift registers at the second stage, the third stage, and the like, may drive the sub-pixels in the display panel row by row for the display drive of one frame. Then, the display period of the first frame ends.

At the beginning of the display period (Display), the first control node H < 1 > is written as a low level and is maintained until the blanking period (Blank). The second transistor is turned on, while the first clock signal CLKA is at a high level, therefore, the second control node N < 1 > is written as a high level and is maintained until the blanking period (Blank).

In the blanking period (Blank) of the first frame 1 F, the working process of the shift register at the first stage A 1 is described as follows.

In the fifth period (5), the first sub-clock signal line CLK_ 1 provides a low-level signal to the first clock signal CLKA, the first control node H < 1 > is maintained as low level, and the second transistor M 2 is turned on. The first clock signal CLKA is provided to the second control node N < 1 >, such that the voltage of the second control node N < 1 > changes to a low level. As the first capacitor C 1 maintains the voltage difference between the first control node H < 1 > and the second control node N < 1 >, the voltage of the first control node H < 1 > is correspondingly reduced. Therefore, the first clock signal CLKA is provided to the second control node N < 1 > without loss, such that the voltage of the second control node N < 1 > can reach the lowest potential of the first clock signal CLKA, thereby achieving lossless outputting. Moreover, the third transistor M 3 is turned on, to provide the voltage of the second control node N < 1 > (the lossless first clock signal CLKA) to the pull-down node Q < 1 >, such that the voltage of the pull-down node Q < 1 > changes to a low level. During this period, the fourth clock signal CLKD and the fifth clock signal terminal CLKE are both high-level signals, such that the shift signal output terminal CR, the first drive signal output terminal OUT 1 , and the second drive signal output terminal OUT 2 output high level signal, respectively.

In the sixth period (6), the first sub-clock signal line CLK_ 1 provides a high-level signal to the first clock signal CLKA. The voltage of the second control node N < 1 > changes to a high level. The voltage difference held by the first capacitor C 1 causes the voltage of the first control node H < 1 > to rise accordingly.

In the seventh period (7), the second sub-clock signal line CLK_ 2 provides a low-level signal to the second clock signal CLKB. The first transistor M 1 is turned on, to provide the blanking input signal STU 1 at a high-level to the first control node H < 1 >, to pull the corresponding voltage up to a high level. The second transistor M 2 is turned off, and the voltage of the second control node N < 1 > is held unchanged.

The third transistor M 3 is turned off. The fourth clock signal CLKD and the fifth clock signal CLKE are low-level signals. The shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 > output low-level signal, respectively. With the function of the second capacitor C 2 and the third capacitor C 3 , the voltage of the pull-down node Q < 1 > can be further pulled down.

Moreover, because the second clock signal CLKB is at a low level, the first transistor M 1 in the shift register at the second stage A 2 is turned on. The blanking input signal STU 1 < 2 > of the shift register at the second stage A 2 is coupled to the shift signal output terminal CR < 1 > of the shift register at the first stage A 1 . Therefore, the voltage of the first control node H < 2 > in the second-stage shift register A 2 is reduced to a low level.

In the eighth period (8), the second sub-clock signal line CLK_ 2 provides a high-level signal to the second clock signal CLKB. The third sub-clock line CLKD_ 1 provides a low-level signal to the fourth clock signal terminal CLKD. The seventh sub-clock signal line CLKE_ 1 provides a high-level signal to the fifth clock signal terminal CLKE. In this case, the shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 > outputs a low-level signal, while the second drive signal output terminal OUT 2 < 1 > outputs a high-level signal. The first transistor M 1 in the second-stage shift register A 2 is turned off. The first control node H < 2 > remains at a low level until the blanking period BLANK for the next frame.

In the ninth period (9), the second clock signal CLKB remains at a high level. The fourth clock signal CLKD and the fifth clock signal CLKE are both at a low level. The shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 > output low-level signal, respectively.

From the above, during the 7-9th period of the blanking period, the first drive signal output terminal OUT 1 < 1 > outputs the first drive signal at low-level, to drive the sensing transistor (for example, P Type transistor). Therefore, the sensing transistors in the first row of sub-pixels can sense the driving current of the sub-pixels in the row, thereby compensating based on the sensed driving current.

In the tenth period (10), both the fourth clock signal CLKD and the fifth clock signal CLKE become high level. The shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 > output a high-level signal, respectively. Under the control of the second capacitor C 2 and the third capacitor C 3 , the voltage of the pull-down node Q rises.

In the eleventh period (11), the blanking reset signal line TRST provides a low-level signal to the blanking reset signal terminal TRST. The fifth transistor M 5 is turned on. The voltage of the pull-down node Q is at a high level. The fourth voltage is at a low level. The tenth transistor M 10 is turned on, such that the voltage of the second pull-up node QB_B is at a low level. Accordingly, the twenty-first transistor M 21 , the twenty-fourth transistor M 24 , and the twenty-seventh transistor M 27 are all turned on. Therefore, the shift signal output terminal CR < 1 >, the first drive signal output terminal OUT 1 < 1 >, and the second drive signal output terminal OUT 2 < 1 > respectively output high-level signals.

Then, a process for driving the gate driving circuit in more time periods such as a second frame 2 F, a third frame 3 F, or the like can be implemented with reference to the foregoing description. Details will not be described herein again.

As described above, during the blanking period of each frame, the blanking output signal from the gate driving circuit can be configured to drive the sensing transistors in the sub-pixels in the display panel. As shown in the figures, the drive signals are row-by-row sequentially provided. For example, during the blanking period of the first frame, the gate driving circuit outputs drive signals for the sub-pixels in the first row of the display panel. During the blanking period of the second frame, the gate driving circuit outputs drive signals for the sub-pixels in the second row of the display panel, and so on, thereby performing sequential compensation on a row-by-row basis.

On the other hand, an array substrate and a display device including the gate driving circuit 30 described above are also provided according to embodiments of the present disclosure. In the embodiments, the display device may include a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet, a notebook computer, a digital photo frame, a navigator, and any other product or component having a display function.

In addition, a method for driving a shift register is also provided according to embodiments of the present disclosure. FIG. 9 shows a schematic flowchart of a method for driving a shift register according to the embodiments of the present disclosure. The shift register may be any applicable shift register according to the embodiments of the present disclosure.

In a display period of a frame, in step 910 , under the control of a second clock signal CLKB from a second clock signal terminal, a blanking input signal STU 1 from a blanking input signal terminal is provided to a first control node H, and a voltage difference between the first control node H and a second control node N is maintained. For example, reference can be made to the description for the first period in FIG. 8 .

In an embodiment, a first voltage V 1 from a first voltage terminal may be provided to a pull-down node Q according to a display input signal STU 2 from a display input signal terminal. For example, reference can be made to the description for the second period in FIG. 8 .

Accordingly, a display output signal can be output according to a voltage of the pull-down node Q. For example, reference can be made to the description for the third period in FIG. 8 .

In addition, the pull-down node Q can be reset according to a display reset signal STD. For example, reference can be made to the description for the fourth period in FIG. 8 .

In a blank period of the frame, in step 920 , a first clock signal CLKA from a first clock signal terminal may be provided to the second control node N according to the voltage of the first control node H. Moreover, the voltage of the first control node H may be controlled via the voltage difference held according to the voltage of the second control node N. Therefore, the first clock signal CLKA can be output to the second control node N without any loss.

In step 930 , the voltage of the second control node N (that is, the lossless first clock signal CLKA) may be provided to the pull-down node Q according to the first clock signal CLKA.

For step 920 and step 930 , reference can be made to, for example, the description for the fifth period in FIG. 8 above.

Then, after the first clock signal CLKA changes, the second control node N receives the first clock signal CLKA, such that the voltage of the second control node N changes. Then the voltage of the first control node H may be controlled via the maintained voltage difference according to the voltage of the second control node N. For example, reference can be made to the description for the sixth period of FIG. 8 above.

In step 940 , a shift signal and a drive signal (such as a first drive signal and a second drive signal) are output according to the voltage of the pull-down node Q. Moreover, under the control of the second clock signal, the blanking input signal STU 1 from the blanking input signal terminal may be provided to the first control node H, such that the first clock signal may no longer be provided to the second control node N. Reference can be made to, for example, the description for periods 7-10 of FIG. 8 above.

Then, the pull-down node Q can also be reset according to a blanking reset signal TRST. For example, reference can be made to the description for the eleventh period in FIG. 8 .

Those skilled in the art can understand that while the above steps are described in order, they do not constitute a limitation on the order for the method. The embodiments of the present disclosure may also be implemented in any other suitable order. In an embodiment, the above steps may occur in different periods of the same frame, or may occur in different periods of different frames. For example, the first step may occur during the blanking period of the first frame, and other steps may occur during the display period and the blanking period of the second frame. There is no limitation for this aspect based on the present disclosure.

Several embodiments of the present disclosure have been described in detail above, but the scope of protection of the present disclosure is not limited thereto. It is apparent to those of ordinary skills in the art that various modifications, substitutions, or changes may be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.