Semiconductor Package Including Interposors and Electronic System

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2022-0082615, filed on Jul. 5, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

A semiconductor package may include a plurality of interposers and an electronic system including the same.

Recently, semiconductor packages using an interposer and including a plurality of semiconductor chips have been developed in accordance with demand for high performance and high integration of semiconductor packages.

SUMMARY

Example embodiments provide a semiconductor package having improved performance, while including a plurality of interposers and a plurality of semiconductor chip structures.

Example embodiments provide an electronic system including the semiconductor package.

According to example embodiments, an electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a first semiconductor chip structure on the first and second interposers and including a first circuit region and a second circuit region, and a second semiconductor chip structure on the first and second interposers and spaced apart from the first semiconductor chip structure. The second semiconductor chip structure includes a third circuit region configured to communicate with the first circuit region of the first semiconductor chip structure at a first rate through the first signal paths of the first interposer and a fourth circuit region configured to communicate with the second circuit region of the first semiconductor chip structure at a second rate, different from the first rate, through the second signal paths of the second interposer.

According to example embodiments, an electronic system includes a first interposer including first signal paths, a second interposer spaced apart from the first interposer and including second signal paths, a controller semiconductor chip on the first and second interposers, and a memory semiconductor chip on the first and second interposers and spaced apart from the controller semiconductor chip. The controller semiconductor chip is configured to communicate data with the memory semiconductor chip through the first signal paths of the first interposer, and the memory semiconductor chip is configured to receive a command and an address signal from the controller semiconductor chip through the second signal paths of the second interposer.

According to example embodiments, a semiconductor package includes a package substrate, a first interposer on the package substrate and including first signal paths, a second interposer on the package substrate, spaced apart from the first interposer, and including second signal paths, a first semiconductor chip structure on the first and second interposers, and at least one second semiconductor chip structure on the first and second interposers, electrically connected to the first semiconductor chip structure through the first signal paths, and electrically connected to the first semiconductor chip structure through the second signal paths. The number of the first signal paths is different from the number of the second signal paths.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the present inventive concept will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a diagram schematically illustrating an electronic system including a semiconductor package according to some embodiments of the present inventive concept;

FIG. 2 is a top view schematically illustrating a semiconductor package according to some embodiments of the present inventive concept;

FIGS. 3 A to 3 C are cross-sectional views schematically illustrating an example of a semiconductor package according to some embodiments of the present inventive concept;

FIGS. 4 A and 4 B are cross-sectional views schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIGS. 5 A and 5 B are cross-sectional views schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 6 is a top view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 7 is a top view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIGS. 8 A and 8 B are cross-sectional views schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 9 is a top view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 10 is a cross-sectional view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 11 is a top view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 12 is a cross-sectional view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 13 is a cross-sectional view schematically illustrating a modified example of a semiconductor package according to some embodiments of the present inventive concept;

FIG. 14 is a diagram schematically illustrating a modified example of an electronic system including a semiconductor package according to some embodiments of the present inventive concept; and

FIGS. 15 and 16 are diagrams schematically illustrating a semiconductor package according to some embodiments of the present inventive concept.

DETAILED DESCRIPTION

The present inventive concept will be understood through the following examples in conjunction with the accompanying drawings. However, the present inventive concept is not limited to the embodiments described herein and may be embodied in other forms. In some embodiments, when it is mentioned that certain elements or lines are connected to a target region, it may include not only direct connection but also indirect connection via other elements. In addition, a connection relationship between regions and lines described with reference to the drawings in some embodiments is only shown for an effective description of the technical content, and some embodiments may further include other regions and other lines not shown in the drawings.

An electronic system according to some embodiments of the present inventive concept will be described with reference to FIG. 1 . FIG. 1 is a diagram schematically illustrating an electronic system according to some embodiments of the present inventive concept.

Referring to FIG. 1 , an electronic system 1 according to some embodiments may include a plurality of interposers INT and a plurality of semiconductor chip structures CH on the plurality of interposers INT.

The plurality of interposers INT may include a first interposer INT_ 1 and a second interposer INT_ 2 spaced apart from each other.

The first interposer INT_ 1 may include first signal paths SI_H.

The second interposer INT_ 2 may include second signal paths SI_L.

The first interposer INT_ 1 may further include first power/ground paths PW 1 adjacent the first signal paths SI_H. The first power/ground paths PW may include first power paths PWa and first ground paths PWb.

The second interposer INT_ 2 may further include second power/ground paths PW 2 adjacent the second signal paths SI_L. The second power/ground paths PW 2 may include second power paths PWc and second ground paths PWd.

The number of the first signal paths SI_H may be greater than the number of the second signal paths SI_L. For example, the number of the first signal paths SI_H may be about 1.5 times to about 1.8 times greater than the number of the second signal paths SI_L.

The plurality of semiconductor chip structures CH may include a first semiconductor chip structure CH_ 1 and a second semiconductor chip structure CH_ 2 that are spaced apart from each other.

The first semiconductor chip structure CH_ 1 may be on the first and second interposers INT_ 1 and INT_ 2 . The second semiconductor chip structure CH_ 2 may be on the first and second interposers INT_ 1 and INT_ 2 .

The electronic system 1 may further include a package substrate 3 . The plurality of interposers INT may be mounted on the package substrate 3 . The plurality of semiconductor chip structures CH may be mounted on the plurality of interposers INT.

The first semiconductor chip structure CH_ 1 may include at least one first semiconductor chip. The second semiconductor chip structure CH_ 2 may include at least one second semiconductor chip.

The at least one first semiconductor chip of the first semiconductor chip structure CH_ 1 and the at least one second semiconductor chip of the second semiconductor chip structure CH_ 2 may include circuit regions capable of communicating at different rates. For example, the first semiconductor chip structure CH_ 1 may include a first circuit region CR 1 and a second circuit region CR 2 , and the second semiconductor chip structure CH_ 2 may include a third circuit region CR 3 configured to communicate with the first circuit region CR 1 and a fourth circuit region CR 4 configured communicate with the second circuit region CR 2 .

The third circuit region CR 3 may be configured to communicate with the first circuit region CR 1 at a first rate through the first signal paths SI_H of the first interposer INT_ 1 . The fourth circuit region CR 4 may be configured to communicate with the second circuit region CR 2 at a second rate slower than the first rate through the second signal paths SI_L of the second interposer INT_ 2 .

The first signal paths SI_H may be referred to as ‘fast signal paths’, and the second signal paths SI_L may be referred to as ‘slow signal paths’.

The first semiconductor chip structure CH_ 1 may further include a first interface region IF 1 . As shown in FIG. 2 , the second semiconductor chip structure CH_ 2 may further include a second interface region IF 2 .

In another embodiment, the second interface region IF 2 of the second semiconductor chip structure CH_ 2 may be omitted.

The first semiconductor chip structure CH_ 1 may include a first semiconductor chip, and the second semiconductor chip structure CH_ 2 may include a second semiconductor chip including circuit regions configured to communicate with the first semiconductor chip at different rates. For example, the first semiconductor chip structure CH_ 1 may include a controller semiconductor chip, and the second semiconductor chip structure CH_ 2 may include at least one memory semiconductor chip. For example, the second semiconductor chip structure CH_ 2 may include a volatile memory semiconductor chip, such as a DRAM or a nonvolatile memory semiconductor chip, such as a flash memory.

The first semiconductor chip structure CH_ 1 , that is, the controller semiconductor chip, may be configured to communicate data with the second semiconductor chip structure CH_ 2 , that is, the memory semiconductor chip, through the first signal paths SI_H of the first interposer INT_ 1 at a high speed, and the second semiconductor chip structure CH_ 2 may receive command and address signals from the controller semiconductor chip CH_ 1 through the second signal paths SI_L of the second interposer INT_ 2 at a low speed. For example, the first circuit region CR 1 of the controller semiconductor chip CH 1 may be configured to communicate data with the third circuit region CR 3 of the memory semiconductor chip CH_ 2 at a first rate through the first signal paths SI_H of the first interposer INT_ 1 , and the fourth circuit region CR 4 of the memory semiconductor chip CH_ 2 may receive command and address signals from the second circuit region CR 2 of the controller semiconductor chip CH_ 1 at a second rate slower than the first rate through the second signal paths SI_L of the second interposer INT_ 2 .

The electronic system 1 may further include an electronic device 1000 electrically connected to the semiconductor package 10 by a system bus 1050 .

The electronic device 1000 may be a host, and may control general operations of the electronic system 1 . For example, a host interface between the electronic device 1000 and the first semiconductor chip structure CH_ 1 may include various protocols for exchanging data between the electronic device 1000 and the first semiconductor chip structure CH_ 1 . For example, the first semiconductor chip structure CH_ 1 may communicate with the electronic device 1000 or the outside through at least one of a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol, etc.

The electronic system 1 may be one of various components of a system, such as an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage constituting a data center, a device that may transmit and receive information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of the various components constituting a computing system.

Next, an example of the semiconductor package 10 will be described with reference to FIGS. 2 , 3 A, 3 B, and 3 C . FIG. 2 is a top view schematically illustrating the semiconductor package 10 of the electronic system 1 of FIG. 1 , and FIG. 3 A is a cross-sectional view schematically illustrating a region taken along line I-I′ of FIG. 2 to describe an example of the semiconductor package 10 of the electronic system 1 of FIG. 1 , FIG. 3 B is a cross-sectional view schematically illustrating a region taken along line II-IF of FIG. 2 to describe an example of the semiconductor package 10 of the electronic system 1 of FIG. 1 , and FIG. 3 C is a cross-sectional view schematically illustrating a region taken along lines and IV-IV′ of FIG. 2 to describe an example of the semiconductor package 10 of the electronic system 1 of FIG. 1 .

Referring to FIGS. 2 , 3 A, 3 B, and 3 C together with FIG. 1 , a semiconductor package according to an example embodiment may include the package substrate 3 , the plurality of interposers INT, and a plurality of chip structures CH as described above with reference to FIG. 1 .

In example embodiments, the package substrate 3 may include a substrate body 6 , lower pads 12 below the substrate body 6 , connection patterns 15 below the lower pads 12 and electrically connected to the lower pads 12 , upper pads 9 on the substrate body 6 , and an inner interconnection 18 electrically connecting the lower pads 12 to the upper pads 9 in the substrate body 6 . The connection patterns 15 may be solder balls including a solder material, such as SnAg or SaAgCu. The package substrate 3 may be a printed circuit board.

In example embodiments, the plurality of interposers INT may include a first interposer 20 a and a second interposer 20 b mounted on the package substrate 3 and spaced apart from each other. The first interposer 20 a may be the first interposer INT_ 1 of FIG. 1 , and the second interposer 20 b may be the second interposer INT_ 2 of FIG. 1 .

In example embodiments, each of the plurality of interposers INT may be a silicon interposer.

The first interposer 20 a may include the first signal paths SI_H and the first power/ground paths PW 1 described above with reference to FIG. 1 . The first interposer 20 a may further include a first substrate 23 a , a first lower insulating layer 25 a , a first upper insulating layer 27 a , first lower pads 29 a , first connection structures comprising a first interconnection structure 35 a and a first insulating structure 48 a , first conductive bumps 22 a , and first through-electrode structures 30 a . The first substrate 23 a may be formed of, for example, any one of a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the first substrate 23 a is a silicon substrate, the first interposer 20 a may be referred to as a silicon interposer. When the first substrate 23 a is an organic substrate, the first interposer 23 a may be referred to as a panel interposer.

The first lower insulating layer 25 a may cover a lower surface of the first substrate 23 a . The first lower pads 29 a may be below the first lower insulating layer 25 a . The first upper insulating layer 27 a may cover an upper surface of the first substrate 23 a.

Each of the first through-electrode structures 30 a may include a through-electrode 33 passing through the first substrate 23 a , the first lower insulating layer 25 a , and the first upper insulating layer 27 a and an insulating spacer 31 covering a side surface of the through-electrode 33 .

The first connection structures may include a first insulating structure 48 a on the first upper insulating layer 27 a and a first interconnection structure 35 a at least partially positioned in the first insulating structure 48 a.

The first interconnection structure 35 a may be electrically connected to the first through-electrode structures 30 a . At least a portion of the first interconnection structure 35 a may be on the same vertical level as that of the first signal paths SI_H and the first power/ground paths PW 1 . At least a portion of the first interconnection structure 35 a may be formed of the same conductive material as that of the first signal paths SI_H and the first power/ground paths PW 1 . The first signal paths SI_H and the first power/ground paths PW 1 may be in the first insulating structure 48 a.

At least a portion of the first interconnection structure 35 a may be on substantially the same vertical level as that of the first signal paths SI_H and the first power/ground paths PW 1 .

The first through-electrode structures 30 a and the first interconnection structure 35 a may be a first interface path electrically connected to the first interface region IF 1 .

The first interconnection structure 35 a may have a single-layer structure or a multilayer structure.

When the first interconnection structure 35 a has a multilayer structure, the first interconnection structure 35 a may include first lower pads 37 a electrically connected to the through-electrodes 33 of the first through-electrode structures 30 a , first upper pads 45 a on the first insulating structure 48 a , first interconnection lines 41 an in the first insulating structure 48 a , first lower vias 39 a between the first interconnection lines 41 a and the first lower pads 37 a , and first upper vias 42 a between the first interconnection lines 41 a and the first upper pads 45 a.

The first signal paths SI_H and the first power/ground paths PW 1 may include line portions on substantially the same vertical level as that of the first interconnection lines 41 a , via portions on substantially the same vertical level as that of the first upper vias 42 a , and pad portions on substantially the same vertical level as that of the first upper pads 45 a.

The second interposer 20 b may include the second signal paths SI_L and the second power/ground paths PW 2 described above with reference to FIG. 1 . The second signal paths SI_L may be on substantially the same vertical level as that of the first signal paths SI_H. The second interposer 20 b may further include a second substrate 23 b , a second lower insulating layer 25 b , a second upper insulating layer 27 b , second lower pads 29 b , second connection structures comprising a second interconnection structure 35 b and a second insulating structure 48 b , second conductive bumps 22 b , and second through-electrode structures 30 b . The second substrate 23 b may be formed of the same material as that of the first substrate 23 a . The second lower insulating layer 25 b may cover a lower surface of the second substrate 23 b . The second lower pads 29 b may be below the second lower insulating layer 25 b . The second upper insulating layer 27 b may cover an upper surface of the second substrate 23 b.

Each of the second through-electrode structures 30 b may include a through-electrode 33 passing through the second substrate 23 b , the second lower insulating layer 25 b , and the second upper insulating layer 27 b and an insulating spacer 31 covering a side surface of the through-electrode 33 .

The second connection structures may include a second insulating structure 48 b on the second upper insulating layer 27 b and a second interconnection structure 35 b at least partially positioned in the second insulating structure 48 b.

At least a portion of the second interconnection structure 35 b may be on substantially the same vertical level as the second signal paths SI_L and the second power/ground paths PW 2 .

The second through-electrode structures 30 b and the second interconnection structure may be a second interface path electrically connected to the first interface region IF 1 .

The second interconnection structure 35 b may have a single-layer structure or a multilayer structure.

When the second interconnection structure 35 b has a multilayer structure, the second interconnection structure 35 b may include second lower pads 37 b electrically connected to the through-electrodes 33 of the second through-electrode structures 30 b , second upper pads 45 b on the second insulating structure 48 b , second interconnection lines 41 b in the second insulating structure 48 b , second lower vias 39 b between the second interconnection lines 41 b and the second lower pads 37 b , and second upper vias 39 b between the second interconnection lines 41 b and the second upper pads 45 b.

The second signal paths SI_L and the second power/ground paths PW 2 may include line portions on substantially the same vertical level as that of some of the second interconnection lines 41 b , via portions on substantially the same vertical level as that of the second upper vias 42 b , and pad portions on substantially the same vertical level as that of the second upper pads 45 b . The plurality of semiconductor chip structures CH may include a first semiconductor chip structure 50 and a second semiconductor chip structure 70 spaced apart from each other. The first semiconductor chip structure 50 may be the first semiconductor chip structure CH_ 1 of FIG. 1 , and the second semiconductor chip structure 70 may be the second semiconductor chip structure CH_ 2 of FIG. 1 .

The first semiconductor chip structure 50 may include a first semiconductor chip including the first circuit region CR 1 and the second circuit region CR 2 as described above with reference to FIG. 1 , and the second semiconductor chip structure 70 may include at least one second semiconductor chip including the third circuit region CR 3 and the fourth circuit region CR 4 as described above with reference to FIG. 1 .

In example embodiments, the first semiconductor chip of the first semiconductor chip structure 50 may include a first semiconductor substrate 53 and a first region 56 below the first semiconductor substrate 53 and constituting the first and second circuit regions CR 1 and CR 2 .

In example embodiments, the at least one second semiconductor chip of the second semiconductor chip structure 70 may include a second semiconductor substrate 73 and a second region 76 below the second semiconductor substrate 73 and constituting the third and fourth circuit regions CR 3 and CR 4 .

Pads may be below the first region 56 , and pads may be below the second region 76 .

The pads below the first region 56 of the first semiconductor chip structure 50 may include first signal pads 59 a electrically connected to the first signal paths SI_H, second signal paths 59 b electrically connected to the second signal paths SI_L, first power pads 59 c 1 electrically connected to the first power paths PWa of the first power/ground paths PW 1 , first ground pads 59 c 2 electrically connected to the first ground paths PWb of the first power/ground paths PW 1 , second power pads 59 d 1 electrically connected to the second power paths PWb of the second power/ground paths PW 2 , and second ground pads 59 c 2 electrically connected to the second ground paths PWd of the second power/ground paths PW 2 .

The pads below the first region 56 of the first semiconductor chip structure 50 may further include first and second interface pads 62 . The first and second interface pads 62 may include first interface pads 62 a overlapping the first interposer 20 a and second interface pads 62 b overlapping the second interposer 20 b.

In the first semiconductor chip structure 50 , any one of the first interface pads 62 a and the second interface pads 62 b may be omitted.

The pads below the second region 76 of the second semiconductor chip structure 70 may include third signal pads 79 a electrically connected to the first signal paths SI_H, fourth signal pads 79 b electrically connected to the second signal paths SI_L, third power pads 99 c 1 electrically connected to the first power paths PWa of the first power/ground paths PW 1 , third ground pads 79 c 2 electrically connected to the first ground paths PWb of the first power/ground paths PW 1 , fourth power pads 79 d 1 electrically connected to the second power paths PWb of the second power/ground paths PW 2 , and fourth ground pads 79 c 2 electrically connected to the second ground paths PWd of the second power/ground paths PW 2 .

The pads below the second region 76 of the second semiconductor chip structure 70 may further include third and fourth interface pads 82 . The third and fourth interface pads 82 include third interface pads 82 a overlapping the first interposer 20 a and fourth interface pads 82 b overlapping the second interposer 20 b.

In the second semiconductor chip structure 70 , any one of the third interface pads 82 a and the fourth interface pads 82 b may be omitted.

In the second semiconductor chip structure 70 , the third and fourth interface pads 82 a and 82 b may be omitted.

The first semiconductor chip structure 50 may further include conductive bumps 65 below the pads 59 and 62 and electrically connected to and contacting the first and second upper pads 45 a and 45 b of the first and second interposers 20 a and 20 b . The second semiconductor chip structure 70 may further include conductive bumps 85 electrically connected to and contacting the first and second upper pads 45 a and 45 b.

The first and second semiconductor chip structures 50 and 70 may be mounted on the first and second interposers 20 a and 20 b by the conductive bumps 85 in a flip-chip manner. The first and second interposers 20 a and 20 b may be mounted on the package substrate 3 by the conductive bumps 22 a and 22 b in a flip-chip manner.

In some embodiments, at least one of the first and second semiconductor chip structures 50 and 70 may include interface regions IF 1 and IF 2 , at least one of the first and second interposers 20 a and 20 b may include interface paths including the first interconnection structure 35 a and the second interconnection structure 35 b electrically connected to the interface regions IF 1 and IF 2 , and at least a portion of the interface paths may be on substantially the same vertical level as that of the first and second signal paths SI_H and SI_L.

Hereinafter, various modified examples of the components of the aforementioned embodiment will be described. Various modified examples of the components of the aforementioned embodiment to be described below will be mainly described with respect to components being modified or components being replaced. In addition, the components that may be modified or replaced described below are described with reference to the following drawings, but the components that may be modified or replaced may be combined with each other or combined with the components described above to implement an electronic system according to some embodiments of the present inventive concept.

The plurality of interposers INT in FIG. 1 described above may be the first and second interposers 20 a and 20 b , which may be silicon interposers as shown in FIGS. 3 A, 3 B and 3 C , but the embodiments of the present inventive concept are not limited thereto. For example, the first and second interposers 20 a and 20 b may be modified or replaced with an interposer other than a silicon interposer, for example, a redistribution interposer, and the semiconductor package of an electronic system according to some embodiments of the present inventive concept may be modified to a semiconductor package including interposers that may be modified or replaced.

An example of a redistribution interposer capable of replacing the silicon interposer of the first and second interposers 20 a and 20 b will be described with reference to FIGS. 4 A and 4 B , and another example of a redistribution interposer capable of replacing the silicon interposer of the first and second interposers 20 a and 20 b will be described with reference to FIGS. 5 A and 5 B .

FIGS. 4 A and 4 B are conceptual cross-sectional views illustrating a redistribution interposer that may replace the silicon interposer of the first and second interposers 20 a and described above with reference to FIGS. 3 A to 3 C . FIG. 4 A is a cross-sectional view schematically illustrating a region taken along line I-I′ of FIG. 2 , and FIG. 4 B is a cross-sectional view schematically illustrating a region taken along line III-III′ and IV-IV′ of FIG. 2 .

In a modified example, referring to FIGS. 4 A and 4 B , a semiconductor package 10 b in the modified example may include a first interposer 120 a that may replace the first interposer described above with reference to FIGS. 3 A to 3 C and a second interposer 120 b that may replace the second interposer 20 b described above with reference to FIGS. 3 A to 3 C .

The first and second interposers 120 a and 120 b may be redistribution interposers.

The first interposer 120 a may include the first signal paths SI_H and the first power/ground paths PW 1 described above with reference to FIG. 1 , and the second interposer 120 b may include the second signal paths SI_L and the second power/ground paths PW 2 described above with reference to FIG. 1 . Each of the first and second interposers 120 a and 120 b may further include an insulating structure 132 a , lower pads 129 a below the insulating structure 132 a , redistribution structures 139 a and 141 a in the insulating structure 132 a , and upper pads 148 a on the insulating structure 132 a.

At least a portion of the redistribution structures 139 a and 141 a may be on substantially the same vertical level as those of the first signal paths SI_H, the first power/ground paths PW 1 , the second signal paths SI_L, and the second power/ground paths PW 2 . The first signal paths SI_H and the first power/ground paths PW 1 may be in the insulating structure 132 a of the first interposer 120 a , and the second signal paths SI_L and the second power/ground paths PW 2 may be in the insulating structure 132 a of the second interposer 120 b.

The redistribution structures 139 a and 141 a may include lower redistribution structures 139 a and upper redistribution structures 141 a on the lower redistribution structures 139 a . At least some of the redistribution structures 139 a and 141 a may include a line portion and a via portion extending from the line portion. For example, each of the lower redistribution structures 139 a may include a lower via portion 139 V and a lower line portion 139 L extending from the lower via portion 139 V

At least some of the upper redistribution structures 141 a may include an upper via portion 141 V and an upper line portion 141 L extending from the upper via portion 141 V.

In example embodiments, some of the upper redistribution structures 141 a of the first interposer 120 a , for example, the upper line portion 141 L, may be on substantially the same vertical level as that of the first signal paths SI_H and the first power/ground paths PW 1 .

In example embodiments, some of the upper redistribution structures 141 a of the second interposer 120 b , for example, the upper line portions 141 L, may be on substantially the same vertical level as that of the second signal paths SI_L and the second power/ground paths PW 2 .

The upper pads 148 a may be electrically connected to the upper line portions 141 L of the upper redistribution structures 141 a . The lower redistribution structures 139 a may be electrically connected to the lower pads 129 a.

In another embodiment, the lower redistribution structures 139 a may be omitted, and some of the upper redistribution structures 141 a may be electrically connected to and in contact with the lower pads 129 a.

Next, a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept will be described with reference to FIGS. 5 A and 5 B . FIGS. 5 A and 5 B are conceptual cross-sectional views illustrating a redistribution interposer that may replace the silicon interposer of the first and second interposers 20 a and 20 b described above with reference to FIGS. 3 A to 3 C . FIG. 5 A is a cross-sectional view schematically illustrating a region taken along line I-I′ of FIG. 2 , and FIG. 5 B is a cross-sectional view schematically illustrating a region taken along lines and IV-IV′ of FIG. 2 .

In a modified example, referring to FIGS. 5 A and 5 B , a semiconductor package 10 c in a modified example may include a first interposer 220 a that may replace the first interposer described above with reference to FIGS. 3 A to 3 C and a second interposer 220 b that may replace the second interposer 20 b described above with reference to FIGS. 3 A to 3 C .

The first and second interposers 220 a and 220 b may be redistribution interposers.

The first interposer 220 a may include the first signal paths SI_H and the first power/ground paths PW 1 described above with reference to FIG. 1 , and the second interposer 220 b may include the second signal paths SI_L and the second power/ground paths PW 2 described above with reference to FIG. 1 . Each of the first and second interposers 220 a and 220 b may further include an insulating structure 232 a , lower pads 229 a below the insulating structure 232 a , redistribution structures 239 a and 241 a in the insulating structure 232 a , and upper pads 448 a on the insulating structure 232 a.

At least a portion of the redistribution structures 239 a and 241 a may be on substantially the same vertical level as that of the first signal paths SI_H, the first power/ground paths PW 1 , the second signal paths SI_L, and the second power/ground paths PW 2 . The first signal paths SI_H and the first power/ground paths PW 1 may be in the insulating structure 232 a of the first interposer 220 a , and the second signal paths SI_L and the second power/ground paths PW 2 may be in the insulating structure 232 a of the second interposer 220 b.

The redistribution structures 239 a and 241 a may include lower redistribution structures 239 a and upper redistribution structures 241 a on the lower redistribution structures 239 a.

Each of the lower redistribution structures 239 a may include a lower via portion 239 V and a lower line portion 239 L extending from the lower via portion 239 V below the lower via portion 239 V.

At least some of the upper redistribution structures 241 a may include an upper via portion 241 V and an upper line portion 241 L extending downwardly from the upper via portion 241 V.

In example embodiments, some of the upper redistribution structures 241 a of the first interposer 220 a , for example, the upper line portions 241 L, may be on substantially the same vertical level as that of the first signal paths SI_H and the first power/ground paths PW 1 .

In example embodiments, some of the upper redistribution structures 241 a of the second interposer 220 b , for example, the upper line portions 241 L, may be on substantially the same vertical level as that of the second signal paths SI_L and the second power/ground paths PW 2 .

The upper pads 248 a may be electrically connected to the upper via portions 241 V of the upper redistribution structures 241 a . The lower redistribution structures 239 a may be electrically connected to the lower pads 229 a.

In another embodiment, the lower redistribution structures 239 a may be omitted, and some of the upper redistribution structures 241 a may be electrically connected to and in contact with the lower pads 229 a.

In the first semiconductor chip structure 50 , the pads 59 and 62 of FIGS. 3 A to 3 C may be replaced with pads 59 ′ and 62 ′ having a lower surface coplanar with a lower surface of the first region 56 . In the second semiconductor chip structure 70 , the pads 79 and 82 of FIGS. 3 A to 3 C may be replaced with pads 79 ′ and 82 ′ having a lower surface coplanar with the lower surface of the second region 76 .

The pads 59 ′, 62 ′, 79 ′, and 82 ′ of the first and second semiconductor chip structures 50 and 70 may be electrically connected and in contact with the upper pads 248 a of the first and second interposers 220 a and 220 b.

In the aforementioned embodiment, the second interposer 20 b in FIG. 2 may have the same length and the same width as those of the first interposer 20 a , but the embodiment of the present inventive concept is not limited thereto. For example, the second interposer 20 b having the same size as the first interposer 20 a as shown in FIG. 2 may be replaced with a second interposer having a different size from the first interposer 20 a . Hereinafter, an example of a second interposer having a size different from that of the first interposer 20 a will be described with reference to FIG. 6 . FIG. 6 is a conceptual top view illustrating example embodiments of a semiconductor package including a second interposer having a size different from that of the first interposer 20 a of FIG. 2 .

In a modified example, referring to FIG. 6 , the semiconductor package 10 d in the modified example may include a second interposer 20 b ′ having a size different from that of the first interposer 20 a described above with reference to FIG. 2 . For example, the second interposer 20 b ′ may have the same length as that of the first interposer 20 a , and may have a different width from that of the first interposer 20 a . For example, the width of the second interposer 20 b ′ may be smaller than the width of the first interposer 20 a.

The second interposer 20 b ′ may be an interposer having a reduced width than the second interposer 20 b in FIG. 2 , and the components of the second interposer 20 b ′ may be substantially the same as those of the second interposer 20 b in FIG. 2 .

The first and second interposers 20 a and 20 b ′ may be a silicon interposer as shown in FIGS. 3 A to 3 C , a redistribution interposer as shown in FIGS. 4 A and 4 B , or a redistribution interposer as shown in FIGS. 5 A and 5 B .

Next, a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept will be described with reference to FIG. 7 . FIG. 7 is a top view schematically illustrating a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept.

In a modified example, referring to FIG. 7 , in a semiconductor package 10 e in the modified example, at least one of the plurality of semiconductor chip structures CH on the plurality of interposers INT may be mounted on the plurality of interposers INT by a wire bonding method. For example, the first semiconductor chip structure 50 among the plurality of semiconductor chip structures CH may be mounted on the plurality of interposers INT by a flip chip bonding method or a direct bonding method as shown in FIG. 2 , and the second semiconductor chip structure 370 among the plurality of semiconductor chip structures CH may be mounted on the plurality of interposers INT by a wire bonding method. For example, as shown in FIGS. 3 A and 3 B , the first semiconductor chip structure 50 may be mounted on the plurality of interposers INT by a flip-chip bonding method, and the second semiconductor chip structure 370 may be mounted on the plurality of interposers INT by a wire bonding method, as shown in FIGS. 3 A and 3 B .

The plurality of interposers INT may include a first interposer 320 a and a second interposer 320 b mounted on the package substrate 3 and spaced apart from each other. The second semiconductor chip structure 370 may include chip pads 379 , the first interposer 320 a may include first substrate pads 479 a , and the second interposer 320 b may include second substrate pads 479 b . The chip pads 379 and the first substrate pads 479 a , and the chip pads 379 and the second substrate pads 479 b may be electrically connected to each other by bonding wires 390 .

The second semiconductor chip structure 370 may include the third circuit region CR 3 and the fourth circuit region CR 4 as described with reference to FIGS. 1 and 2 .

The first interposer 320 a may include the first power/ground paths PW 1 and the first signal paths SI_H as shown in FIGS. 1 and 2 . The second interposer 320 b may include the second power/ground paths PW 2 and the second signal paths SI_L as shown in FIGS. 1 and 2 .

The first substrate pads 479 a of the first interposer 320 a may be electrically connected to the first power/ground paths PW 1 and the first signal paths SI_H as shown in FIG. 2 . The second substrate pads 479 b of the second interposer 320 b may be electrically connected to the second power/ground paths PW 2 and the second signal paths SI_L as shown in FIG. 2 .

The third circuit region CR 3 of the second semiconductor chip structure 370 may be electrically connected to the first circuit region CR 1 of the first semiconductor chip structure through the chip pads 379 , the bonding wires 390 , the first substrate pads 479 a , the first power/ground paths PW 1 , and the first signal paths SI_H.

The fourth circuit region CR 4 of the second semiconductor chip structure 370 may be electrically connected to the second circuit region CR 2 of the first semiconductor chip structure 50 through the chip pads 379 , the bonding wires 390 , the second substrate pads 479 b , the second power/ground paths PW 2 , and the second signal paths SI_L.

As described above with reference to FIG. 1 , the third circuit region CR 3 may communicate with the first circuit region CR 1 at a first rate through the first signal paths SI_H of the first interposer 320 a , and the fourth circuit region CR 4 may communicate with the second circuit region CR 2 at a second rate, slower than the first rate, through the second signal paths SI_L of the second interposer 320 b.

The interposers INT may be silicon interposers as shown in FIGS. 3 A to 3 C , redistribution interposers as shown in FIGS. 4 A and 4 B , or redistribution interposers as shown in FIGS. 5 A and 5 B . Hereinafter, an example in which the interposers INT are silicon interposers as shown in FIGS. 3 A to 3 C will be described with reference to FIGS. 8 A and 8 B . FIG. 8 A is a cross-sectional view schematically illustrating a region taken along line Ia-Ia′ of FIG. 7 , and FIG. 8 B is a cross-sectional view schematically illustrating a region taken along lines and IVa-IVa′ of FIG. 7 .

Referring to FIGS. 7 , 8 A and 8 B , in the cross-sectional structure of FIGS. 3 A and 3 C , the second semiconductor chip structure ( FIGS. 3 A and 3 B ) may be mounted on the interposers INT by a flip chip bonding method, and the second semiconductor chip structure 370 described above with reference to FIG. 7 may be mounted on the interposers INT by a wire bonding method.

The first and second interposers 320 a and 320 b of the interposers INT may be interposers including the first substrate pads 479 a and the second substrate pads 479 b for wire bonding.

The second semiconductor chip structure 370 may include a semiconductor substrate 373 and a region 376 in which the third and fourth circuit regions (CR 3 and CR 4 of FIG. 7 ) are on the semiconductor substrate 373 . The second semiconductor chip structure 370 may include chip pads 379 for wire bonding. The chip pads 379 may be on the region 376 of the second semiconductor chip structure 370 . The second semiconductor chip structure 370 may be bonded to the interposers INT by an adhesive layer 395 . The chip pads 379 of the second semiconductor chip structure 370 and the first and second interposers 320 a and 320 b may be electrically connected to each other by bonding wires 390 .

Next, a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept will be described with reference to FIG. 9 . FIG. 9 is a top view schematically illustrating a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept.

In a modified example, referring to FIG. 9 , in a semiconductor package 10 f in a modified example, the plurality of interposers INT described above may further include a third interposer 20 c . The third interposer 30 c may be between the first and second interposers, for example, the first interposer (INT_ 1 of FIG. 1 , 20 a of FIG. 2 ) and the second interposer (INT_ 2 of FIG. 1 , 20 b of FIG. 2 ) as shown in FIGS. 1 and 2 . The third interposer 20 c may be spaced apart from the first interposer (INT_ 1 of FIG. 1 , 20 a of FIG. 2 ) and the second interposer (INT_ 2 of FIG. 1 , 20 b of FIG. 2 ).

The third interposer 20 c may include third power/ground paths PW 3 including a third power path PW 3 a and a third ground path PW 3 b . For example, the third power paths PW 3 a may be PLL power more sensitive than the first and second power paths PW 1 a and PW 2 c . The third interposer 20 c may include the third power paths PW 3 a of sensitive PLL power, but may not include a signal path for signal transmission.

The interposers INT may be silicon interposers as shown in FIGS. 3 A to 3 C , redistribution interposers as shown in FIGS. 4 A and 4 B , or redistribution interposers as shown in FIGS. 5 A and 5 B . Hereinafter, an example in which the interposers INT are silicon interposers as shown in FIGS. 3 A to 3 C will be described with reference to FIG. 10 . FIG. 10 is a cross-sectional view schematically illustrating a region taken along line IIIb-IIIb′ of FIG. 9 .

Referring to FIGS. 9 and 10 , the third interposer 20 c described above with reference to FIG. 9 may be the same silicon interposer as the first and second interposers ( 20 a and 20 b of FIG. 3 C ). For example, the third interposer 30 c may be a silicon interposer including the third power/ground paths PW 3 described above with reference to FIG. 9 , and the third power/ground paths PW 3 may be electrically connected to the first and second semiconductor chip structures CH_ 1 and CH_ 2 .

Next, a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept will be described with reference to FIG. 11 . FIG. 11 is a top view schematically illustrating a modified example of the semiconductor package of the electronic system according to some embodiments of the present inventive concept.

In a modified example, referring to FIG. 11 , in a semiconductor package 10 g in the modified example, at least one of the plurality of semiconductor chip structures CH on the plurality of interposers INT may be a stacked chip structure which is vertically stacked. For example, the second semiconductor chip structure ( 370 of FIG. 7 ) mounted on the interposers INT by a wire bonding method in FIG. 7 may be stacked semiconductor chip structures 570 _ 1 and 570 _ 2 including vertically stacked semiconductor chips as shown in FIG. 11 . The stacked chip structures 570 _ 1 and 570 _ 2 may be stacked by a wire bonding method. The stacked chip structures 570 _ 1 and 570 _ 2 may be mounted on the plurality of interposers INT by a wire bonding method. The plurality of interposers INT may include the first and second interposers 20 a and 20 b.

The stacked chip structures 570 _ 1 and 570 _ 2 may include a first semiconductor chip 570 _ 1 and a second semiconductor chip 570 _ 2 that are sequentially stacked. The first and second semiconductor chips 570 _ 1 and 570 _ 2 may include chip pads 579 , the first interposer 20 a may include first substrate pads 679 , and the second interposer 20 a may include second substrate pads 779 .

The chip pads 579 of the first and second semiconductor chips 570 _ 1 and 570 _ 2 and the first and second substrate pads 679 and 779 may be electrically connected to each other by bonding wires 590 . The first and second semiconductor chips 570 _ 1 and 570 _ 2 may be nonvolatile memory chips, such as NAND flash memory, or volatile memory chips, such as DRAM memory.

Each of the first and second semiconductor chips 570 _ 1 and 570 _ 2 may include the third circuit region CR 3 and the fourth circuit region CR 4 as described above with reference to FIGS. 1 and 2 .

The first interposer 20 a may include the first power/ground paths PW 1 and the first signal paths SI_H as shown in FIGS. 1 and 2 . The second interposer 20 b may include the second power/ground paths PW 2 and the second signal paths SI_L as shown in FIGS. 1 and 2 .

The first substrate pads 679 of the first interposer 20 a may be electrically connected to the first power/ground paths PW 1 and the first signal paths SI_H as shown in FIG. 2 . The second substrate pads 779 of the second interposer 20 b may be electrically connected to the second power/ground paths PW 2 and the second signal paths SI_L as shown in FIG. 2 .

The third circuit region CR 3 of each of the first and second semiconductor chips 570 _ 1 and 570 _ 2 may be electrically connected to the first circuit region CR 1 of the first semiconductor chip structure 50 through the chip pads 579 , the bonding wires 590 , the first substrate pads 679 , the first power/ground paths PW 1 , and the first signal paths SI_H.

The fourth circuit region CR 4 of each of the first and second semiconductor chips 570 _ 1 and 570 _ 2 may be electrically connected to the second circuit region CR 2 of the first semiconductor chip structure 50 through the chip pads 579 , the bonding wires 590 , the second substrate pads 779 , the second power/ground paths PW 2 , and the second signal paths SI_L.

As described above with reference to FIG. 1 , the third circuit region CR 3 may communicate with the first circuit region CR 1 at a first rate through the first signal paths SI_H of the first interposer 20 a , and the fourth circuit region CR 4 may communicate with the second circuit region CR 2 at a second rate, slower than the first rate, through the second signal paths SI_L of the second interposer 20 b.

The interposers INT may be silicon interposers as shown in FIGS. 3 A to 3 C , redistribution interposers as shown in FIGS. 4 A and 4 B , or redistribution interposers as shown in FIGS. 5 A and 5 B . Hereinafter, an example in which the interposers INT are silicon interposers as shown in FIGS. 3 A to 3 C will be described with reference to FIG. 12 . FIG. 12 is a cross-sectional view schematically illustrating a region taken along the line Ic-Ic′ of FIG. 11 .

Referring to FIGS. 11 and 12 , the first semiconductor chip 570 _ 1 may be attached to the first and second interposers 20 a and 20 b by an adhesive layer 595 covering a lower surface of the first semiconductor chip 570 _ 1 , and the second semiconductor chip 570 _ 2 may be attached to the first semiconductor chip 570 _ 1 by the adhesive layer 595 covering a lower surface of the second semiconductor chip 570 _ 2 . As described above, the first and second semiconductor chips 570 _ 1 and 570 _ 2 may include the chip pads 579 , and the first and second interposers 20 a and 20 b may include the first and second substrate pads 679 . As described above with reference to FIG. 11 , the chip pads 579 of the first and second semiconductor chips 570 _ 1 and 570 _ 2 and the first and second substrate pads 679 and 779 may be electrically connected to each other by the bonding wires 590 .

In FIGS. 11 and 12 , at least one of the plurality of semiconductor chip structures CH on the plurality of interposers INT may be stacked chip structures 570 _ 1 and 570 _ 2 stacked by a wire bonding method, but the embodiments of the present inventive concept are not limited thereto. For example, at least one of the plurality of semiconductor chip structures CH on the plurality of interposers INT may be replaced by a stacked chip structure stacked by a method other than the wire bonding method, for example, a flip chip bonding method or a direct bonding method. For example, in FIG. 2 , the second semiconductor chip structure 70 may be replaced with a stacked chip structure stacked by a method other than a wire bonding method, for example, a flip chip bonding method or a direct bonding method. Hereinafter, a stacked chip structure that may replace the second semiconductor chip structure 70 in FIGS. 2 , 3 A, 3 B , and 3 C will be described with reference to FIG. 13 . FIG. 13 is a cross-sectional view illustrating a stacked chip structure that may replace the second semiconductor chip structure in the cross-sectional structure of FIG. 3 A .

Referring to FIG. 13 , a semiconductor package 10 h in the modified example may include a stacked chip structure 770 that may replace the second semiconductor chip structure 70 in FIGS. 2 , 3 A, 3 B, and 3 C .

The stacked chip structure 770 may include a lower chip 771 and a plurality of semiconductor chips 772 that are vertically spaced apart from each other and stacked on the lower chip 771 .

The stacked chip structure 770 may further include bump structures 780 for interconnecting the lower chip 771 and the plurality of semiconductor chips 772 . The lower chip 771 may further include through-electrodes 773 for electrically connecting the plurality of semiconductor chips 772 and the plurality of interposers INT, and chips other than the uppermost semiconductor chip, among the plurality of semiconductor chips 772 may further include through-electrodes 773 for interconnecting the plurality of semiconductor chips 772 . The stacked chip structure 770 may further include a mold layer 774 covering lower portions of the plurality of semiconductor chips 772 on the lower chip 771 and covering side surfaces of the plurality of semiconductor chips 772 . The stacked chip structure 770 may be mounted on the first and second interposers 20 a and 20 b using a flip-chip method. The lower chip 771 may be a buffer chip or a logic chip. The plurality of semiconductor chips 772 may be volatile memory chips, such as DRAM memory.

In the semiconductor package 10 of the electronic system described above with reference to FIGS. 1 to 13 , the plurality of semiconductor chips CH may include the first semiconductor chip structure (CH_ 1 of FIG. 1 ) and the second semiconductor chip structure (CH_ 2 of FIG. 1 ) spaced apart from each other. However, the embodiments of the present inventive concept are not limited thereto. The second semiconductor chip structure (CH_ 2 of FIG. 1 ) described above may be replaced with a plurality of semiconductor chips respectively mounted on the plurality of interposers INT. An example in which the second semiconductor chip structure (CH_ 2 of FIG. 1 ) may be replaced with a plurality of semiconductor chip structures respectively mounted on the plurality of interposers INT will be described with reference to FIGS. 14 , 15 , and 16 . FIG. 14 is a conceptual view illustrating an example in which the second semiconductor chip structure (CH_ 2 of FIG. 1 ) may be replaced with a plurality of semiconductor chip structures respectively mounted on the plurality of interposers INT described above in the electronic system 1 of FIG. 1 , FIG. 15 is a top view schematically illustrating an example of a semiconductor package of the electronic system of FIG. 14 , and FIG. 16 is a cross-sectional view schematically illustrating a region taken along lines IIId-IIId′ and IV-IV′ of FIG. 15 .

Referring to FIGS. 14 , 15 , and 16 , the second semiconductor chip structure (CH_ 2 of FIG. 1 ) described above with reference to FIG. 1 may be replaced with a plurality of semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ respectively mounted on the plurality of interposers INT.

The plurality of semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ may be spaced apart from each other in a horizontal direction, and the semiconductor chip structure mounted on the first interposer INT_ 1 may be referred to as a second semiconductor chip structure CH_ 2 ′, and the semiconductor chip structure mounted on the second interposer INT_ 2 may be referred to as a third semiconductor chip structure CH_ 3 ′.

The first and second interposers INT_ 1 and INT_ 2 may be silicon interposers as described with reference to FIGS. 3 A to 3 C , but the embodiment is not limited thereto. For example, the first and second interposers INT_ 1 and INT_ 2 may be redistribution interposers as shown in FIGS. 4 A and 4 B or redistribution interposers as shown in FIGS. 5 A and 5 B .

The first interposer INT_ 1 may include the first power/ground paths PW 1 and the first signal paths SI_H as described above with reference to FIG. 1 , and the second interposer INT_ 2 may include the second power/ground paths PW 2 and the second signal paths SI_L as described above with reference to FIG. 1 . The number of first signal paths SI_H may be greater than the number of second signal paths SI_L. For example, the number of first signal paths SI_H may be about 1.5 times to about 1.8 times greater than the number of second signal paths SI_L.

The circuit region CR 3 of the second semiconductor chip structure CH_ 2 ′ may communicate with the first circuit region CR 1 of the first semiconductor chip structure CH_ 1 at a first rate through the first signal paths SI_H of the first interposer INT_ 1 . The circuit region CR 4 of the third semiconductor chip structure CH_ 3 ′ may communicate with the second circuit region CR 2 of the first semiconductor chip structure CH_ 1 at a second rate, slower than the first rate, through the second signal paths SI_L of the second interposer INT_ 2 .

The second semiconductor chip structure CH_ 2 ′ may include a semiconductor substrate 873 a and a region 876 a including the third circuit region CR 3 below the semiconductor substrate 873 a , and the third semiconductor chip structure CH_ 3 ′ may include a semiconductor substrate 873 b and a region 876 b including the fourth circuit region CR 4 below the semiconductor substrate 873 b.

The second and third semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ may be mounted on the first and second interposers INT_ 1 and INT_ 2 by a flip-chip bonding method as shown in FIG. 16 , but the embodiments of the invention are not limited thereto. For example, at least one of the second and third semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ may be mounted on the first and second interposers INT_ 1 and INT_ 2 in a wire bonding method similar to FIG. 7 .

Each of the second and third semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ may be a single chip, but embodiments of the present inventive concept are not limited thereto. For example, at least one of the second and third semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ may be a stacked chip structure in which semiconductor chips are vertically stacked. For example, at least one of the second and third semiconductor chip structures CH_ 2 ′ and CH_ 3 ′ may be a stacked chip structure stacked by a wire bonding method as described above with reference to FIGS. 11 and 12 , or may be a stacked chip structure interconnected by through-electrodes 773 as shown in FIG. 13 .

According to embodiments, a semiconductor package including a first interposer providing first signal paths having a relatively high speed and a second interposer providing second signal paths having a relatively low speed, and an electronic system including the same may be provided.

A plurality of semiconductor chip structures mounted on the first and second interposers may communicate with each other at a first rate through the first signal paths of the first interposer and may communicate with each other at a second rate, slower than the first rate, through the second signal paths of the first interposer. In this manner, by providing the first signal paths and the second signal paths in the first and second interposers spaced apart from each other, the first signal paths and the second signal paths may be physically separated from each other.

As such, by separating the first interposer including the first signal paths and the second interposer including the second signal paths from each other, a noise coupling issue due to an increase in pattern arrangement density, that is, the occurrence of noise due to cross-talk may be reduced or prevented. For example, by physically separating the first signal paths and the second signal paths, the occurrence of noise coupling in a high-speed signal of the first signal paths may be reduced or prevented, thereby preventing deterioration of the characteristics of the high-speed signal. Accordingly, since noise that may occur between signal paths having different speeds may be reduced or prevented, the performance of the semiconductor package may be improved, and an electronic system including the semiconductor package with improved performance may be provided.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modified examples and variations could be made without departing from the scope of the present inventive concept as defined by the appended claims.