Semiconductor Storage Device

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-150834 filed Sep. 16, 2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storage device.

BACKGROUND

A semiconductor storage device including a substrate and a stacked body in which conductive layers and insulating layers are alternately stacked on the substrate, is known.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the configuration of a semiconductor storage device according to a first embodiment.

FIG. 2 is an equivalent circuit diagram schematically illustrating the configuration of a memory cell array in the semiconductor storage device.

FIG. 3 is a plan view of a memory layer of the semiconductor storage device as viewed from above in the Z direction.

FIG. 4 is a plan view of a circuit layer of the semiconductor storage device as viewed from above in the Z direction.

FIG. 5 is a plan view schematically illustrating an enlarged portion A 1 of FIG. 3 .

FIG. 6 is a schematic cross-sectional view of a cross-section taken along line X 1 -X 1 ′ in FIG. 5 .

FIG. 7 is a cross-sectional view of an enlarged portion A 2 of FIG. 6 .

FIG. 8 is a schematic perspective view illustrating a hookup region of the semiconductor storage device.

FIG. 9 is a schematic cross-sectional view of a cross-section taken along line Y 1 -Y 1 ′ in FIG. 5 .

FIG. 10 is a schematic perspective view of a part of a wiring layer of the semiconductor storage device.

FIG. 11 is a schematic cross-sectional view of a cross-section taken along line X 2 -X 2 ′ in FIG. 5 .

FIG. 12 is a plan view illustrating a conductive layer in the wiring layer of the semiconductor storage device.

FIG. 13 is a view illustrating another wiring pattern in the wiring layer of the semiconductor storage device.

FIG. 14 is a plan view illustrating an example of a wiring pattern used in the wiring layer of the semiconductor storage device.

FIGS. 15 A to 15 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 16 A to 16 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 17 A to 17 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 18 A to 18 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 19 A to 19 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 20 A to 20 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 21 A to 21 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 22 A to 22 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIGS. 23 A to 23 C are a schematic plan view and cross-sectional views illustrating a manufacturing process of the semiconductor storage device.

FIG. 24 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 25 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 26 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 27 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 28 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 29 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 30 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 31 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 32 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor storage device.

FIG. 33 is a schematic plan view of a semiconductor storage device according to a second embodiment.

FIG. 34 is a schematic plan view of a semiconductor storage device according to a third embodiment.

FIG. 35 is a plan view schematically illustrating an enlarged portion A 3 of FIG. 34 .

FIG. 36 is a schematic cross-sectional view of a cross-section taken along line Y 2 -Y 2 ′ in FIG. 35 .

FIG. 37 is a schematic plan view of a semiconductor storage device according to a fourth embodiment.

FIG. 38 is a schematic cross-sectional view of a cross-section taken along line Y 3 -Y 3 ′ in FIG. 37 .

FIG. 39 is a schematic plan view of a semiconductor storage device according to a fifth embodiment.

FIG. 40 is a schematic cross-sectional view of a cross-section taken along line Y 3 -Y 3 ′ in FIG. 39 .

FIG. 41 is a schematic plan view illustrating a semiconductor storage device according to a sixth embodiment.

FIG. 42 is a schematic cross-sectional view illustrating a semiconductor storage device according to a seventh embodiment.

FIG. 43 is a schematic equivalent circuit diagram illustrating a semiconductor storage device according to an eighth embodiment.

FIG. 44 is a schematic equivalent circuit diagram illustrating a semiconductor storage device according to a ninth embodiment.

FIG. 45 is a schematic equivalent circuit diagram illustrating a semiconductor storage device according to a tenth embodiment.

DETAILED DESCRIPTION

Embodiments provide a semiconductor storage device having many wiring paths.

In general, according to one embodiment, a semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a first contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.

Next, a semiconductor storage device according to embodiments will be described in detail with reference to the accompanying drawings. The following embodiments are merely examples, and are not intended to limit the present disclosure. In addition, the following drawings are schematic, and certain configurations may be omitted for convenience of explanation. The same reference numerals may be given to common parts of the embodiments, and descriptions thereof may be omitted.

In the present specification, a direction intersecting the surface of a substrate is referred to as a first direction, a direction intersecting the first direction is referred to as a second direction, and a direction intersecting the first direction and the second direction is referred to as a third direction. Further, a predetermined direction parallel to the surface of the substrate is referred to as the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the surface of the substrate is referred to as the Z direction. In the following description, a case will be illustrated where the X direction, the Y direction, and the Z direction correspond to the third direction, the second direction, and the first direction, respectively. However, the first direction, the second direction, and the third direction are not limited to the X direction, the Y direction, and the Z direction, respectively.

Further, in the present specification, expressions such as “upward” and “downward” are defined with respect to the substrate. For example, the direction away from the substrate along the first direction is referred to as “upward”, and the direction closer to the substrate along the first direction is referred to as “downward”. When the lower surface or lower end of a configuration is referred to, it means the surface or end of the substrate of the configuration, and when the upper surface or upper end of a configuration is referred to, it means the surface or end on the opposite side of the substrate of the configuration. Further, the surface intersecting the second direction or the third direction is referred to as a side surface.

Further, in the present specification, the expression “semiconductor storage device” has various meanings such as a memory system including a memory die, a memory chip, a memory card, and a control die such as an SSD, and a configuration including a host computer such as a smartphone, a tablet terminal, and a personal computer.

Further, in the present specification, when a first configuration is “electrically connected” to a second configuration, it means that the first configuration is connected to the second configuration directly or via a circuit such as a wiring, a semiconductor member, or a transistor. For example, when three transistors are connected in series, even when the second transistor is in the OFF state, the first transistor is “electrically connected” to the third transistor.

First Embodiment

[Configuration]

Hereinafter, the configuration of a semiconductor storage device according to a first embodiment will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating the configuration of the semiconductor storage device according to the first embodiment.

The semiconductor storage device according to the present embodiment includes a memory cell array MCA and a peripheral circuit PC that controls the memory cell array MCA.

FIG. 2 is an equivalent circuit diagram schematically illustrating the configuration of the memory cell array MCA. The memory cell array MCA has, for example, a plurality of NAND-connected memory cells MCs.

The memory cell array MCA includes a plurality of memory blocks MBs. Each of the plurality of memory blocks MBs includes a plurality of string units SUs. Each of the plurality of string units SU includes a plurality of memory units MUs. One ends of the plurality of memory units MUs are each connected to the peripheral circuit PC via a bit line BL. Further, the other ends of the plurality of memory units MUs are each connected to the peripheral circuit PC via a common source line SL.

The memory unit MU includes a drain select transistor STD, a plurality of memory cells MCs (memory string MS), and a source select transistor STS, which are connected in series between the bit line BL and the source line SL. Hereinafter, the drain select transistor STD and the source select transistor STS may be simply referred to as a select transistor (STD, STS).

The memory cell MC is a field effect transistor (memory transistor) including a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a memory film capable of storing data. The memory film is a charge storage film such as, for example, a silicon nitride film (SiN) or a floating gate. The threshold voltage of the memory cell MC changes according to the amount of charges in the charge storage film. A word line WL is connected to each of the gate electrodes of a plurality of memory cells MCs corresponding to one memory string MS. Each of the word lines WLs is commonly connected to all memory strings MSs in one memory block MB.

The select transistor (STD, STS) is a field effect transistor including a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. In this example, one memory unit MU is illustrated to include only one drain select transistor STD and one source select transistor STS. However, each of the select transistors STD and STS in one memory unit MU may include one or plural select transistors. Select gate lines (SGD, SGS) are connected to the gate electrodes of the select transistors (STD, STS), respectively. One drain select gate line SGD is provided for each string unit SU and is commonly connected to all the memory units MUs in one string unit SU. The source select gate line SGS is commonly connected to all memory units MUs in a plurality of string units SUs in one memory block MB.

As illustrated in FIG. 1 , the peripheral circuit PC includes a voltage generation circuit VG that generates an operating voltage, an input/output buffer I/OB that inputs/outputs data, addresses, commands, and status information, an address register AR that stores address data, a row decoder RD and a column decoder CD that decode the address, a data cache DC that stores data to be written to the memory cell array MCA and data read from the memory cell array MCA, a sense amplifier SA connected to the bit line BL of the memory cell array MCA, and a controller CR that controls these elements.

The voltage generation circuit VG generates a plurality of operating voltages applied to the bit line BL, the source line SL, the word line WL, and the select gate line (SGD, SGS) during the read operation, write operation, and erase operation for the memory cell array MCA according to the control signal from the controller CR and outputs the generated operating voltages to the memory cell array MCA, the row decoder RD, and the sense amplifier SA. The voltage generation circuit VG includes, for example, a plurality of charge pump circuits and a plurality of regulator circuits.

The input/output buffer I/OB receives addresses, data, and commands from the outside via the I/O terminal, and transmits data and status information to the outside via the I/O terminal.

The row decoder RD refers to the row address in the address register AR according to the control signal from the controller CR, decodes this row address, and applies a voltage to the word line WL and the source select gate line SGS connected to the memory block MB corresponding to the row address, and the drain select gate line SGD connected to the string unit SU corresponding to the row address, to activate these lines.

The column decoder CD refers to the column address in the address register AR according to the control signal from the controller CR, decodes this column address, and applies a voltage to the bit line BL corresponding to the column address.

The data cache DC temporarily stores data transferred between the input/output buffer I/OB and the sense amplifier SA.

The sense amplifier SA is connected to a plurality of bit lines BL. The sense amplifier SA includes, for example, a plurality of sense amplifier units, each corresponding to one of the bit lines BL. The sense amplifier unit includes a clamp transistor that charges the bit line BL based on the voltage generated by the voltage generation circuit VG, a sensing circuit that senses the voltage or current of the bit line BL, a plurality of latches that stores the output signal and write data of the sensing circuit and the verify path flag FLG, and a logic circuit. The logic circuit determines the data stored in the memory cell MC by referring to the data stored in the lower page in the latch, for example, during the read operation. Further, for example, in the write operation, the voltage of the bit line BL is controlled by referring to the data stored in the lower page in the latch.

The controller CR supplies a chip enable signal/CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal/WE, a read enable signal/RE, and a write protect signal/WP, through corresponding input terminals, and controls each part that latches addresses and commands, and reads/writes data based on these control signals. The controller CR has a command register, refers to the command data stored in the command register, decodes this command data, controls each part, and outputs a ready/busy signal/RB to the outside via a/RB terminal.

FIG. 3 is a plan view of a memory layer ML of the semiconductor storage device according to the present embodiment as viewed from above in the Z direction. FIG. 4 is a plan view of a circuit layer CL of the semiconductor storage device as viewed from above in the Z direction.

In the semiconductor storage device of the present embodiment, the memory layer ML illustrated in FIG. 3 is provided on the circuit layer CL illustrated in FIG. 4 . The memory layer ML is stacked on the circuit layer CL.

As illustrated in FIG. 3 , the memory layer ML has two memory planes MPs arranged in the X direction and a plurality of bonding pads BPs arranged on one side of the memory planes MPs in the Y direction and arranged in the X direction. The memory plane MP has a memory cell array MCA and wiring layers WIRs provided on both sides of the memory cell array MCA in the Y direction and extending in the X direction. The memory cell array MCA has a plurality of memory blocks MB. The plurality of memory block MBs extend in the X direction and are arranged in the Y direction. Each memory block MB includes a plurality of memory cell regions RMCs arranged in the X direction, a contact connection region RCT arranged between the memory cell regions RMCs, and hookup regions RHU arranged at both ends in the X direction. The memory plane MP and the bonding pad BP are surrounded by an edge seal ES. The edge seal ES has a crack growth preventing function of stopping cracks generated in a chip during dicing, a filth invasion prevention function of preventing impurity ions from entering from the outside, and a function of providing a route for releasing electric charges generated in the manufacturing process.

Each circuit block of the circuit layer CL corresponds to the circuit block of the peripheral circuit PC of FIG. 1 , and is disposed as illustrated in, for example, FIG. 4 . A row decoder RD is disposed below the hookup region RHU located at both ends of each memory plane MP of the memory layer ML in the X direction. A sense amplifier SA, a data cache DC, a column decoder CD, an address register AR, a controller CR, and a voltage generation circuit VG are arranged in a region that is between the row decoders RDs on the lower side of each memory plane MP. An input/output buffer I/OB is disposed below the bonding pads BP. These circuit elements are surrounded by the edge seal ES.

FIG. 5 is a plan view schematically illustrating an enlarged portion A 1 of FIG. 3 . Each memory block MB has a plurality of conductive layers 110 a arranged in the Z direction. The plurality of conductive layers 110 a in each memory block MB are insulated and separated from each other in the Y direction by the insulating layer ST extending in the X direction. In this example, each memory block MB has two string units SU in the Y direction. The two string units SU in one memory block MB are separated from each other in the Y direction by an insulating layer SHE. A plurality of memory structures 100 is provided side by side in the X and Y directions in the memory cell region RMC. In the contact connection region RCT, a plurality of contacts CDMas penetrating the memory layer ML down to the circuit layer CL is disposed in the X direction.

The wiring layer WIR is adjacent to the memory cell array MCA in the Y direction. An insulating layer ST is provided between the memory cell array MCA and the wiring layer WIR, whereby the memory cell array MCA and the wiring layer WIR are insulated and separated from each other. The wiring layer WIR has a plurality of conductive layers 110 b arranged in the Z direction. The conductive layer 110 b has a wiring region WIRa on the side closer to the memory cell array MCA and a connection region WIRb on the side farther from the memory cell array MCA. The wiring region WIRa is continuous in the X direction. The connection region WIRb has a contact insertion portion 200 cut out in a rectangular shape. A contact CCb passes through the contact insertion portion 200 and is connected to the conductive layer 110 b in the lower layer. FIG. 5 represents an example in which the width of the wiring layer WIR in the Y direction is larger than the width of the conductive layer 110 a in the Y direction between two adjacent insulating layers ST in the memory cell array MCA (i.e., the width of the word line WL in the Y direction). However, the width of the wiring layer WIR in the Y direction may be smaller than the width of the conductive layer 110 a in the Y direction between two adjacent insulating layers ST in the Y direction (i.e., the width of the word line WL in the Y direction).

On the side of the wiring layer WIR opposite to the memory cell array MCA, a plurality of contacts CDMbs penetrating the memory layer ML down to the peripheral region of the circuit layer CL in the Z direction is disposed in the X direction. The peripheral wiring region includes the wiring layer WIR and the contact CDMb. In this example, the contacts CDMbs are arranged in the X direction, but the arrangement direction of the contacts CDMbs may be any direction, and may be arranged in, for example, two random directions.

FIG. 6 is a schematic cross-section viewed in the Y direction, of the portions cut along line X 1 a -X 1 a ′ and line X 1 b -X 1 b ′ in FIG. 5 . Hereinafter, in the present embodiment, an example will be illustrated in which four conductive layers 110 a (SGD) functioning as the drain select gate line SGD and ten conductive layers 110 a (WL) functioning as the word line WL are stacked. However, the number of stacked conductive layers 110 a (SGD) and 110 a (WL) is not limited to fourteen (14) layers.

The circuit layer CL is formed on the substrate S. The substrate S is a semiconductor substrate containing, for example, single crystal silicon (Si). The substrate S has, for example, a double-well structure having an N-type impurity layer such as phosphorus (P) on the surface of the semiconductor substrate and further having a P-type impurity layer such as boron (B) in the N-type impurity layer. In the double-well structure, an insulating layer 140 such as SiO2 is provided for separating the transistors Tr. A contact CS such as tungsten (W) and wirings D 0 , D 1 , and D 2 are sequentially provided on the transistor Tr from the bottom to the top.

The memory layer ML has a plurality of conductive layers 110 a extending in the XY direction and arranged in the Z direction in the memory cell region RMC and the hookup region RHU. The plurality of conductive layers 110 a include, for example, a stacked film of titanium nitride (TiN) and tungsten (W). An insulating layer 101 a such as silicon dioxide (SiO2) is provided between the plurality of conductive layers 110 a . In the contact connection region RCT of the memory layer ML, a plurality of insulating layers 110 A such as silicon nitride (SiN) is provided on the layers corresponding to the plurality of conductive layers 110 a of the memory cell region RMC and the hookup region RHU. An insulating layer 101 a is provided between the plurality of insulating layers 110 A. Insulating layers ST 1 are provided on both sides of the contact connection region RCT in the X direction. The insulating layer ST 1 may not be provided in some embodiments. In such embodiments, in the wet etching step of removing the insulating layer 110 A, the wet etching time may be adjusted so that the insulating layer 110 A remains around the contact CDMa of the contact connection region RCT.

The memory cell region RMC is provided with, for example, a plurality of columnar memory structures 100 that extends in the Z direction through the plurality of conductive layers 110 a and the insulating layer 101 a . The hookup region RHU has a staircase portion STP formed by the X-direction end of the conductive layers 110 a moving away from the memory cell region RMC as it approaches the substrate S. Each conductive layer 110 a of the staircase portion STP is connected to a contact CCa extending in the Z direction. In the portion where the insulating layers 110 A and 101 a of the contact connection region RCT are stacked, a contact CDMa penetrates this portion in the Z direction and extends to the circuit layer CL. A plurality of wirings M 0 , M 1 , and M 2 made of metal such as tungsten (W), copper (Cu) and aluminum (Al) is connected to the upper end of the memory structure 100 and the upper ends of the contacts CCa and CDMa. An upper wiring layer includes wirings M 1 and M 2 . The upper wiring layer is stacked on the memory layer ML.

The memory structures 100 are arranged in a predetermined pattern in the X direction and the Y direction in the memory cell region RMC. These memory structures 100 function as a memory unit MU. The upper end of the memory structure 100 is connected to the bit line BL, and the lower end thereof is connected to the conductive layer 112 .

FIG. 7 is a cross-sectional view of an enlarged portion A 2 of FIG. 6 . As illustrated in FIG. 7 , the memory structure 100 includes a semiconductor layer 120 extending in the Z direction and a gate insulating film 130 provided between the semiconductor layer 120 and the conductive layer 110 a.

The semiconductor layer 120 functions as, for example, a channel region of a plurality of memory cells MC and drain select transistors STD provided in one memory unit MU (see, for example, FIG. 2 ). The semiconductor layer 120 has, for example, a substantially cylindrical shape, and an insulating layer 125 such as silicon oxide (SiO2) is embedded in the central portion thereof. The semiconductor layer 120 contains, for example, undoped polycrystalline or single crystal silicon (Si).

The gate insulating film 130 is provided at each intersection of the semiconductor layer 120 and the conductive layer 110 a . The gate insulating film 130 includes a tunnel insulating film 131 , a charge storage film 132 , and a block insulating film 133 , which are stacked between the semiconductor layer 120 and the conductive layer 110 a . The tunnel insulating film 131 and the block insulating film 133 are, for example, insulating films such as silicon oxide (SiO2). The charge storage film 132 constitutes a memory film and is a film capable of storing electric charges such as silicon nitride (SiN).

The conductive layers 110 a are substantially plate-shaped conductive layers that are arranged in the Z direction via an insulating layer 101 a such as silicon oxide and extend in the X and Y directions. The plurality of conductive layers 110 a span the memory cell region RMC, a part of the contact connection region RCT, and the hookup region RHU. A high-dielectric film 111 such as alumina (Al2O3) is provided on the surface of the conductive layer 110 a . However, the high-dielectric film 111 may not be provided.

FIG. 8 is a schematic perspective view illustrating the hookup region RHU. The hookup region RHU has a staircase portion STP in which the ends of the conductive layers 110 a move away from the memory cell region RMC the closer they are to the substrate S. The staircase portion STP may be arranged differently, e.g., so that the end of the conductive layers 110 a are closer to the memory cell region RMC the closer they are to the substrate S. Further, in this example, the hookup region RHU includes a first hookup region RHU 1 for the upper four (4) layers close to the memory cell region RMC, and a second hookup region RHU 2 for the lower ten (10) layers farther from the memory cell area RMC than the first hookup region RHU 1 .

The conductive layer 110 a (SGD) of the first hookup region RHU 1 functions as a gate electrode of the drain select gate line SGD and a plurality of drain select transistors STD (see, for example, FIG. 2 ) connected to the drain select gate line SGD. The conductive layer 110 a (SGD) is divided into two in the memory block MB in the Y direction by the insulating layer SHE such as silicon oxide. The conductive layer 110 a (SGD) is commonly connected to all the memory structures 100 in one string unit SU.

The conductive layer 110 a (WL) of the second hookup region RHU 2 functions as a gate electrode of the word line WL and a plurality of memory cells MC (see, for example, FIG. 2 ) connected to the word line WL, respectively. The conductive layer 110 a (WL) is commonly connected to all the memory structures 100 in one memory block MB. An insulating layer ST, such as silicon oxide, extending to the substrate S is provided between the conductive layers 110 a (WL) of the memory blocks MB adjacent to each other in the Y direction.

The contact CCa extends in the Z direction and is connected to the contact region RCC of the plurality of conductive layers 110 a . The contact CCa includes, for example, a stacked film of titanium nitride (TiN) and tungsten (W). In the support structure region RHR around the contact CCa, a cylindrical support structure HR that maintains the stacked structure of the insulating layer 101 a during the manufacturing process penetrates the stacked structure. The support structure HR has a structure similar to that of the memory structure 100 . However, the upper end of the support structure HR is not connected to the wiring M 0 and the support structure HR does not function as a memory unit MU.

FIG. 9 is a schematic cross-section viewed in the X direction, of the portion cut along line Y 1 -Y 1 ′ in FIG. 5 . As illustrated in FIG. 9 , the wiring layers WIR arranged on both sides of the memory cell array MCA in the Y direction have a plurality of conductive layers 110 b extending in the X and Y directions and arranged in the Z direction. The plurality of conductive layers 110 b include, for example, a stacked film of titanium nitride (TiN) and tungsten (W). An insulating layer 101 b such as silicon dioxide (SiO2) is provided between the plurality of conductive layers 110 b . The conductive layer 110 b is provided on the same layer as the conductive layer 110 a of the memory cell region RMC. The insulating layer 101 b is provided on the same layer as the insulating layer 101 a of the memory cell region RMC. The conductive layer 110 b may be formed of substantially the same material, stack, or film thickness as the conductive layer 110 a of the memory cell region RMC. The insulating layer 101 b may be formed of substantially the same material and film thickness as the insulating layer 101 a of the memory cell region RMC.

The wiring layer WIR has a wiring region WIRa disposed on the side closer to the memory cell region RMC and a connection region WIRb disposed on the area farther from the memory cell region RMC. In the connection region WIRb, a stepped contact insertion portion 200 is appropriately provided according to the wiring pattern. The lower end of the contact CCb extending in the Z direction is connected to the conductive layer 110 b of the connection region WIRb. The upper end of the contact CCb is connected to the contact CDMb in the peripheral region and/or the contact CDMa in the contact connection region RCT via the wirings M 0 , M 1 , and M 2 . The contacts CCb and CDMb include, for example, a stacked film of titanium nitride (TiN) and tungsten (W).

FIG. 10 is a schematic perspective view of a part of the wiring layer WIR. The contact CCb is disposed in a region where the bit line BL does not exist, passes through the contact insertion portion 200 formed in the wiring layer WIR, and is connected to the lower conductive layer 110 b . The upper end of the contact CCb is connected to the upper end of the contact CDMa via the wirings M 0 , M 1 , and M 2 . In FIG. 10 , the end of the bit line BL is located above the Y-direction end region of the memory cell array MCA, but may be located above the wiring region WIRa or above the insulating layer ST at a boundary between the wiring region WIRa and the memory cell array MCA.

FIG. 11 is a schematic cross-section viewed in the Y direction, of the portion cut along line X 2 -X 2 ′ in FIG. 5 . Here, among the wiring layers WIR, the conductive layers 110 b of the upper ten (10) layers are indicated as the conductive layers 110 b 1 to 110 b 10 in order from the bottom. Hereinafter, the contact CCb represented by reference numeral “A” may be referred to as contact A, and the contact CCb represented by reference numeral “B” may be referred to as contact B. The contact A is connected to the conductive layer 110 b 1 . The contact B is connected to the conductive layer 110 b 4 . The contact C is connected to the conductive layer 110 b 7 . The contact D is connected to the conductive layer 110 b 10 . The other conductive layers 110 b 2 , 110 b 3 , 110 b 5 , 110 b 6 , 110 b 8 , and 110 b 9 are in an electrically floating state.

FIG. 12 is a plan view illustrating four conductive layers 110 b 1 , 110 b 4 , 110 b 7 , and 110 b 10 . A contact insertion portion 201 is formed in the conductive layer 110 b 4 , a contact insertion portion 202 is formed in the conductive layer 110 b 7 , and a contact insertion portion 203 is formed in the conductive layer 110 b 10 . The contact insertion portions of the upper layers have a larger width in the X direction and a larger width in the Y direction. The contact A passes through the contact insertion portions 201 , 202 , and 203 and is connected to the connection region WIRb of the conductive layer 110 b 1 . The contact B passes through the contact insertion portions 202 and 203 and is connected to the connection region WIRb of the conductive layer 110 b 4 . The contact C passes through the contact insertion portion 203 and is connected to the connection region WIRb of the conductive layer 110 b 7 . The contact D is connected to the connection region WIRb of the conductive layer 110 b 10 . A current flows between the contacts A and A via the wiring region WIRa and the connection region WIRb of the conductive layer 110 b 1 , as indicated by the dotted arrow. A current flows between the contacts B and B, between the contacts C and C, and between the contacts D and D via the wiring regions WIRa of 110 b 4 , 110 b 7 , and 110 b 10 , as indicated by the dotted arrows.

In the present embodiment, since two layers of the conductive layers 110 b in an electrically floating state are interposed between the conductive layers 110 b used as the wiring, the capacitance between the wirings may be reduced and the influence of the capacitive coupling may be reduced.

FIG. 13 is a view illustrating another form of wiring form in the wiring layer WIR. In this example, the conductive layers 110 b 1 , 110 b 2 , and 110 b 3 adjacent to each other in the Z direction are commonly connected to the contact A via a common wiring Mccb, the conductive layers 110 b 4 , 110 b 5 , and 110 b 6 adjacent to the Z direction are commonly connected to the contact B via a common wiring Mccb, and the conductive layers 110 b 7 and 110 b 8 adjacent to each other in the Z direction are commonly connected to the contact C via a common wiring Mccb.

According to this form of wiring, as the current value to be passed becomes larger, the wiring resistance may be reduced by increasing the number of the conductive layers 110 b that are commonly connected.

FIG. 14 illustrates an example of a wiring pattern used in the wiring layer WIR. The bit line BL is formed on the memory cell region RMC, and is not formed on the contact connection regions RCT 1 and RCT 2 and the wiring layer WIR. The wiring M 0 and the bit line BL are formed in the same layer and extend in the Y direction. The wiring M 1 is formed in a layer above the wiring M 0 and extends in the X direction. The wiring M 2 is formed in a layer above the wiring M 1 and extends in the Y direction. The wiring layer WIR may also be used as wiring for connecting the circuit blocks of the circuit layer CL illustrated in FIG. 4 .

Wiring Example 1

Peripheral circuit blocks, for example, the input/output I/O buffer I/OB is connected to a circuit block below the contact A 3 , for example, the address register AR, via the contact CDMb 1 , wiring M 2 , contact A 1 , conductive layer 110 b 1 , contact A 2 , wiring M 2 , wiring M 1 , and contact A 3 of connection region RCT 2 of the memory block MB 3 .

Wiring Example 2

Peripheral circuit blocks, for example, the input/output I/O buffer I/OB is connected to a peripheral circuit block below the contact CDMb 3 , for example, the input/output I/O buffer I/OB, via the contact CDMb 2 , wiring M 2 , contact B 1 , conductive layer 110 b 4 , contact B 2 , wiring M 2 , and contact CDMb 3 .

Wiring Example 3

The circuit block below the memory cell array MCA, for example, the voltage generation circuit VG is connected to a circuit block below the contact C 4 , for example, the row decoder RD, via the contact C 1 of the contact connection region RCT 1 of the memory block MB 1 , wiring M 2 , wiring M 1 , wiring M 2 , contact C 2 , conductive layer 110 b 7 , contact C 3 , wiring M 2 , and contact C 4 of the contact connection region RCT 2 of the memory block MB 3 .

Wiring Example 4

The circuit block below the memory cell array MCA, for example, the voltage generation circuit VG is connected to a circuit block below the contact D 4 , for example, the sense amplifier SA, via the contact D 1 of the contact connection region RCT 1 of the memory block MB 2 , wiring M 1 , wiring M 2 , contact D 2 , conductive layer 110 b 10 , contact D 3 , wiring M 2 , wiring M 1 , and contact D 4 of the contact connection region RCT 2 of the memory block MB 5 .

Wiring Example 5

The circuit block below the memory cell array MCA, for example, the column decoder CD is connected to a circuit block below the contact E 2 , for example, the column decoder CD, via the contact E 1 of the contact connection region RCT 1 of the memory block MB 4 , wiring M 1 , and contact E 2 .

Wiring Example 6

The circuit block below the memory cell array MCA, for example, the data cache DC is connected to a circuit block below the contact F 2 , for example, the column decoder CD, via the contact F 1 of the contact connection region RCT 1 of the memory block MB 5 , wiring M 2 , wiring M 1 , wiring M 2 , and contact F 2 .

Effect of First Embodiment

In the present embodiment, for the wirings D 0 , D 1 , and D 2 formed on the circuit layer CL, a heat-resistant metal such as tungsten (W) is used in consideration of the influence of heat during the manufacturing process of the memory layer ML formed thereafter. The heat-resistant metal has a higher resistance value than copper (Cu) and aluminum (Al). Meanwhile, the wirings M 0 , M 1 , and M 2 of metals such as copper and aluminum having low resistance have low heat resistance, and are therefore arranged on the upper layer of the memory layer ML manufactured last in the manufacturing process. Therefore, there is a problem that the wiring in the upper layer of the memory layer ML is too close together.

According to the present embodiment, since the wiring layer WIR having the same number of conductive layers 110 b as the conductive layers 110 a in the memory cell array MCA may be used as wiring, the wiring path may be greatly increased, and the wiring space in the memory layer ML may be significantly expanded.

According to the wiring examples 1 and 2, when the connection points of the circuit blocks of the circuit layer CL are displaced in the X direction, since the wiring resistance is smaller when passing through the conductive layer 110 b than when passing through the wirings D 0 , D 1 , and D 2 in the circuit layer CL, a beneficial effect of causing a large current to flow can be achieved.

According to the wiring example 3, since the wiring does not pass over the bit line BL, there is an effect that even when a high voltage is applied to the wiring, the influence on the bit line BL is small.

According to the wiring example 4, even when the wiring M 1 on the memory cell array MCA is congested by the wiring of the wiring examples 5 and 6, the wiring space may be provided by passing through the conductive layer 110 b of the wiring layer WIR.

Manufacturing Method

Next, a method of manufacturing the semiconductor storage device according to the present embodiment will be described. FIGS. 15 A to 23 C are views illustrating a method of manufacturing the wiring layer WIR. FIGS. 15 A, 16 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A, and 23 A are plan views. FIGS. 15 B, 16 B, 17 B, 18 B, 19 B, 20 B, 21 B, 22 B, and 23 B are schematic cross-sections viewed in the Y direction, of the portion cut along line X 3 -X 3 ′ in FIGS. 15 A, 16 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A, and 23 A , respectively. FIGS. 15 C, 16 C, 17 C, 18 C, 19 C, 20 C, 21 C, 22 C, and 23 C are schematic cross-sections viewed in the Y direction, of the portion cut along line X 4 -X 4 ′ in FIGS. 15 A, 16 A, 17 A, 18 A, 19 A, 20 A, 21 A, 22 A, and 23 A , respectively.

As illustrated in FIGS. 15 A to 15 C , a plurality of insulating layers 101 and a plurality of insulating layers 110 A are alternately stacked in the Z direction on the circuit layer CL. The insulating layer 101 contains, for example, silicon oxide (SiO 2 ). The insulating layer 110 A functions as a sacrificial layer and contains, for example, silicon nitride (SiN). This step is performed by, for example, a method such as a chemical vapor deposition (CVD).

Next, a resist 210 is formed on the stack including the insulating layers 101 and 110 A. The resist 210 has a pattern in which the insulating layer 110 A of the portion forming the staircase portion STP (see, for example, FIG. 6 ) of the hookup region RHU is exposed. Further, the resist has an opening 211 A that exposes the insulating layer 110 A of the portion forming the contact insertion portion 200 (see, for example, FIG. 5 ) of the wiring layer WIR. Each portion of the insulating layers 110 A and 101 not covered by the resist 210 has only one layer removed by anisotropic etching. Anisotropic etching is performed by, for example, a method such as reactive ion etching (RIE). As a result, a step 205 is formed in the hookup region RHU, and a hole 201 A is formed in the portion of the wiring layer WIR corresponding to the opening 211 A.

Subsequently, as illustrated in FIGS. 16 A to 16 C , the resist 210 is partially removed by a method such as wet etching. Thus, the portion of the resist 210 that forms the step 205 of the hookup region RHU is retracted by one stage in the X direction, and the opening 211 B that is larger than that of the previous step is formed. Then, each portion of the insulating layers 110 A and 101 not covered by the resist 210 has one additional layer removed by anisotropic etching. As a result, a two-stage step 205 and a hole 201 B with an increased depth and width are formed.

Subsequently, as illustrated in FIGS. 17 A to 17 C , the resist 210 is partially removed again. Thus, the portion of the resist 210 that forms the step 205 of the hookup region RHU is further retracted by one stage in the X direction, and the opening 211 C that is further enlarged as compared with the previous step is formed. Then, each portion of the insulating layers 110 A and 101 not covered by the resist 210 has one additional layer removed by anisotropic etching. As a result, a three-stage step 205 and a hole 201 C having an increased depth and width are formed.

Subsequently, the resist 210 is first removed, and as illustrated in FIGS. 18 A to 18 C , a new resist 210 having a different pattern is formed on the stack of the insulating layers 110 A and 101 . The portion of the resist 210 that forms the step 205 of the hookup region RHU is further retracted by one stage in the X direction. Three new openings 212 A are formed in the resist 210 . The width of the openings 212 A in the Y direction is set to be substantially the same as the width of the first opening 211 A. Then, each portion of the insulating layers 110 A and 101 not covered by the resist 210 has one layer removed by anisotropic etching. As a result, a four-stage step 205 having an increased depth and width and a hole 202 A are formed.

Subsequently, as illustrated in FIGS. 19 A to 20 C , similar to the previous step, the partial removal of the resist 210 and the anisotropic etching of the insulating layers 110 A and 101 are repeated to form the step 205 , and portions of the insulating layers 110 A and 101 exposed by the openings 212 B and 212 C are sequentially removed. As a result, steps 205 of 5 steps and 6 steps, and holes 202 B and 202 C having increased depth and width are sequentially formed.

In the same manner as in the above step, the resist 210 is first removed, and as illustrated in FIGS. 21 A to 21 C , a resist 210 having a different pattern is formed on the stack of the insulating layers 110 A and 101 . The portion of the resist 210 that forms the step 205 of the hookup region RHU is further retracted by one stage in the X direction. Two new openings 213 A are formed in the resist 210 . The width of the opening 213 A in the Y direction is set to be substantially the same as the width of the first opening 211 A. Then, each portion of the insulating layers 110 A and 101 not covered by the resist 210 has one layer removed by anisotropic etching. As a result, a seven-stage step 205 having an increased depth and width and a hole 203 A are formed.

Subsequently, as illustrated in FIGS. 22 A to 23 C , similar to the previous step, the partial removal of the resist 210 and the anisotropic etching of the insulating layers 110 A and 101 are repeated to form the step 205 , and portions of the insulating layers 110 A and 101 exposed by the openings 213 B and 213 C are sequentially removed. As a result, steps 205 of 8 stages and 9 stages, and holes 203 B and 203 C having increased depth and width are sequentially formed.

Through the above steps, the step 205 forming the staircase portion STP (see, for example, FIG. 6 ) of the hookup region RHU and the contact insertion portion 200 (see, for example, FIG. 5 ) of the wiring layer WIR may be formed. According to this method, when partial removal of the resist 210 is performed m times with n types of resist 210 patterns, a step of n×(m+1)+1 layers may be formed. In the present embodiment, the widths of the openings 211 A, 212 A, and 213 A formed in each pattern of the resist 210 before the partial removal of the resist 210 , are substantially the same in the Y direction. Therefore, the step formation in the Y direction at the contact insertion portion 200 accompanying the step forming process may be reduced to m+1 steps. As a result, the wiring region WIRa having a sufficient width can be provided in the wiring layer WIR.

FIGS. 24 to 32 are cross-sectional views illustrating a method of manufacturing the semiconductor storage device according to the present embodiment, and are schematic cross-sections viewed in the X direction, of the portion cut along line Y 1 -Y 1 ′ in FIG. 5 .

First, as illustrated in FIG. 24 , the insulating layer 150 is formed on the stack of the insulating layers 110 A and 101 so as to fill the insides of the holes 204 manufactured in the above-described steps. The insulating layer 150 includes, for example, tetraethyl orthosilicate (TEOS). This step is performed by, for example, a method such as CVD.

Next, as illustrated in FIG. 25 , the insulating layers 110 A and 101 on the end are removed from the central portion of the hole 204 in the Y direction. This step is performed by a method such as RIE.

Next, as illustrated in FIG. 26 , a plurality of memory structures 100 is formed in the X and Y directions so as to penetrate the stack of the insulating layers 110 A and 101 in the Z direction. In the figure, the memory structure 100 is not formed (or may be partially formed) in the contact connection region RCT. Further, the spacing in the X and Y directions of the memory structure 100 may be uniform as a whole, or may be arranged so that the spacing in the wiring layer WIR is coarser than the spacing in the memory cell region RMC. The memory structure 100 functions as a memory unit MU in the memory cell region RMC, and functions as a support structure HR in the wiring layer WIR. Hereinafter, the memory structure 100 that functions as the memory unit MU may be referred to as the memory structure 100 (MU), and the memory structure 100 that functions as the support structure HR may be referred to as the support structure 100 (HR).

Next, the insulating layer SHE extending in the X direction and the Z direction is formed. The insulating layer SHE divides only the upper layer of the stack of the insulating layers 110 A and 101 in the Y direction between the portions in the memory block MB of the memory cell region RMC where the two memory strings MSs are formed.

Next, as illustrated in FIG. 27 , grooves STBs extending in the X and Z directions and in the Y and Z directions are formed so as to divide the entire plurality of insulating layers 110 A and 101 in the Y and X directions on both sides of the Y direction and both sides of the X direction of the region where the contact CDMa of the contact connection region RCT is formed. Subsequently, as illustrated in FIG. 28 , the insulating layer ST 1 is formed inside the groove STB. The insulating layers ST 1 on both sides in the Y direction and the insulating layers ST 1 on both sides in the X direction of the region where the contact CDMa is formed may be formed by separate manufacturing processes.

Next, as illustrated in FIG. 29 , the entire plurality of insulating layers 110 A and 101 of the memory cell region RMC are divided in the Y direction to form grooves STAs extending in the X and Z directions for forming each memory block MB. Further, on both sides of the region between the insulating layers ST 1 of the contact connection region RCT in the Y direction, the entire plurality of insulating layers 110 A and 101 are divided in the Y direction to form grooves STAs extending in the X and Z directions. Also, between the memory cell array MCA and the wiring layer WIR, the entire plurality of insulating layers 110 A and 101 are divided in the Y direction to form grooves STAs extending in the X and Z directions.

Next, as illustrated in FIG. 30 , the plurality of insulating layers 110 A are removed through the groove STA to form a cavity 110 B. This step is performed, for example, by wet etching. At this time, the memory structure 100 (MU) and the support structure 100 (HR) support a plurality of insulating layers 101 arranged in the Z direction.

Next, as illustrated in FIG. 31 , the conductive layers 110 a and 110 b are embedded in the cavity 110 B via the groove STA. The conductive layers 110 a and 110 b are formed by, for example, a method such as CVD. At this time, the insulating layer ST 1 functions as a wall that prevents the conductive layer 110 a from entering the region where the contact CDMa is formed.

Next, as illustrated in FIG. 32 , the semiconductor storage device according to the present embodiment may be manufactured by forming contacts CDMa, CCb, and CDMb in the connection region WIRb of the wiring layer WIR and the peripheral region between the insulating layers ST 1 of the contact connection region RCT, respectively.

Further, to form the structure illustrated in FIG. 7 , where the high-dielectric film 111 such as alumina (Al 2 O 3 ) is on the surfaces of the conductive layers 110 a and 110 b , the high-dielectric film is formed on the surface of the cavity 110 B prior to the formation of the conductive layers 110 a and 110 b . In this case, by making the step of forming the conductive layer 110 a in the memory cell region RMC different from the step of forming the conductive layer 110 b in the wiring layer WIR, the high-dielectric film 111 may not be formed in the wiring layer WIR.

Effect

According to the present embodiment, the conductive layer 110 b and the insulating layer 101 b in the wiring layer WIR may be formed at the same time as the steps of forming the conductive layer 110 a and the insulating layer 101 a in the memory cell region RMC and the hookup region RHU of the related art.

Second Embodiment

FIG. 33 is a plan view of the semiconductor storage device according to a second embodiment. In FIG. 33 , the same parts as those in FIG. 3 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

In the present embodiment, two wiring layers WIR 1 and WIR 2 arranged in the X direction are provided on both sides of one memory plane MP in the Y direction.

According to the present embodiment, since a plurality of wiring layers WIR 1 and WIR 2 is provided in the X direction, the number of wiring paths may be further increased. In the present embodiment, two wiring layers WIR 1 and WIR 2 are provided in the X direction, but in other embodiments, three or more wiring layers WIR may be provided.

Third Embodiment

FIG. 34 is a plan view of the semiconductor storage device according to a third embodiment. In FIG. 34 , the same parts as those in FIG. 3 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

In the present embodiment, in addition to the wiring layer WIR of the first embodiment, or instead of the wiring layer WIR, the inner region of the edge seal ES is used as the wiring layer WIE.

FIG. 35 is a plan view illustrating an enlarged portion A 3 of FIG. 34 . FIG. 36 is a schematic cross-section viewed in the −X direction, of the portion cut along line Y 2 -Y 2 ′ in FIG. 35 .

In the present embodiment, as illustrated in FIG. 36 , the wiring layer WIE arranged inside the edge seal ES has a stacked structure including a plurality of conductive layers 110 c and insulating layers 101 c alternately stacked on the circuit layer CL, or an insulating layer 110 C as sacrificial layer not replaced with the conductive layer 110 c and an insulating layer 101 c . The conductive layer 110 c contains, for example, tungsten (W). The insulating layer 101 c contains, for example, silicon oxide (SiO 2 ). The insulating layer 110 C contains, for example, silicon nitride (SiN).

As illustrated in FIGS. 35 and 36 , the wiring layer WIE arranged inside the edge seal ES has a wiring layer region WIE 1 inside the insulating layer ST formed along the edge seal ES and a contact connection region WIE 2 outside. The wiring layer region WIE 1 has an outer wiring region WIE 1 a and an inner connection region WIE 1 b . The contact connection region WIE 2 has an inner first region WIE 2 a and an outer second region WIE 2 b.

As illustrated in FIG. 36 , the wiring layer region WIE 1 has a plurality of conductive layers 110 c stacked in the Z direction. Further, the contact connection region WIE 2 has a plurality of conductive layers 110 c in the first region WIE 2 a and a plurality of insulating layers 110 C in the second region WIE 2 b.

The lower end of a contact CCc extending in the Z direction in the insulating layer 153 is connected to the conductive layer 110 c of the connection region WIE 1 b of the wiring layer region WIE 1 . Further, the second region WIE 2 b of the contact connection region WIE 2 is provided with a contact CDMc that penetrates a plurality of insulating layers 110 C and 101 c in the Z direction and has a lower end connected to the circuit layer CL. The contact CDMc is surrounded by the insulating layer 152 so that a problem such as a short circuit does not occur even when a part of the insulating layer 110 C is replaced with the conductive layer 110 c . The upper end of the contact CCc and the upper end of the contact CDMc are connected to each other via the wirings M 0 , M 1 , and M 2 .

The stack containing the contact CDMc is usually located on the innermost side of the edge seal ES. That is, the second region WIE 2 b is also the inner region of the edge seal ES. FIG. 36 illustrates an example in which the contact CCc and the contact CDMc are connected, but they need not be connected. For example, the circuit layer CL and the stack containing the contact CDMc may be connected. A voltage such as a power supply voltage VSS is applied to the stack containing the contact CDMc.

According to the present embodiment, since the wiring layer WIE formed inside the edge seal ES surrounds the two memory planes MPs, the wiring layer WIE may provide wiring at a longer distance from one side to the other side of the memory cell array MCA than in the first and second embodiments. For example, it becomes easy to connect circuit blocks arranged at both ends of the memory plane MP.

Fourth Embodiment

FIG. 37 is a view illustrating a fourth embodiment, and is a schematic plan view of an enlarged portion A 3 of FIG. 34 . FIG. 38 is a schematic cross-section viewed in the −X direction of the portion cut along line Y 3 -Y 3 ′ in FIG. 37 . In FIGS. 37 and 38 , the same parts as those in FIGS. 35 and 36 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

In the third embodiment, the contact CDMc is provided in the second region WIE 2 b of the contact connection region WIE 2 , but in the present embodiment, the contact CDMc is provided in the first region WIE 2 a of the contact connection region WIE 2 . In this case, since the insulating layer 152 is interposed between the contact CDMc and the conductive layer 110 c , the two are not short-circuited. However, the insulating layer 152 does not have to be interposed between the contact CDMc and the conductive layer 110 c if a short-circuit between the two is intended.

Fifth Embodiment

FIG. 39 is a view illustrating a fifth embodiment, and is a schematic plan view of an enlarged portion A 3 of FIG. 34 . FIG. 40 is a schematic cross-section viewed in the −X direction of the portion cut along line Y 4 -Y 4 ′ in FIG. 39 . In FIGS. 39 and 40 , the same parts as those in FIGS. 35 and 36 are designated by the same reference numerals, and the description of the overlapping parts will be omitted.

In the present embodiment, a third region WIE 2 c is provided between the first region WIE 2 a and the second region WIE 2 b of the contact connection region WIE 2 . The third region WIE 2 c is formed by the insulating layer 154 . The contact CDMc extends in the Z direction to penetrate the insulating layer 154 .

According to the present embodiment, the insulating layer 152 around the contact CDMc used in the third and fourth embodiments is unnecessary.

Sixth Embodiment

FIG. 41 is a schematic plan view of the semiconductor storage device according to a sixth embodiment.

According to this embodiment, four wiring layers WIE 11 , WIE 12 , WIE 13 , and WIE 14 isolated from each other are provided inside the edge seal ES. The wiring layers WIE 11 and WIE 13 are arranged at both ends of the memory layer ML in the Y direction. The wiring layers WIE 12 and WIE 14 are arranged at both ends of the memory layer ML in the X direction.

According to the present embodiment, since the wiring layer WIE inside the edge seal ES is divided into four, the wiring path may be further increased. Further, in this embodiment, four wiring layers WIR 11 , WIR 12 , WIE 13 , and WIE 14 are provided, but the wiring layer WIR may be divided into five or more.

Seventh Embodiment

FIG. 42 is a schematic cross-sectional view of the semiconductor storage device according to a seventh embodiment.

This embodiment is an example of a semiconductor storage device in which the memory layer ML and the circuit layer CL are manufactured as separate chips, and finally manufactured by bonding them via pads P 1 and P 2 .

In this case, the contact CCb that is separated from the memory cell array MCA, and is connected to the conductive layer 110 b of the wiring layer WIR including the plurality of conductive layers 110 b formed in the same layer as the plurality of conductive layers 110 a is connected to the circuit layer CL via the pads P 1 and P 2 . In the present embodiment, since the wirings M 01 and M 11 of the memory layer ML, the pad P 1 , the wirings M 02 , M 12 , and M 22 of the circuit layer CL, and the pad P 2 may all be formed of a low resistance metal such as aluminum or copper, the wiring resistance may be further increased. Further, the contact CMDa is unnecessary.

Eighth Embodiment

In the above-described embodiments, descriptions have been made on an example of a NAND-type semiconductor storage device having a three-dimensional structure in which memory cells MCs are NAND-connected.

However, the present disclosure is not limited to the NAND-type semiconductor storage device.

FIG. 43 is an equivalent circuit diagram schematically illustrating a NOR-type semiconductor storage device having a three-dimensional structure according to the eighth embodiment. In this embodiment, a plurality of memory cells MCs is connected in parallel between the horizontally extending bit lines BL 0 to BL 4 and the source lines SL 0 to SL 4 , and a plurality of memory cells MCs arranged in the vertical direction is commonly driven by word lines WL 0 to WL 4 extending vertically.

Ninth And Tenth Embodiments

FIGS. 44 and 45 are equivalent circuit diagrams schematically illustrating a DRAM having a three-dimensional structure according to ninth and tenth embodiments, respectively.

In FIGS. 44 and 45 , a transistor Tr and a capacitor Cpa are inserted between the bit line BL and the plate line PL.

The DRAM of FIG. 44 has a bit line BL extending horizontally and a word line WL extending vertically. The DRAM of FIG. 45 has a bit line BL extending vertically and a word line WL extending horizontally.

Also, in the eighth to tenth embodiments, a stacked structure that is formed in the same layer as any of the wiring layers of the bit line BL, the word line WL, the source line SL, and the plate line PL and provided in a form separated from the memory cell array MCA is used as the wiring layer WIR. As a result, the various effects described above may be achieved.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.