Isolation Structures in Semiconductor Devices

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of U.S. Provisional Patent Application No. 63/322,532, titled “Semiconductor Device with Vertical Local Interconnect and Method for Forming the Same,” filed on Mar. 22, 2022, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

With advances in semiconductor technology, there has been increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and gate-all-around FETs (GAA FETs). Such scaling down has increased the complexity of semiconductor manufacturing processes.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures.

FIGS. 1 A- 1 H illustrate isometric, cross-sectional, and top-down views of a semiconductor device with isolation structures, in accordance with some embodiments.

FIGS. 2 - 5 illustrate top-down views of other semiconductor devices with isolation structures, in accordance with some embodiments.

FIG. 6 is a flow diagram of a method for fabricating a semiconductor device with isolation structures, in accordance with some embodiments.

FIGS. 7 , 8 A- 15 B, and 16 A- 22 F illustrate isometric and cross-sectional views of a semiconductor device with isolation structures at various stages of its fabrication process, in accordance with some embodiments.

Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements. The discussion of elements with the same annotations applies to each other, unless mentioned otherwise.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. As used herein, the formation of a first feature on a second feature means the first feature is formed in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.

In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.

The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes can combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures.

The present disclosure provides example semiconductor devices with stacked FETs (e.g., stacked gate-all-around (GAA) FETs) and vertical interconnect structures between adjacent stacked FETs. The present disclosure further provides example methods of forming the semiconductor devices. With the use of stacked FETs, the device density of ICs can be increased without aggressively scaling down the devices and compromising the electrical isolation between the devices in the IC. In some embodiments, each of the stacked FETs can include a stack of different conductivity type GAA FETs and/or can include a stack of the same conductivity type GAA FETs. Each of the stacked FETs can further include a channel isolation layer. The channel isolation layer can electrically isolate the channel regions of the stacked FETs from each other.

In some embodiments, the vertical interconnect structures (also referred to as “conductive bridge structures” and “through-via structures”) can provide electrical connections between top and bottom GAA FETs in a stacked FET. In some embodiments, the vertical interconnect structures can provide electrical connections between top GAA FETs and an interconnect structure on a back-side of the semiconductor device. In some embodiments, the vertical interconnect structures can provide electrical connections between bottom GAA FETs and an interconnect structure on a front-side of the semiconductor device. The vertical interconnect structures can be electrically connected to S/D contact structures of the top and/or bottom GAA FETs.

The semiconductor device can further include isolation structures formed in a cut-metal-gate (CMG) process to “cut” long metal gate structures, extending over two or more of the stacked FETs, into shorter gate portions and to electrically isolate adjacent stacked FETs from each other. One or more of the isolation structures can include dielectric fill portions and dielectric liner portions. The vertical interconnect structures can be formed in the dielectric liner portions to reduce the device area occupied by the isolation structures and the vertical interconnect structures in the semiconductor device compared to the device area occupied by vertical interconnect structures formed adjacent to isolation structures. The formation of the vertical interconnect structures in the isolation structures also relaxes the dimensional constraints on the vertical interconnect structures. Larger vertical interconnect structures can be formed in the isolation structures, which reduces the resistance of the vertical interconnect structures by about 60% to about 90% compared to the resistance of vertical interconnect structures formed adjacent to isolation structures.

Furthermore, the vertical interconnect structures can be formed in the isolation structures with fewer process steps than the number of process steps involved in forming vertical interconnect structures adjacent to isolation structures. For example, the isolation trenches (also referred to as “metal cuts”) formed using a photolithographic process and an etch process during the CMG process can be used to form both the isolation structures and the vertical interconnect structures. Portions of the isolation trenches can be filled with a dielectric material to form the dielectric fill portions. Other portions of the isolation trenches can be lined with the dielectric material to form the dielectric liner portions, which can be subsequently filled with a conductive material to form the vertical interconnect structures. Thus, a single photolithographic process and a single etch process can be used to form both the vertical interconnect structures and the isolation structures, instead of the multiple photolithographic processes and multiple etch processes used for forming vertical interconnect structures adjacent to isolation structures.

FIG. 1 A illustrates an isometric view of a semiconductor device 100 , according to some embodiments. FIGS. 1 B, 1 C, 1 D, 1 E, 1 F, and 1 G illustrate cross-sectional views of semiconductor device 100 along lines A-A, B—B, C-C, D-D, E-E, and F—F, respectively, of FIGS. 1 A- 1 H , according to some embodiments. FIG. 1 H illustrates a top-down view of semiconductor device 100 , according to some embodiments. FIGS. 1 B- 1 H illustrate views of semiconductor device 100 with additional structures that are not shown in FIG. 1 A for simplicity. The discussion of elements with the same annotations applies to each other, unless mentioned otherwise.

Referring to FIGS. 1 A- 1 H , semiconductor device 100 can include (i) a substrate 104 , (ii) a stacked FET 102 A disposed on substrate 104 , (iii) a stacked FET 102 B disposed on substrate 104 , (iv) an isolation structure 106 disposed between stacked FETs 102 A and 102 B, and (v) a vertical interconnect structure 108 disposed in isolation structure 106 . The discussion of stacked FETs 102 A and 102 B applies to each other, unless mentioned otherwise.

In some embodiments, substrate 104 can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and a combination thereof. Further, substrate 104 can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic).

In some embodiments, stacked FET 102 A can include (i) a fin structure 110 A disposed on substrate 104 , (ii) shallow trench isolation (STI) regions 112 A disposed on substrate 104 and adjacent to fin structure 110 A, (iii) a GAA FET 102 A 1 disposed on fin structure 110 A and STI regions 112 A, (iv) a GAA FET 102 A 2 disposed on GAA FET 102 A 1 , and (v) channel isolation layers 114 A disposed between GAA FETs 102 A 1 and 102 A 2 . Similarly, in some embodiments, stacked FET 102 B can include (i) a fin structure 110 B disposed on substrate 104 , (ii) STI regions 112 B disposed on substrate 104 and adjacent to fin structure 110 B, (iii) a GAA FET 102 B 1 disposed on fin structure 110 B and STI regions 112 B, (iv) a GAA FET 102 B 2 disposed on GAA FET 102 B 1 , and (v) channel isolation layers 114 B disposed between GAA FETs 102 B 1 and 102 B 2 . In some embodiments, fin structures 110 A- 110 B can include a material similar to substrate 104 and extend along an X-axis. In some embodiments, STI regions 112 A- 112 B can include an insulating material, such as silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide.

Stacked FETs 102 A and 102 B can be referred to as “complementary FETs (CFETs) 102 A and 102 B” when GAA FETs 102 A 1 - 102 B 1 have a conductivity type (e.g., n-type or p-type) different from that of GAA FETs 102 A 2 - 102 B 2 . In some embodiments, GAA FETs 102 A 1 - 102 B 1 can be n-type and GAA FETs 102 A 2 - 102 B 2 can be p-type. In some embodiments, GAA FETs 102 A 1 - 102 B 1 can be p-type and GAA FET 102 A 2 - 102 B 2 can be n-type. In some embodiments, GAA FETs 102 A 1 - 102 B 1 have a conductivity type different from each other and GAA FETs 102 A 2 - 102 B 2 have a conductivity type different from each other. In some embodiments, GAA FETs 102 A 1 - 102 A 2 can have the same conductivity type and GAA FETs 102 B 1 - 102 B 2 can have the same conductivity type.

Referring to FIGS. 1 A- 1 H , in some embodiments, GAA FET 102 A 1 can include (i) stacks of nanostructured layers 116 A 1 disposed on fin structure 110 A, (ii) gate structures 118 A 1 - 1 , 118 A 1 - 2 , and 118 A 1 - 3 surrounding nanostructured layers 116 A 1 , (iii) S/D regions 120 A 1 - 1 , 120 A 1 - 2 , and 120 A 1 - 3 disposed adjacent to nanostructured layers 116 A 1 , (iv) S/D contact structures 122 A 1 - 1 and 122 A 1 - 2 disposed on back-side of S/D regions 120 A 1 - 1 and 120 A 1 - 2 , respectively, (v) etch stop layers (ESLs) 124 A 1 disposed on S/D regions 120 A 1 - 1 , 120 A 1 - 2 , and 120 A 1 - 3 , (vi) interlayer dielectric (ILD) layers 126 A 1 disposed on ESLs 124 A 1 , and (vii) inner spacers 128 disposed adjacent to gate structures 118 A 1 - 1 , 118 A 1 - 2 , and 118 A 1 - 3 . Nanostructured layers 116 A 1 that are adjacent to and in direct contact with S/D regions 120 A 1 - 1 , 120 A 1 - 2 , and 120 A 1 - 3 function as channel regions. Nanostructured layers 116 A 1 that are disposed directly on bottom surfaces of channel isolation layers 114 A, as shown in FIGS. 1 B and 1 D , do not function as channel regions. Though a single row of channel regions is shown in FIG. 1 B , GAA FET 102 A 1 can have one or more rows channel regions.

In some embodiments, GAA FET 102 A 2 can include (i) stacks of nanostructured layers 116 A 2 disposed on channel isolation layers 114 A, (ii) gate structures 118 A 2 - 1 , 118 A 2 - 2 , and 118 A 2 - 3 surrounding nanostructured layers 116 A 2 , (iii) S/D regions 120 A 2 - 1 , 120 A 2 - 2 , and 120 A 2 - 3 disposed adjacent to nanostructured layers 116 A 2 and on ILD layers 126 A 1 , (iv) S/D contact structures 122 A 2 - 1 and 122 A 2 - 2 disposed on front-side of S/D regions 120 A 2 - 1 and 120 A 2 - 2 , respectively, (v) ESLs 124 A 2 disposed on S/D regions 120 A 2 - 1 , 120 A 2 - 2 , and 120 A 2 - 3 , (vi) ILD layers 126 A 2 disposed on ESLs 124 A 2 , (vii) inner spacers 128 A 2 disposed adjacent to gate structures 118 A 2 - 1 , 118 A 2 - 2 , and 118 A 2 - 3 , (viii) gate spacers 130 disposed adjacent to gate structures 118 A 2 - 1 , 118 A 2 - 2 , and 118 A 2 - 3 , and (ix) gate capping layers 131 A disposed on gate structures 118 A 2 - 1 , 118 A 2 - 2 , and 118 A 2 - 3 . Nanostructured layers 116 A 2 that are adjacent to and in direct contact with S/D regions 120 A 2 - 1 , 120 A 2 - 2 , and 120 A 2 - 3 function as channel regions. Nanostructured layers 116 A 2 that are disposed directly on top surfaces of channel isolation layers 114 A, as shown in FIGS. 1 B and 1 D , do not function as channel regions. Though two rows of channel regions are shown in FIG. 1 B , GAA FET 102 A 2 can have one or more rows of channel regions.

In some embodiments, GAA FET 102 B 1 can include (i) stacks of nanostructured layers 116 B 1 disposed on fin structure 110 B, (ii) gate structures 118 B 1 - 1 , 118 B 1 - 2 , and 118 B 1 - 3 surrounding nanostructured layers 116 B 1 , (iii) S/D regions 120 B 1 - 1 , 120 B 1 - 2 , and 120 B 1 - 3 disposed adjacent to nanostructured layers 116 B 1 , (iv) S/D contact structures 122 B 1 - 1 and 122 B 1 - 2 disposed on back-side of S/D regions 120 B 1 - 1 and 120 B 1 - 2 , respectively, (v) etch stop layers (ESLs) 124 B 1 disposed on S/D regions 120 B 1 - 1 , 120 B 1 - 2 , and 120 B 1 - 3 , (vi) interlayer dielectric (ILD) layers 126 B 1 disposed on ESLs 124 B 1 , and (vii) inner spacers 128 disposed adjacent to gate structures 118 B 1 - 1 , 118 B 1 - 2 , and 118 B 1 - 3 . Nanostructured layers 116 B 1 that are adjacent to and in direct contact with S/D regions 120 B 1 - 1 , 120 B 1 - 2 , and 120 B 1 - 3 function as channel regions. Nanostructured layers 116 B 1 that are disposed directly on bottom surfaces of channel isolation layers 114 B, as shown in FIG. 1 D , do not function as channel regions. GAA FET 102 B 1 can have one or more rows of channel regions.

In some embodiments, GAA FET 102 B 2 can include (i) stacks of nanostructured layers 116 B 2 disposed on channel isolation layers 114 B, (ii) gate structures 118 B 2 - 1 , 118 B 2 - 2 , and 118 B 2 - 3 surrounding nanostructured layers 116 B 2 , (iii) S/D regions 120 B 2 - 1 , 120 B 2 - 2 , and 120 B 2 - 3 disposed adjacent to nanostructured layers 116 B 2 and on ILD layers 126 B 1 , (iv) S/D contact structures 122 B 2 - 1 and 122 B 2 - 2 disposed on front-side of S/D regions 120 B 2 - 1 and 120 B 2 - 2 , respectively, (v) ESLs 124 B 2 disposed on S/D regions 120 B 2 - 1 , 120 B 2 - 2 , and 120 B 2 - 3 , (vi) ILD layers 126 B 2 disposed on ESLs 124 B 2 , (vii) inner spacers 128 B 2 disposed adjacent to gate structures 118 B 2 - 1 , 118 B 2 - 2 , and 118 B 2 - 3 , (viii) gate spacers 130 disposed adjacent to gate structures 118 B 2 - 1 , 118 B 2 - 2 , and 118 B 2 - 3 , and (ix) gate capping layers 131 B disposed on gate structures 118 B 2 - 1 , 118 B 2 - 2 , and 118 B 2 - 3 . Nanostructured layers 116 B 2 that are adjacent to and in direct contact with S/D regions 120 B 2 - 1 , 120 B 2 - 2 , and 120 B 2 - 3 function as channel regions. Nanostructured layers 116 B 2 that are disposed directly on top surfaces of channel isolation layers 114 B, as shown in FIG. 1 D , do not function as channel regions. GAA FET 102 B 2 can have one or more rows of channel regions.

In some embodiments, the gate structures of stacked FET 102 A and 102 B can have substantially equal gate lengths along an X-axis. Gate structures 118 A 1 - 1 , 118 A 1 - 2 , 118 A 1 - 3 , 118 B 1 - 1 , 118 B 1 - 2 , and 118 B 1 - 3 can be referred to as “bottom gate structures” and gate structures 118 A 2 - 1 , 118 A 2 - 2 , 118 A 2 - 3 , 118 B 2 - 1 , 118 B 2 - 2 , and 118 B 2 - 3 can be referred to as “top gate structures.”

The discussion of the elements of GAA FET 102 A 1 applies to the corresponding elements of GAA FET 102 B 1 and the discussion of the elements of GAA FET 102 A 2 applies to the corresponding elements of GAA FET 102 B 2 , unless mentioned otherwise. As used herein, the term “nanostructured” defines a structure, layer, and/or region as having a horizontal dimension (e.g., along an X- and/or Y-axis) and/or a vertical dimension (e.g., along a Z-axis) less than about 100 nm, for example about 90 nm, about 50 nm, about 10 nm, or other values less than about 100 nm. In some embodiments, nanostructured layers 116 A 1 , 116 A 2 , 116 B 1 , and/or 116 B 2 can have be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructured shapes.

In some embodiments, ESLs 124 A 1 - 124 A 2 , ILD layers 126 A 1 - 126 A 2 , inner spacers 128 A 1 - 128 A 2 , and gate spacers 130 can include an insulating material, such as silicon oxide, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and silicon germanium oxide.

Channel isolation layers 114 A can electrically isolate channel regions of GAA FET 102 A 1 from the overlying channel regions of GAA FET 102 A 2 . In some embodiments, channel isolation layers can include a dielectric material with a dielectric constant ranging from about 3 to about 25. In some embodiments, the dielectric material can include SiO2, SiN, silicon oxynitride (SiOxNy), silicon oxycarbon nitride (SiOxCyNz), HfO2, ZrO2, or a combination thereof. In some embodiments, the dielectric material can include a material with a dielectric constant lower than the dielectric constant of SiO2 (about 3.9), such as hydrogenated carbon-doped silicon oxide (SiCOH) (dielectric constant ranging from about 2.7 to about 3.3), fluorosilicate glass (FSG) (dielectric constant of about 3.5 to about 3.9), nanopore carbon doped oxide (CDO), black diamond (BD), a benzocyclobutene (BCB) based polymer, an aromatic (hydrocarbon) thermosetting polymer (ATP), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), poly-arylene ethers (PAE), diamond-like carbon (DLC) doped with nitrogen, and combinations thereof. In some embodiments, thickness of channel isolation layers 114 A can range from about 10 nm to about 30 nm for adequate electrical isolation between channel regions of GAA FETs 102 A 1 and 102 A 2 without compromising device size and manufacturing cost. In some embodiments, channel isolation layers 114 A can have side surfaces with linear side profiles (shown in FIGS. 1 B, 1 D, and 1 F ), faceted side profiles (not shown), or tapered side profiles (not shown).

In some embodiments, nanostructured layers 116 A 1 and 116 A 2 can include semiconductor materials similar to or different from substrate 104 . In some embodiments, nanostructured layers 116 A 1 and 116 A 2 can include Si, SiAs, silicon phosphide (SiP), SiC, SiCP, SiGe, Silicon Germanium Boron (SiGeB), Germanium Boron (GeB), Silicon-Germanium-Tin-Boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor materials. Though rectangular cross-sections of nanostructured layers 116 A 1 and 116 A 2 are shown, nanostructured layers 116 A 1 and 116 A 2 can have cross-sections of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal).

The discussion of gate structure 118 A 1 - 1 applies to gate structures 118 A 1 - 2 and 118 A 1 - 3 , and the discussion of gate structure 118 A 2 - 1 applies to gate structures 118 A 2 - 2 and 118 A 2 - 3 , unless mentioned otherwise. In some embodiments, gate structures 118 A 1 - 1 and 118 A 2 - 1 can include (i) interfacial oxide (IL) layers 132 disposed on nanostructured layers 116 A 1 and 116 A 2 , and (ii) high-k (HK) gate dielectric layers 134 disposed on IL layers 132 . In some embodiments, IL layers 132 can include silicon oxide (SiO 2 ), silicon germanium oxide (SiGeO x ), or germanium oxide (GeO x ). In some embodiments, HK gate dielectric layers 134 can include a high-k dielectric material, such as hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 3 ), hafnium silicate (HfSiO 4 ), zirconium oxide (ZrO 2 ), and zirconium silicate (ZrSiO 2 ).

In some embodiments, gate structures 118 A 1 - 1 and 118 A 2 - 1 can further include conductive layers 136 A 1 and 136 A 2 , respectively. Conductive layers 136 A 1 - 136 A 2 can be multi-layered structures. The different layers of conductive layers 136 A 1 - 136 A 2 are not shown for simplicity. Each of conductive layers 136 A 1 - 136 A 2 can include a WFM layer disposed on HK dielectric layer 134 and a gate metal fill layer on the WFM layer. In some embodiments, the WFM layers can include titanium aluminum (TiAl), titanium aluminum carbide (TiAIC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAIC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, or other suitable Al-based materials for n-type GAA FET 102 A 1 or 102 A 2 . In some embodiments, the WFM layers can include substantially Al-free (e.g., with no Al) Ti-based or Ta-based nitrides or alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti—Au) alloy, titanium copper (Ti—Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta—Au) alloy, and tantalum copper (Ta—Cu) for p-type GAA FET 102 A 1 or 102 A 2 . The gate metal fill layers can include a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and a combination thereof.

In some embodiments, gate structures 118 A 1 - 1 and 118 A 2 - 1 can be electrically isolated from adjacent S/D regions 120 A 1 - 1 and 120 A 2 - 1 by inner spacers 128 . In some embodiments, gate structure 118 A 2 - 1 can be electrically isolated from adjacent S/D contact structure 122 A 2 - 1 by gate spacer 130 .

In some embodiments, S/D regions 120 A 1 - 1 , 120 A 1 - 2 , and 120 A 1 - 3 can include an epitaxially-grown semiconductor material, such as Si and SiGe, and p-type dopants, such as boron and other suitable p-type dopants. In some embodiments, S/D regions 120 A 2 - 1 , 120 A 2 - 2 , and 120 A 2 - 3 can include an epitaxially-grown semiconductor material, such as Si, and n-type dopants, such as phosphorus and other suitable n-type dopants. S/D regions 120 A 1 - 1 , 120 A 1 - 2 , 120 A 1 - 3 , 120 B 1 - 1 , 120 B 1 - 2 , and 120 B 1 - 3 can be referred to as “bottom S/D regions” and S/D regions 120 A 2 - 1 , 120 A 2 - 2 , 120 A 2 - 3 , 120 B 2 - 1 , 120 B 2 - 2 , and 120 B 2 - 3 can be referred to as “top S/D regions.”

Referring to FIGS. 1 B, 1 E, and 1 G- 1 H , S/D contact structures 122 A 1 - 1 , 122 A 1 - 2 , 122 B 1 - 1 , and 122 B 1 - 2 can be referred to as “back-side S/D contact structures” and S/D contact structures 122 A 2 - 1 , 122 A 2 - 2 , 122 B 2 - 1 , and 122 B 2 - 2 can be referred to as “front-side S/D contact structures.” In some embodiments, each of front- and back-side S/D contact structures can include silicide layers 138 , contact plugs 140 disposed on silicide layers 138 , and nitride barrier layers 142 along sidewalls of contact plugs 140 . In some embodiments, silicide layers 138 can include titanium silicide (Ti x Si y ), tantalum silicide (Ta x Si), molybdenum silicide (Mo x Si y ), nickel silicide (Ni x Si y ), cobalt silicide (Co x Si y ), tungsten silicide (W x Si y ), or a combination thereof. In some embodiments, contact plugs 140 can include conductive materials, such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), copper (Cu), zirconium (Zr), stannum (Sn), silver (Ag), gold (Au), zinc (Zn), cadmium (Cd), and a combination thereof.

In some embodiments, the front-side S/D contact structures can be electrically connected to power supplies and/or other active devices through front-side interconnect structure (not shown) formed on GAA FETs 102 A 2 and 102 B 2 . In some embodiments, the back-side S/D contact structures can be electrically connected to power supplies and/or other active devices through back-side interconnect structure (not shown) formed on the back-side S/D contact structures. In some embodiments, S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 can be electrically connected to each other through vertical interconnect structure 108 , as shown in FIG. 1 G . In some embodiments, instead of both S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 being connected to vertical interconnect structure 108 , S/D contact structure 122 B 1 - 2 can be electrically connected to the front-side interconnect structure through vertical interconnect structure 108 or S/D contact structure 122 B 2 - 2 can be electrically connected to the back-side interconnect structure through vertical interconnect structure 108 . In some embodiments, instead of S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 , gate contact structures 144 B 1 - 2 and/or 144 B 2 - 2 can be electrically connected to vertical interconnect structure 108 , as shown in FIG. 1 F . Thus, vertical interconnect structure 108 can provide flexible routing for S/D regions and gate structures in stacked FETs, such as stacked FETs 102 A- 102 B.

Referring to FIGS. 1 E and 1 G , the front-side S/D contact structures can have heights H 1 -H 4 of about 15 nm to about 35 nm and the back-side S/D contact structures can have heights H 5 -H 8 of about 25 nm to about 35. Within these ranges of heights H 1 -H 8 , the front- and back-side S/D contact structures can form adequate contact areas with corresponding top and bottom S/D regions without compromising the structure of the top and bottom S/D regions and the device manufacturing cost. In some embodiments, heights H 1 -H 4 of the front-side S/D contact structures can be substantially equal to or different from each other and heights H 5 -H 8 of the back-side S/D contact structures can be substantially equal to or different from each other.

In some embodiments, the front-side S/D contact structures can have widths W 1 -W 4 of about 5 nm to about 35 nm and the back-side S/D contact structures can have widths W 5 -W 8 of about 25 nm to about 65 nm. Within these ranges of widths W 1 -W 8 , the front- and back-side S/D contact structures can form adequate contact areas with corresponding top and bottom S/D regions and can provide adequate landing areas for via structures (not shown) formed on the front- and back-side S/D contact structures. Furthermore, within these ranges of widths W 1 -W 8 , (i) S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 can form adequate contact areas with vertical interconnect structure 108 , and (ii) S/D contact structures 122 A 1 - 1 , 122 A 1 - 2 , 122 A 2 - 1 , 122 A 2 - 2 , 122 B 1 - 1 , and 122 B 2 - 1 can form adequate contact areas with corresponding top and bottom S/D regions without overlapping with vertical interconnect structure 108 and isolation structure 106 . In some embodiments, widths W 1 -W 4 of the front-side S/D contact structures can be formed substantially equal to each other and widths W 5 -W 8 of the back-side S/D contact structures can be formed substantially equal to each other for the ease of fabrication. In some embodiments, widths W 5 -W 8 of the back-side S/D contact structures can be formed greater than widths W 1 -W 4 of the front-side S/D contact structures as fabrication of the back-side S/D contact structures are less constrained than that of the front-side S/D contact structures due to fewer elements formed on the back-side of semiconductor device 100 compared to its front-side.

Referring to FIGS. 1 A and 1 C- 1 H , in some embodiments, isolation structure 106 can electrically isolate stacked FETs 102 A and 102 B from each other. FIG. 1 H does not show ESLs 124 A 2 - 124 B 2 and ILD layers 126 A 2 - 126 B 2 for simplicity. Isolation structure 106 can be formed in a CMG process (described in further detail below) to cut long gate structures (e.g., along a Y-axis) formed across fin structures 110 A and 110 B into shorter gate structures of stacked FETs 102 A and 102 B. In some embodiments, isolation structure 106 can include dielectric fill portions 106 A and a dielectric liner portion 106 B. In some embodiments, dielectric fill portions 106 A and dielectric liner portion 106 B can include a nitride material, such as silicon nitride.

In some embodiments, dielectric liner portion 106 B can have a thickness T 2 greater than thickness T 1 of dielectric fill portions 106 A because of vertical interconnect structure 108 disposed in dielectric liner portion 106 B. Dielectric liner portion 106 B can surround vertical interconnect structure 108 , as shown in FIG. 1 H . The inner sidewalls of dielectric liner portion 106 B can be in physical contact with the sidewalls of vertical interconnect structure 108 , except for the sidewall portions of vertical interconnect structure 108 in physical contact with S/D contact structures 122 B 1 - 2 and/or 122 B 2 - 2 or gate structures 144 B 1 - 2 and/or 144 B 2 - 2 . In some embodiments, vertical interconnect structure 108 can include a conductive material, such as Co, W, Ru, Ir, Ni, Os, Rh, Al, Mo, Cu, Ag, Au, and a combination thereof.

Vertical interconnect structure 108 can be formed in isolation structure 106 to reduce the device area occupied by isolation structure 106 and the vertical interconnect structure 108 compared to the device area occupied by vertical interconnect structures formed adjacent to isolation structures. The formation of vertical interconnect structure 108 in isolation structure 106 also relaxes the dimensional constraints on vertical interconnect structure 108 . Vertical interconnect structure 108 with greater thickness along a Y-axis can be formed in isolation structure 106 compared to vertical interconnect structures formed adjacent to isolation structures. As a result of larger vertical interconnect structure 108 , the resistance of vertical interconnect structure 108 can be reduced by about 60% to about 90% compared to the resistance of vertical interconnect structures formed adjacent to isolation structures.

Furthermore, vertical interconnect structure 108 can be formed in isolation structure 106 with fewer process steps than the number of process steps involved in forming vertical interconnect structures adjacent to isolation structures. For example, isolation trenches 1806 (shown in FIGS. 18 B- 18 F ) formed using a photolithographic process and an etch process during the CMG process can be used to form both isolation structure 106 and vertical interconnect structure 108 , as described below with reference to FIGS. 18 A- 20 F . A portion of the isolation trench 1806 can be lined with a dielectric material to form dielectric liner portion 106 B, which can be subsequently filled with a conductive material to form vertical interconnect structure 108 and other portions of isolation trench 1806 can be filled with the dielectric material to form dielectric fill portions 106 A. Thus, a single photolithographic process and a single etch process can be used to form both vertical interconnect structure 108 and isolation structure 106 , instead of the multiple photolithographic processes and multiple etch processes used for forming vertical interconnect structures adjacent to isolation structures.

In some embodiments, sidewalls of dielectric fill portions 106 A and dielectric liner portion 106 B along an X-axis and facing stacked FET 102 A can be substantially coplanar with each other. In some embodiments, sidewalls of dielectric fill portions 106 A and dielectric liner portion 106 B along an X-axis and facing stacked FET 102 B can be non-coplanar. In some embodiments, a portion of dielectric liner portion 106 B and a portion of vertical interconnect structure 108 facing stacked FET 102 B can be protruded from sidewalls of dielectric fill portions 106 A facing stacked FET 102 B. The protruding portions of dielectric liner portion 106 B and vertical interconnect structure 108 can be in physical contact with S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 . Due to these protruding portions, S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 can be electrically connected to vertical interconnect structure 108 with widths substantially equal to widths of other S/D contact structures of stacked FET 102 B that are not electrically connected to vertical interconnect structure 108 . The formation of the front-side S/D contact structures with substantially equal widths W 1 -W 4 and of the back-side S/D contact structures with substantially equal widths W 5 -W 8 reduces the complexity of fabrication, thus increasing manufacturing yield and decreasing manufacturing cost.

Referring to FIGS. 1 C- 1 H , in some embodiments, isolation structure 106 can have a height H 9 of about 110 nm to about 170 nm to provide adequate electrical isolation between stacked FETs 102 A and 102 B. As vertical interconnect structure 108 is disposed in isolation structure 106 , and top and bottom surfaces of vertical interconnect structure 108 are substantially coplanar with those of isolation structure 106 , vertical interconnect structure 108 can have height H 9 to provide adequate electrical connection between S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 . In some embodiments, dielectric fill portions 106 A can have a thickness T 1 of about 10 nm to about 20 nm to provide adequate electrical isolation between stacked FETs 102 A and 102 B.

In some embodiments, dielectric liner portion 106 B can have a thickness T 2 of about 30 nm to about 40 nm and a width W 9 of about 50 nm to about 220 nm or of about 1.5 contacted poly pitch (CPP) to about 4.5 CPP. In some embodiments, 1 CPP can be about 45 nm to about 48 nm and 4.5 CPP can be greater than about 200 nm. Within these ranges of thickness T 2 and width W 9 , dielectric liner portion 106 B provide adequate electrical isolation between stacked FETs 102 A and 102 B without overlapping with their S/D regions and provide adequate space to enclose vertical interconnect structure 108 . The CPP (also referred to as “gate pitch”) is defined as a sum of a distance along an X-axis between adjacent gate structures of substantially equal gate lengths (e.g., gate structures 118 B 2 - 2 and 118 B 2 - 3 ) and a gate length (e.g., GL shown in FIG. 1 H ) of one of the adjacent gate structures. The CPP is also defined as a distance along an X-axis between the symmetry lines along a Y-axis of adjacent gate structures of substantially equal gate lengths.

In some embodiments, dielectric liner portion 106 B can have a thickness T 3 of 5 nm to about 10 nm surrounding vertical interconnect structure 108 to provide adequate electrical isolation between vertical interconnect structure 108 and gate structures 118 A 1 - 2 , 118 A 1 - 3 , 118 A 2 - 2 , 118 A 2 - 3 , 118 B 1 - 2 , 118 B 1 - 3 , 118 B 2 - 2 , and 118 B 2 - 3 . Furthermore, in some embodiments, sidewalls of dielectric liner portion 106 B along a Y-axis can be aligned with sidewalls of gate spacers 130 along a Y-axis to prevent misalignment of vertical interconnect structure 108 with S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 . In some embodiments, standard cell boundary G-G can be aligned between sidewalls of isolation structure 106 and vertical interconnect structure 108 along an X-axis and facing stacked FET 102 A.

In some embodiments, vertical interconnect structure 108 can have a thickness T 4 of about 15 nm to about 25 nm to have an aspect ratio (e.g., H 9 :T 4 ) of about 5 to about 10 without compromising device size and manufacturing cost. Within these aspect ratio ranges, fabrication defects (e.g., voids) in vertical interconnect structure 108 can be prevented or minimized, thus improving the electrical conductivity of vertical interconnect structure 108 . Furthermore, vertical interconnect structure 108 can have a width W 10 of about 45 nm to about 200 nm or about 1 CPP (e.g., about 45 nm to about 48 nm) to about 4 CPP (e.g., greater than about 180 nm) to improve its electrical conductivity and to prevent misalignment with S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 . These ranges of width W 10 can also provide adequate contact area between vertical interconnect structure 108 and S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 . In some embodiments, width W 10 can be about 1 CPP to about 1.5 CPP when vertical interconnect structure 108 are electrically connected to one front- and/or one back-side S/D contact structure, such as S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 .

FIGS. 2 - 5 illustrate different top-down views of semiconductor device 100 with different configurations of isolation structures and vertical interconnect structures, according to some embodiments. FIGS. 2 - 5 illustrate views of semiconductor device 100 with additional structures that are not shown in FIGS. 1 A- 1 H for simplicity. Elements in FIGS. 2 - 5 with the same annotations as elements in FIGS. 1 A- 1 H are described above.

Referring to FIGS. 2 - 5 , stacked FETs 102 A and 102 B can include gate structures 118 A 2 - 4 , 118 A 2 - 5 , 118 B 2 - 4 , and 118 B 2 - 5 , S/D regions 120 A 2 - 3 and 120 B 2 - 3 , and S/D contact structures 122 A 2 - 3 , 122 B 2 - 3 , and 122 B 2 - 4 that are not shown in FIGS. 1 A- 1 H for simplicity. The discussion of gate structures, S/D regions, and S/D contact structures of FIGS. 1 A- 1 H applies to those of FIGS. 2 - 5 , unless mentioned otherwise.

In some embodiments, instead of isolation structure 106 and vertical interconnect structure 108 , semiconductor device 100 can have (i) an isolation structure 206 and vertical interconnect structures 208 A- 208 B, as shown in FIG. 2 , (ii) isolation structures 306 A- 306 B and vertical interconnect structures 208 A- 208 B, as shown in FIG. 3 , (iii) isolation structures 306 A and 406 and a vertical interconnect structure 208 A, as shown in FIG. 4 , or (iv) an isolation structure 506 and a vertical interconnect structure 508 , as shown in FIG. 5 , disposed between stacked FETs 102 A and 102 B. In some embodiments, isolation structure 106 and vertical interconnect structure 108 can be disposed between stacked FETs 102 A and 102 B, and the isolation structures and vertical interconnect structures of FIGS. 2 , 3 , 4 , and/or 5 can be disposed in different device areas and between different pairs of stacked FETs of semiconductor device 100 similar to the pair of stacked FETs 102 A- 102 Bs. In some embodiments, semiconductor device 100 can have any combination of the isolation structures and vertical interconnect structures shown in FIGS. 1 H and 2 - 5 .

Referring to FIG. 2 , in some embodiments, isolation structure 206 can include a dielectric fill portion 206 A and dielectric liner portions 206 B 1 - 206 B 2 . Vertical interconnect structures 208 A and 208 B can be disposed in dielectric liner portions 206 B 1 and 206 B 2 , respectively. The discussion of dielectric liner portion 106 B and vertical interconnect structure 108 applies to dielectric liner portion 206 B 2 and vertical interconnect structure 208 B, respectively, unless mentioned otherwise. Isolation structure 206 can include a material similar to that of isolation structure 106 and vertical interconnect structures 208 A- 208 B can include a material similar to that of vertical interconnect structure 108 . Dielectric liner portion 206 B 1 can have thicknesses T 5 and T 6 substantially equal to thicknesses T 2 and T 3 , respectively, of dielectric liner portion 206 B 2 . Vertical interconnect structure 208 A can have a thickness T 7 substantially equal to thickness T 4 of vertical interconnect structure 208 B. Isolation structure 206 and vertical interconnect structures 208 A- 208 B can have heights similar to height H 9 of isolation structure 106 and vertical interconnect structures 108 . Vertical interconnect structures 208 A- 208 B can have aspect ratios similar to that of vertical interconnect structure 108 .

Vertical interconnect structure 208 A can be configured to be in physical contact with two S/D contact structures 122 B 2 - 1 and 122 B 2 - 2 and vertical interconnect structure 208 B can be configured to be in physical contact with one of S/D contact structures 122 B 2 - 1 . In some embodiments, vertical interconnect structure 208 A can have a width W 12 of about 2 CPP to about 4 CPP to improve its electrical conductivity and to prevent misalignment with S/D contact structures 122 B 2 - 1 and 122 B 2 - 2 . This range of width W 12 can also provide adequate contact area between vertical interconnect structure 208 A and S/D contact structures 122 B 2 - 1 and 122 B 2 - 2 . In some embodiments, width W 11 can be about 2 CPP to about 2.5 CPP when vertical interconnect structure 208 A are electrically connected to two S/D contact structures, such as S/D contact structures 122 B 2 - 1 and 122 B 2 - 2 .

Isolation structure 206 can be configured to (i) align dielectric fill portion 206 A with S/D contact structures (e.g., S/D contact structure 122 B 2 - 3 ) that are not electrically connected to any vertical interconnect structures, and (ii) align dielectric liner portions 206 B 1 - 206 B 2 with S/D contact structures (e.g., S/D contact structures 122 B 2 - 1 , 122 B 2 - 2 , and 122 B 2 - 4 ) that are electrically connected to vertical interconnect structures (e.g., vertical interconnect structures 208 A and 208 B). In some embodiments, dielectric liner portion 206 B 1 can have a thickness T 5 of about 30 nm to about 40 nm and a width W 11 of about 50 nm to about 160 nm or of about 2.5 CPP to about 4.5 CPP. Within these ranges of thickness T 5 and width W 11 , dielectric liner portion 206 B 1 provide adequate electrical isolation between stacked FETs 102 A and 102 B without overlapping with their S/D regions and provide adequate space to enclose vertical interconnect structure 208 A.

In some embodiments, thickness T 6 of dielectric liner portion 206 B 1 surrounding vertical interconnect structure 208 A provide adequate electrical isolation between vertical interconnect structure 208 A and gate structures 118 A 2 - 1 , 118 A 2 - 2 , 118 A 2 - 3 , 118 B 2 - 1 , 118 B 2 - 2 , and 118 B 2 - 3 . In some embodiments, sidewalls of dielectric liner portion 206 B 1 along a Y-axis can be aligned with sidewalls of gate spacers 130 along a Y-axis to prevent misalignment of vertical interconnect structure 208 A with SID contact structures 122 B 2 - 1 and 122 B 2 - 2 . In some embodiments, sidewalls of dielectric liner portion 206 B 2 along a Y-axis can be aligned with sidewalls of gate spacers 130 along a Y-axis to prevent misalignment of vertical interconnect structure 208 B with SID contact structure 122 B 2 - 4 .

Referring to FIG. 3 , in some embodiments, semiconductor device 100 can have segmented isolation structures 306 A and 306 B, which are spaced apart from each other along an X-axis. In some embodiments, isolation structures 306 A and 306 B can be similar to dielectric liner portions 206 B 1 and 206 B 2 , respectively. However, unlike dielectric liner portions 206 B 1 and 206 B 2 , isolation structures 306 A and 306 B are not connected to each other through a dielectric fill portion, such as dielectric fill portion 206 A. Vertical interconnect structures 208 A and 208 B can be disposed in isolation structures 306 A and 306 B, respectively.

Referring to FIG. 4 , in some embodiments, semiconductor device 100 can have segmented isolation structures 306 A and 406 , which are spaced apart from each other along an X-axis. In some embodiments, isolation structure 406 can be similar to dielectric fill portion 106 A.

Referring to FIG. 5 , in some embodiments, isolation structure 506 can include a dielectric fill portion 506 A and a dielectric liner portion 506 B. Vertical interconnect structure 508 can be disposed in dielectric liner portion 506 B. Dielectric liner portion 506 B can be similar to dielectric liner portion 206 A, but unlike dielectric liner portion 206 A, dielectric liner portion 506 B can be in physical contact with S/D contact structures of both stacked FETs 102 A and 102 B. Vertical interconnect structure 508 can be similar to vertical interconnect structure 208 A, but unlike vertical interconnect structure 208 A, vertical interconnect structure 508 can be in physical contact with S/D contact structures of both stacked FETs 102 A and 102 B. That is, vertical interconnect structure 508 can be electrically connected to S/D contact structures 122 A 2 - 1 and/or 122 A 2 - 2 and S/D contact structures 122 B 2 - 1 and/or 122 B 2 - 2 . Furthermore, unlike isolation structure 206 , the symmetry line of isolation structure 506 can be substantially aligned with standard cell boundary G-G.

FIG. 6 is a flow diagram of an example method 600 for fabricating semiconductor devices 100 shown in FIGS. 1 A- 1 H , according to some embodiments. For illustrative purposes, the operations illustrated in FIG. 6 will be described with reference to the example fabrication process for fabricating semiconductor devices 100 as illustrated in FIGS. 7 , 8 A- 15 B, and 16 A- 22 F . FIG. 7 is an isometric view of semiconductor device 100 at a stage of fabrication, according to some embodiments. FIGS. 8 A- 15 A are cross-sectional views of semiconductor devices 100 along lines A-A of FIGS. 1 A and 1 D- 1 H at various stages of fabrication, according to some embodiments. FIGS. 8 B- 15 B are cross-sectional views of semiconductor devices 100 along lines H—H of FIGS. 1 A and 1 D- 1 H at various stages of fabrication, according to some embodiments.

FIGS. 16 A- 22 A are cross-sectional views of semiconductor devices 100 along lines A-A of FIGS. 1 A and 1 D- 1 H at various stages of fabrication, according to some embodiments. FIGS. 16 B- 22 B are cross-sectional views of semiconductor devices 100 along lines B-B of FIGS. 1 A and 1 D- 1 H at various stages of fabrication, according to some embodiments. FIGS. 16 C- 22 C are cross-sectional views of semiconductor devices 100 along lines C-C of FIGS. 1 A- 1 C and 1 H at various stages of fabrication, according to some embodiments. FIGS. 16 D- 22 D are cross-sectional views of semiconductor devices 100 along lines D-D of FIGS. 1 A- 1 C and 1 H at various stages of fabrication, according to some embodiments. FIGS. 16 E- 22 E are cross-sectional views of semiconductor devices 100 along lines E-E of FIGS. 1 A- 1 C and 1 H at various stages of fabrication, according to some embodiments. FIGS. 16 F- 22 F are cross-sectional views of semiconductor devices 100 along lines F-F of FIGS. 1 A- 1 C and 1 H at various stages of fabrication, according to some embodiments.

Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method 600 may not produce a semiconductor device 100 . Accordingly, it is understood that additional processes can be provided before, during, and after method 600 , and that some other processes may only be briefly described herein. Elements in FIGS. 7 - 15 B and 16 A- 22 F with the same annotations as elements in FIGS. 1 A- 1 H are described above.

Referring to FIG. 6 , in operation 605 , first and second stacks of superlattice structures are formed on first and second fin structures, respectively. For example, as shown in FIG. 7 , first and second stacks of superlattice structures 746 A and 746 B are formed on first and second fin structures 110 A and 110 B, respectively. First stack of superlattice structure 746 A can include first and second superlattice structures 746 A 1 and 746 A 2 and a nanostructured isolation layer 714 A disposed between first and second superlattice structures 746 A 1 and 746 A 2 . Second stack of superlattice structure 746 B can include first and second superlattice structures 746 B 1 and 746 B 2 and a nanostructured isolation layer 714 B disposed between first and second superlattice structures 746 B 1 and 746 B 2 .

Each of superlattice structures 746 A 1 - 746 A 2 and 746 B 1 - 746 B 2 can include nanostructured layers 716 and 748 . In some embodiments, nanostructured layer 716 can include Si and nanostructured layer 748 can include SiGe. Nanostructured layers 716 can form nanostructured layers 116 A 1 - 116 A 2 and 116 B 1 - 116 B in subsequent processing. Nanostructured isolation layers 714 A- 714 B can form channel isolation layers 114 A- 114 B in subsequent processing. In some embodiments, the formation of first and second stacks of superlattice structures 746 A and 746 B can include epitaxially growing the materials of nanostructured layers 716 and 748 and depositing the material of nanostructured isolation layers 714 A- 714 B on substrate 104 , followed by a photolithography process and an etching process.

Referring to FIG. 6 , in operation 610 , polysilicon structures are formed on the first and second stacks of superlattice structures. For example, as shown in FIGS. 8 A- 8 B , polysilicon structures 818 are formed on first and second stacks of superlattice structures 746 A and 746 B.

Referring to FIG. 6 , in operation 615 , bottom S/D regions are formed on the first and second fin structures and top S/D regions are formed on the bottom S/D regions. For example, as described with reference to FIGS. 9 A- 12 B , S/D regions 120 A 1 - 1 , 120 A 1 - 2 , 120 B 1 - 1 , and 120 B 1 - 2 , referred to as “bottom S/D regions,” are formed on fin structures 110 A and 110 B, and S/D regions 120 A 2 - 1 , 120 A 2 - 2 , 120 B 2 - 1 , and 120 B 2 - 2 , referred to as “top S/D regions,” are formed on the bottom S/D regions.

The formation of the bottom S/D regions can include sequential operations of (i) forming S/D openings 952 , as shown in FIGS. 9 A- 9 B , by etching first and second stacks of superlattice structures 746 A and 746 B through openings 850 (shown in FIGS. 8 A- 8 B ), and (ii) epitaxially growing a semiconductor layer with a first conductivity type dopants (e.g., p-type dopants) in S/D openings 952 to form the structures of FIGS. 10 A- 10 B . In some embodiments, inner spacers 128 can be formed between operations (i) and (ii) of the formation process of the bottom S/D regions, as shown in FIGS. 9 A- 9 B . The formation of the bottom S/D regions can be followed by the formation of ESLs 124 A 1 - 124 B 1 and ILD layers 126 A 1 - 126 B 1 on the bottom S/D regions, as shown in FIGS. 11 A- 11 B .

The formation of the top S/D regions can include epitaxially growing a semiconductor layer with a second conductivity type dopants (e.g., n-type dopants) in S/D openings 952 to form the structures of FIGS. 12 A- 12 B . The semiconductor layer can epitaxially grow on the sidewalls of nanostructured layers 116 A 2 and 116 B 2 facing S/D openings 952 . During the epitaxial growth of the semiconductor layer, the semiconductor layer can extend laterally and vertically to substantially fill S/D openings 952 . The semiconductor layer does not grow epitaxially on the non-semiconductor material of inner spacers 128 and ILD layers 126 A 1 - 126 B 1 . As a result, in some embodiments, there can be air gaps (not shown) at the interfaces between the top S/D regions and inner spacers 128 and between the top S/D regions and ILD layers 126 A 1 - 126 B 1 . In some embodiments, top surfaces of the top S/D regions can be substantially coplanar with bottom surfaces of polysilicon structures 818 , as shown in FIGS. 12 A- 12 B . Following the formation of the top S/D regions, ESLs 124 A 2 - 124 B 2 and ILD layers 126 A 2 - 126 B 2 can be formed, as shown in FIGS. 13 A- 13 B .

Referring to FIG. 6 , in operation 620 , bottom gate structures are formed on the first and second fin structures and top gate structures are formed on the bottom gate structures. For example, as described with reference to FIGS. 13 A- 15 B and 16 A- 16 F , gate structures 1518 A- 1 , 1518 A- 2 , and 1518 A- 3 , referred to as “bottom gate structures,” are formed on fin structures 110 A and 110 B, and gate structures 1518 B- 1 , 1518 B- 2 , and 1518 B- 3 , referred to as “top gate structures,” are formed on the bottom gate structures.

The formation of the bottom gate structures can include sequential operations of (i) forming gate openings 1318 , as shown in FIGS. 13 A- 13 B , by etching polysilicon structures 818 and nanostructured layers 748 from the structures of FIGS. 12 A- 12 B , (ii) forming IL layers 132 on exposed regions of nanostructured layers 116 A 1 - 116 A 2 and 116 B 1 - 116 B 2 in gate openings 1318 , as shown in FIGS. 14 A- 14 B , (iii) depositing HK gate dielectric layers 134 on IL layers 132 , as shown in FIGS. 14 A- 14 B , (iv) depositing conductive layers 1436 on HK gate dielectric layers 134 , as shown in FIGS. 14 A- 14 B , and (v) etching conductive layers 1436 from gate openings 1318 above channel isolation layers 114 A- 114 B to form bottom gate structures as shown in FIGS. 15 A- 15 B . Conductive layers 1436 can have a material similar to that of conductive layers 136 A 1 discussed above. The formation of the top gate structures can include depositing conductive layers 1536 in gate openings 1318 above channel isolation layers 114 A- 114 B, followed by a chemical mechanical polishing (CMP) process to form the top gate structures shown in FIGS. 16 A- 16 C and 16 E . The formation of the top gate structures can be followed by the formation of ESLs 124 A 2 - 124 B 2 and ILD layers 126 A 2 - 126 B 2 on the top S/D regions, as shown in FIGS. 16 D and 16 F .

Referring to FIG. 6 , in operation 625 , an isolation trench is formed to cut the top and bottom gate structures into shorter gate structures. For example, as described with reference to FIGS. 17 A- 18 F , an isolation trench 1806 is formed through the top and bottom gate structures to cut the top and bottom gate structures into shorter gate structures of GAA FETs 102 A 1 - 102 A 2 and 102 B 1 - 102 B 2 . The formation of isolation trench 1806 through the top and bottom gate structures can be referred to as the “CMG process.”

The formation of isolation trench 1806 can include sequential operations of (i) depositing a nitride layer 1754 on the structures of FIGS. 16 A- 16 F , (ii) depositing a photoresist layer 1756 on nitride layer 1754 , (iii) forming openings 1757 in nitride layer 1754 and photoresist layer 1756 using a lithographic patterning process and an etching process, as shown in FIGS. 17 A- 17 F , (iv) etching portions of the top and bottom gate structures, ESLs 124 A 1 - 124 B 2 , ILD layers 126 A 1 - 126 B 2 , and STI regions 112 A- 112 B through openings 1757 in patterned nitride layer 1754 and patterned photoresist layer 1756 to form isolation trench 1806 , as shown in FIGS. 18 B- 18 F . Isolation trench 1806 is not visible in the cross-sectional view of FIG. 18 A . In subsequent processing, (i) the portion of isolation trench 1806 visible in FIG. 18 B can form the portions of isolation structure 106 and vertical interconnect structure 108 shown along line B-B in FIG. 1 H , (ii) the portion of isolation trench 1806 visible in FIGS. 18 C and 18 D can form the portions of isolation structure 106 shown along lines C-C and D-D, respectively in FIG. 1 H , and (iii) the portion of isolation trench 1806 visible in FIGS. 18 E and 18 F can form the portions of isolation structure 106 and vertical interconnect structure 108 shown along lines E-E and F—F, respectively in FIG. 1 H .

In some embodiments, the formation of isolation trench 1806 includes forming a first portion (shown in FIGS. 18 C- 18 D ) with a dimension T 1 and a second portion (shown in FIGS. 18 E- 18 F ) with a dimension T 2 , which is greater than dimension T 1 . The first portion of isolation trench 1806 corresponds to the subsequently-formed dielectric fill portion 106 A (shown in FIGS. 20 C- 20 D ) and the second portion of the isolation trench 1806 corresponds to the subsequently-formed dielectric liner portion 106 B (shown in FIGS. 20 E- 20 F ). In some embodiments, isolation trench 1806 can be formed with a height H 10 of about 180 nm to about 220 nm, dimension T 1 of about 10 nm to about 20 nm, and dimension T 2 of about 30 nm to about 40 nm. These ranges of height H 10 and dimension T 1 -T 2 can provide the first portion of isolation trench with an aspect ratio (e.g., H 10 :T 1 ) of about 9 to about 22 and the second portion of isolation trench with an aspect ratio (e.g., H 10 :T 2 ) of about 5 to about 7 without compromising device size and manufacturing cost. Within these aspect ratio ranges, fabrication defects (e.g., voids) in subsequently-formed isolation structure 106 and vertical interconnect structure 108 can be prevented or minimized.

Referring to FIG. 6 , in operation 630 , an isolation structure with a fill portion and a liner portion is formed in the isolation trench. For example, as described with reference to FIGS. 19 B- 19 F , isolation structure 106 with dielectric fill portion 106 A and dielectric liner portion 106 B are formed in the first and second portions of isolation trench 1806 , respectively. The formation of dielectric fill portion 106 A and dielectric liner portion 106 B can include depositing a nitride layer 1906 with a thickness T 3 of about 5 nm to about 10 nm on the structures of FIGS. 18 A- 18 F to form the structures of FIGS. 19 A- 19 F . This range of thickness T 3 can facilitate the merging of nitride layer 1906 deposited on sidewalls of the first portion of isolation trench 1806 to form dielectric fill portion 106 A, as shown in FIGS. 19 C- 19 D . Below this range of thickness T 3 , nitride layer 1906 deposited on sidewalls of the first portion of isolation trench 1806 may not merge to fill the first portion of isolation trench 1806 . On the other hand, above this range of thickness T 3 , nitride layer 1906 may form an overhang at the opening of the first portion of isolation trench 1806 and constrict or close the opening of the first portion, thus preventing the first portion of isolation trench 1806 from being adequately filled with nitride layer 1906 .

Referring to FIG. 6 , in operation 635 , a vertical interconnect structure is formed in the liner portion of the isolation structure. For example, as described with reference to FIGS. 20 B and 20 E- 20 F , vertical interconnect structure 108 is formed in dielectric liner portion 106 B. The formation of vertical interconnect structure 108 can include depositing a conductive material on the structures of FIGS. 19 A- 19 F , followed by a CMP process to form the structures of FIGS. 20 A- 20 F . The deposition process fills the second portion of isolation trench 1806 with the conductive material, as shown in FIGS. 20 B and 20 E- 20 F . The CMP process can substantially coplanarize top surfaces of top gate structures, vertical interconnect structure 108 , dielectric fill portion 106 A, and dielectric liner portion 106 B. Vertical interconnect structure 108 is not visible in the cross-sectional views of FIGS. 20 A and 20 C- 20 D .

Referring to FIG. 6 , in operation 640 , front-side S/D contact structures are formed on front-side surfaces of the top S/D regions. For example, as described with reference to FIGS. 21 A, 21 D, and 21 F , front-side S/D contact structures 122 A 2 - 1 , 122 A 2 - 2 , 122 B 2 - 1 , and 122 B 2 - 2 are formed on front-side surfaces of top S/D regions 120 A 2 - 1 , 120 A 2 - 2 , 120 B 2 - 1 , and 120 B 2 - 2 . Front-side S/D contact structures are not visible in the cross-sectional views of FIGS. 21 B- 21 C and 21 E . In some embodiments, gate capping layers 131 A- 131 B (shown in FIGS. 21 A, 21 C, and 21 E ) can be formed prior to forming the front-side S/D contact structures.

Referring to FIG. 6 , in operation 645 , back-side S/D contact structures are formed on back-side surfaces of the bottom S/D regions. For example, as described with reference to FIGS. 22 A, 22 D, and 22 F , back-side S/D contact structures 122 A 1 - 1 , 122 A 1 - 2 , 122 B 1 - 1 , and 122 B 1 - 2 are formed on back-side surfaces of bottom S/D regions 120 A 2 - 1 , 120 A 2 - 2 , 120 B 2 - 1 , and 120 B 2 - 2 . Back-side S/D contact structures are not visible in cross-sectional views of FIGS. 22 B- 22 C and 22 E . The formation of the back-side S/D contact structures can include sequential operations of (i) thinning or removing substrate 104 , as shown in FIGS. 22 A- 22 F , (ii) forming S/D contact openings (not shown) by removing portions of fin structures 110 A- 110 B under the bottom S/D regions, (iii) forming silicide layers 138 in the S/D contact openings, as shown in FIGS. 22 A, 22 D , and 22 F, and (iv) forming contact plugs 140 on silicide layers 138 , as shown in FIGS. 22 A, 22 D, and 22 F . In some embodiments, a portion of dielectric liner portion 106 B in physical contact with substrate 104 , as shown in FIGS. 21 B- 21 F can be removed during the thinning or removal of substrate 104 , as shown in FIGS. 22 B- 22 F .

The present disclosure provides example semiconductor devices (e.g., semiconductor device 100 ) with stacked FETs (e.g., stacked FETs 102 A- 102 B) and vertical interconnect structures (e.g., vertical interconnect structures 108 , 208 A- 208 B, and 508 ) between adjacent stacked FETs. The present disclosure further provides example methods (e.g., method 600 ) of forming the semiconductor devices. With the use of stacked FETs, the device density of ICs can be increased without aggressively scaling down the devices and compromising the electrical isolation between the devices in the IC. In some embodiments, each of the stacked FETs can include a stack of different conductivity type GAA FETs (e.g., GAA FETs 102 A 1 - 102 A 2 ) and/or can include a stack of the same conductivity type GAA FETs. Each of the stacked FETs can further include a channel isolation layer (e.g., channel isolation layers 114 A- 114 B). The channel isolation layer can electrically isolate the channel regions of the stacked FETs from each other.

In some embodiments, the vertical interconnect structures (also referred to as “conductive bridge structures” and “through-via structures”) can provide electrical connections between top and bottom GAA FETs (e.g., GAA FETs 102 B 1 - 102 B 2 ) in a stacked FET (e.g., stacked FET 102 B). In some embodiments, the vertical interconnect structures can provide electrical connections between top GAA FETs and an interconnect structure on a back-side of the semiconductor device. In some embodiments, the vertical interconnect structures can provide electrical connections between bottom GAA FETs and an interconnect structure on a front-side of the semiconductor device. The vertical interconnect structures can be electrically connected to S/D contact structures (e.g., S/D contact structures 122 B 1 - 2 and 122 B 2 - 2 ) of the top and/or bottom GAA FETs (e.g., GAA FETs 102 B 1 - 102 B 2 ).

The semiconductor device can further include isolation structures (e.g., isolation structures 106 , 206 , 306 A- 306 B, 406 , and 506 ) formed in a CMG process to “cut” long metal gate structures, extending over two or more of the stacked FETs, into shorter gate portions and to electrically isolate adjacent stacked FETs from each other. One or more of the isolation structures can include dielectric fill portions (e.g., dielectric fill portions 106 A, 206 A, 406 , and 506 A) and dielectric liner portions (e.g., dielectric liner portions 106 B, 206 B 1 , 206 B 2 , 306 A- 306 B, and 506 B). The vertical interconnect structures can be formed in the dielectric liner portions to reduce the device area occupied by the isolation structures and the vertical interconnect structures in the semiconductor device compared to the device area occupied by vertical interconnect structures formed adjacent to isolation structures. The formation of the vertical interconnect structures in the isolation structures also relaxes the dimensional constraints on the vertical interconnect structures. Larger vertical interconnect structures can be formed in the isolation structures, which reduces the resistance of the vertical interconnect structures by about 60% to about 90% compared to the resistance of vertical interconnect structures formed adjacent to isolation structures.

Furthermore, the vertical interconnect structures can be formed in the isolation structures with fewer process steps than the number of process steps involved in forming vertical interconnect structures adjacent to isolation structures. For example, the isolation trenches (e.g., isolation trench 1806 ) formed using a photolithographic process and an etch process during the CMG process (e.g., operation 625 of method 600 ) can be used to form both the isolation structures and the vertical interconnect structures. Portions of the isolation trenches can be filled with a dielectric material to form the dielectric fill portions (e.g., operation 630 of method 600 ). Other portions of the isolation trenches can be lined with the dielectric material to form the dielectric liner portions (e.g., operation 630 of method 600 ), which can be subsequently filled with a conductive material to form the vertical interconnect structures (e.g., operation 630 of method 600 ). Thus, a single photolithographic process and a single etch process can be used to form both the vertical interconnect structures and the isolation structures, instead of the multiple photolithographic processes and multiple etch processes used for forming vertical interconnect structures adjacent to isolation structures.

In some embodiments, a semiconductor device includes a first FET, a second FET, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion of the isolation structure and conductively coupled to a S/D region of the second array of S/D regions.

In some embodiments, a semiconductor device includes a first stacked FET, a second stacked FET, an isolation structure, and a vertical interconnect structure. The first stacked FET includes a first GAA FET of a first conductivity type and a second GAA FET of a second conductivity type disposed on the first GAA FET. The first and second conductivity types are different from each other. The second stacked FET includes a third GAA FET of the first conductivity type and a fourth GAA FET of the second conductivity type disposed on the third GAA FET. The isolation structure includes a dielectric fill portion and a dielectric liner portion disposed between the first and second stacked FETs. The vertical interconnect structure is surrounded by the dielectric liner portion and conductively coupled to S/D regions of the third and fourth GAA FETs.

In some embodiments, a method includes forming first and second fin structures on a substrate, forming first and second arrays of S/D regions on the first and second fin structures, respectively, forming third and fourth arrays of S/D regions on the first and second arrays of S/D regions, respectively, forming an array of gate structures on the first and second fin structures, forming an isolation trench through the array of gate structures and between the first and second arrays of S/D regions, depositing a nitride layer in the isolation trench to fill a first portion of the isolation trench and form a liner along sidewalls of a second portion of the isolation trench, and depositing a conductive material on the liner to fill the second portion of the isolation trench.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.