PMOS Voltage Selection Circuit with an Auxiliary Selection Circuit to Prevent a Floating Output

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No. 63/388,258, filed on Jul. 12, 2022. The content of the application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is related to electronic circuits, and in particular, to a selection circuit for enhancing voltage supply.

2. Description of the Prior Art

Electronic devices frequently utilize a plurality of supply voltages to achieve various functions. For example, a non-volatile memory device can employ a lower voltage of 2.5V for reading memory cells and employ a higher voltage of 6V for programming the memory cells. In such a case, an electronic device is configured to output the lower voltage during a read operation and output the higher voltage during a program operation.

In the related, a selection circuit is employed in the electronic device to select between the lower voltage and the higher voltage. Nevertheless, the conventional selection circuit typically requires additional control signals to control the voltage output, increasing circuit complexity and circuit area. In another approach, the electronic device employs a selection circuit to output a highest one of the plurality of supply voltages to the subsequent circuit for high-voltage applications. However, when the plurality of supply voltages are close or equal to each other, the selection circuit will be shut off, and output a voltage lower than all of the supply voltages, leading to degradation of performance of the high-voltage applications (e.g., unable to program the memory cells).

SUMMARY OF THE INVENTION

According to an embodiment of the invention, a selection circuit includes a main selection circuit and an auxiliary selection circuit. The main selection circuit includes a first main transistor and a second main transistor. The auxiliary selection circuit includes a first auxiliary transistor, a second auxiliary transistor, a third auxiliary transistor, and a fourth auxiliary transistor. The first main transistor includes a control terminal configured to receive a second voltage, a first terminal configured to receive a first voltage, a second terminal coupled to an output terminal, and a bulk terminal coupled to the output terminal. The second main transistor includes a control terminal configured to receive the first voltage, a first terminal configured to receive the second voltage, a second terminal coupled to the output terminal, and a bulk terminal coupled to the output terminal. The first auxiliary transistor includes a control terminal, a first terminal configured to receive the first voltage, a second terminal coupled to the output terminal, and a bulk terminal coupled to the output terminal. The second auxiliary transistor includes a control terminal coupled to the control terminal of the first auxiliary transistor, a first terminal configured to receive the second voltage, a second terminal coupled to the output terminal, and a bulk terminal coupled to the output terminal. The third auxiliary transistor includes a control terminal configured to receive the second voltage, a first terminal configured to receive the first voltage, a second terminal coupled to the control terminal of the first auxiliary transistor, a bulk terminal coupled to the control terminal of the first auxiliary transistor. The fourth auxiliary transistor includes a control terminal configured to receive the first voltage, a first terminal configured to receive the second voltage, a second terminal coupled to the control terminal of the first auxiliary transistor, a bulk terminal coupled to the control terminal of the first auxiliary transistor.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit schematic of a selection circuit according to an embodiment of the invention.

FIG. 2 shows a schematic diagram of the selection circuit in FIG. 1 for the first voltage equal to the second voltage.

FIG. 3 shows a schematic diagram of the selection circuit in FIG. 1 for the first voltage greater than the second voltage.

FIG. 4 shows a schematic diagram of the selection circuit in FIG. 1 for the first voltage less than the second voltage.

DETAILED DESCRIPTION

FIG. 1 is a circuit schematic of a selection circuit 1 according to an embodiment of the invention. The selection circuit 1 may receive a first voltage V 1 and a second voltage V 2 , and output an output voltage VS according to the first voltage V 1 and the second voltage V 2 . In some embodiments, the first voltage V 1 may be a system voltage in a memory system, the second voltage V 2 may be a programming voltage in the memory system, and the output voltage VS may be used to operate a memory circuit to perform a read operation, a program operation and/or an erase operation. The first voltage V 1 and the second voltage V 2 may be equal to or different from each other. When the first voltage V 1 and the second voltage V 2 are different from each other, the selection circuit 1 may output a higher one of the first voltage V 1 and the second voltage V 2 as the output voltage VS. When the first voltage V 1 and the second voltage V 2 are equal or close to each other, the selection circuit 1 may output the output voltage VS at a level close to the first voltage V 1 and the second voltage V 2 . For example, if the first voltage V 1 is 2.5V, the second voltage V 2 is 6V, the selection circuit 1 may output 6V as the output voltage VS. If the first voltage V 1 and the second voltage V 2 are both 2.5V, the selection circuit 1 may output 2.495V as the output voltage VS. In this fashion, the output voltage VS is equal or close to the highest one of the first voltage V 1 and the second voltage V 2 without being left floating, thereby enhancing voltage supply and enhancing performance of the high-voltage applications.

The selection circuit 1 may include a main selection circuit 10 and an auxiliary selection circuit 12 . As used herein, the first voltage V 1 and the second voltage V 2 are referred to as being different if the first voltage V 1 and the second voltage V 2 are different by more than a predetermined amount; and the first voltage V 1 and the second voltage V 2 are referred to as being close if the first voltage V 1 and the second voltage V 2 are different by less than the predetermined amount. The predetermined amount may be the threshold voltage of a transistor in the selection circuit 1 , and may be 0.6V. When the first voltage V 1 and the second voltage V 2 are different, the main selection circuit 10 may select to a higher one of the first voltage V 1 and the second voltage V 2 as the output voltage VS. When the first voltage V 1 and the second voltage V 2 are equal, the auxiliary selection circuit 12 may pull the output voltage VS to a first level close to but less than the first voltage V 1 and the second voltage V 2 . When the first voltage and the second voltage are close but not equal, both the main selection circuit 10 and the auxiliary selection circuit 12 may pull the output voltage VS to a second level close to but less than the higher one of the first voltage V 1 and the second voltage V 2 . The second level may be equal to or different from the first level.

The main selection circuit 10 may include a first main transistor Ma and a second main transistor Mb. The auxiliary selection circuit 12 may include a first auxiliary transistor M 1 , a second auxiliary transistor M 2 , a third auxiliary transistor M 3 , and a fourth auxiliary transistor M 4 .

The first main transistor Ma includes a control terminal configured to receive the second voltage V 2 , a first terminal configured to receive the first voltage V 1 , a second terminal coupled to an output terminal 100 , and a bulk terminal coupled to the output terminal 100 . The output terminal 100 may provide the output voltage VS. The first main transistor Ma may further include a body diode Da including an anode coupled the first terminal of the first main transistor Ma and a cathode coupled the second terminal of the first main transistor Ma. The second main transistor Mb includes a control terminal configured to receive the first voltage V 1 , a first terminal configured to receive the second voltage V 2 , a second terminal coupled to the output terminal 100 , and a bulk terminal coupled to the output terminal 100 . The second main transistor Mb may further include a body diode Db including an anode coupled the first terminal of the second main transistor Mb and a cathode coupled the second terminal of the second main transistor Mb.

The first auxiliary transistor M 1 includes a control terminal, a first terminal configured to receive the first voltage V 1 , a second terminal coupled to the output terminal 100 , and a bulk terminal coupled to the output terminal 100 . The first auxiliary transistor M 1 may further include a body diode D 1 including an anode coupled the first terminal of the first auxiliary transistor M 1 and a cathode coupled the second terminal of the first auxiliary transistor M 1 . The second auxiliary transistor M 2 includes a control terminal coupled to the control terminal of the first auxiliary transistor M 1 , a first terminal configured to receive the second voltage V 2 , a second terminal coupled to the output terminal 100 , and a bulk terminal coupled to the output terminal 100 . The second auxiliary transistor M 2 may further include a body diode D 2 including an anode coupled the first terminal of the second auxiliary transistor M 2 and a cathode coupled the second terminal of the second auxiliary transistor M 2 . The third auxiliary transistor M 3 includes a control terminal configured to receive the second voltage V 2 , a first terminal configured to receive the first voltage V 1 , a second terminal coupled to the control terminal of the first auxiliary transistor M 1 , a bulk terminal coupled to the control terminal of the first auxiliary transistor M 1 . The third auxiliary transistor M 3 may further include a body diode D 3 including an anode coupled the first terminal of the third auxiliary transistor M 3 and a cathode coupled the second terminal of the third auxiliary transistor M 3 . The fourth auxiliary transistor M 4 includes a control terminal configured to receive the first voltage V 1 , a first terminal configured to receive the second voltage V 2 , a second terminal coupled to the control terminal of the first auxiliary transistor M 1 , a bulk terminal coupled to the control terminal of the first auxiliary transistor M 1 . The fourth auxiliary transistor M 4 may further include a body diode D 4 including an anode coupled the first terminal of the fourth auxiliary transistor M 4 and a cathode coupled the second terminal of the fourth auxiliary transistor M 4 .

The auxiliary selection circuit 12 may further include an auxiliary current load 14 coupled to the control terminal of the first auxiliary transistor M 1 . The auxiliary current load 14 may draw an auxiliary load current from the control terminal of the first auxiliary transistor M 1 to pull down a control voltage VS 2 at the control terminal of the first auxiliary transistor M 1 . The control voltage VS 2 will be described in more detail later. In some other embodiments, the auxiliary current load 14 shown in FIG. 1 may be replaced by the diode connected PMOS/NMOS. For example, the auxiliary current load 14 can be replaced by a PMOS transistor having a source terminal connected to the control terminal of the first auxiliary transistor M 1 , and a control terminal and a drain terminal connected to a ground terminal.

The first main transistor Ma, the second main transistor Mb, the first auxiliary transistor M 1 , the second auxiliary transistor M 2 , the third auxiliary transistor M 3 , and the fourth auxiliary transistor M 4 may be P-type metal oxide semiconductor field-effect transistors (MOSFET), so as to generate the output voltage VS without being affected by the threshold voltages thereof. Further, the first main transistor Ma, the second main transistor Mb, the first auxiliary transistor M 1 , the second auxiliary transistor M 2 , the third auxiliary transistor M 3 , and the fourth auxiliary transistor M 4 may be matched transistors, having equal transistor sizes and equal threshold voltages.

FIG. 2 shows a schematic diagram of the selection circuit 1 for the first voltage V 1 equal to the second voltage V 2 . If the first voltage V 1 and the second voltage V 2 are equal, the first main transistor Ma, the second main transistor Mb, the third auxiliary transistor M 3 and the fourth auxiliary transistor M 4 will be turned off, and the body diodes Da, Db, D 1 , D 2 , D 3 and D 4 will be forward biased. The body diodes D 1 , D 2 , Da and Db may set the output voltage VS to be (V 1 -Vth) (=V 2 -Vth), where Vth is the threshold voltage of the body diodes D 1 , D 2 , Da and Db. Similarly, the body diodes D 3 and D 4 may set the control voltage VS 2 to be (V 1 -Vth) (=V 2 -Vth), where Vth is the threshold voltage of the body diodes D 3 and D 4 . Since the control voltage VS 2 is less than the first voltage V 1 by the threshold voltage Vth, the first auxiliary transistor M 1 and the second auxiliary transistor M 2 may be slightly turned on by the control voltage VS 2 , so as to pull the output voltage VS from (V 1 -Vth) toward V 1 . In one example, both the first voltage V 1 and the second voltage V 2 may be 2.5V, and the threshold voltage may be 0.6, resulting in the control voltage VS 2 of 1.9V, and pulling the output voltage VS to 2.495V, close to the first voltage V 1 and the second voltage V 2 .

FIG. 3 shows a schematic diagram of the selection circuit 1 for the first voltage V 1 greater than the second voltage V 2 . The first voltage V 1 and the second voltage V 2 may be referred to as being close to each other if a difference between the first voltage V 1 and the second voltage V 2 is less than the threshold voltage Vth of the first main transistor Ma or the second main transistor Mb. If the first voltage V 1 is greater than the second voltage V 2 , the first main transistor Ma and the third auxiliary transistor M 3 will be turned on, the second main transistor Mb and the fourth auxiliary transistor M 4 will be turned off, and the body diodes Da, Db, D 1 , D 2 , D 3 and D 4 will be turned off, setting the output voltage VS and the control voltage VS 2 to be the first voltage V 1 . Since control voltage VS 2 is equal to the first voltage V 1 , the first auxiliary transistor M 1 and the second auxiliary transistor M 2 may be turned off by the control voltage VS 2 , blocking current paths via the first auxiliary transistor M 1 and the second auxiliary transistor M 2 . That is, the auxiliary selection circuit 12 may not affect the output voltage VS when the first voltage V 1 is greater than the second voltage V 2 . For example, the first voltage V 1 may be 6V, the second voltage V 2 may be 2.5V, and the threshold voltage may be 0.6, resulting in the output voltage VS of 6V and the control voltage VS 2 of 6V (=V 1 ), turning off the first auxiliary transistor M 1 and the second auxiliary transistor M 2 .

FIG. 4 shows a schematic diagram of the selection circuit 1 for the first voltage V 1 less than the second voltage V 2 . If the first voltage V 1 is less than the second voltage V 2 , the second main transistor Mb and the fourth auxiliary transistor M 4 will be turned on, the first main transistor Ma and the third auxiliary transistor M 3 will be turned off, and the body diodes Da, Db, D 1 , D 2 , D 3 and D 4 will be turned off, setting the output voltage VS and the control voltage VS 2 to be the second voltage V 2 , respectively. Since control voltage VS 2 is equal to the second voltage V 2 , the first auxiliary transistor M 1 and the second auxiliary transistor M 2 may be turned off by the control voltage VS 2 , blocking current paths via the first auxiliary transistor M 1 and the second auxiliary transistor M 2 . That is, the auxiliary selection circuit 12 may not affect the output voltage VS when the second voltage V 2 is greater than the first voltage V 1 . For example, the first voltage V 1 may be 2.5V, the second voltage V 2 may be 6V, and the threshold voltage may be 0.6, resulting in the output voltage VS of 6V and the control voltage VS 2 of 6V (=V 2 ), turning off the first auxiliary transistor M 1 and the second auxiliary transistor M 2 .

If the first voltage V 1 is close to but not equal to the second voltage V 2 , one of the first main transistor Ma and the second main transistor Mb will be partially turned on and the other one will be turned off, one of the third auxiliary transistor M 3 and the fourth auxiliary transistor M 4 will be partially turned on and the other one will be turned off, and the body diodes Da, Db, D 1 , D 2 , D 3 and D 4 will be forward biased, setting the output voltage VS and the control voltage VS 2 to be less than the higher one of the first voltage V 1 and the second voltage V 2 but greater than at least one of (V 1 -Vth) and (V 2 -Vth). Consequently, the first auxiliary transistor M 1 and the second auxiliary transistor M 2 may be partially turned on, pulling the output voltage VS closer to the higher one of first voltage V 1 and the second voltage V 2 . For example, the first voltage V 1 may be 2.5V, the second voltage V 2 may be 2.4V, and the threshold voltage may be 0.6V, resulting in the control voltage VS 2 of 2V, and pulling the output voltage VS to 2.49V, closer to the first voltage V 1 .

In order to show no preference for the first voltage V 1 or the second voltage V 2 , both the main selection circuit 10 and the auxiliary selection circuit 12 may be arranged in a symmetrical structure. That is, the transistor size of the first main transistor Ma and the transistor size of the second main transistor Mb may be equal, the transistor size of the first auxiliary transistor M 1 and the transistor size of the second auxiliary transistor M 2 may be equal, and the transistor size of the third auxiliary transistor M 3 and the transistor size of the fourth auxiliary transistor M 4 may be equal. The transistor size referred herein may be the channel width-to-length ratio of each transistor, or only the channel length of each transistor. In some embodiments, the transistor sizes of the first auxiliary transistor M 1 and the second auxiliary transistor M 2 may be equal to the transistor sizes of the first main transistor Ma and the second main transistor Mb, enhancing voltage supply capability when the first voltage V 1 is equal or close to the second voltage V 2 . In some embodiments, the transistor sizes of the first auxiliary transistor M 1 and the second auxiliary transistor M 2 may be less than the transistor sizes of the first main transistor Ma and the second main transistor Mb, reducing the circuit size of the selection circuit 1 . In some embodiments, the transistor sizes of the first main transistor Ma, the second main transistor Mb, the first auxiliary transistor M 1 , the second auxiliary transistor M 2 , the third auxiliary transistor M 3 , and the fourth auxiliary transistor M 4 may be equal, enhancing voltage supply capability when the first voltage V 1 is equal or close to the second voltage V 2 . In some embodiments, the transistor sizes of the first auxiliary transistor M 1 , the second auxiliary transistor M 2 , the third auxiliary transistor M 3 and fourth auxiliary transistor M 4 may be less than the transistor sizes of the first main transistor Ma and the second main transistor Mb, reducing the circuit size of the selection circuit 1 . In some embodiments, the transistor sizes of the third auxiliary transistor M 3 and the fourth auxiliary transistor M 4 may be less than the transistor sizes of the first auxiliary transistor M 1 and the second auxiliary transistor M 2 , further reducing the circuit size of the selection circuit 1 . The size of the auxiliary current load 14 may match the transistor sizes of the transistor sizes of the third auxiliary transistor M 3 and the fourth auxiliary transistor M 4 .

The selection circuit 1 employs the auxiliary selection circuit 12 to pull the output voltage VS closer to the first voltage V 1 and the second voltage V 2 as the first voltage V 1 and the second voltage V 2 are close or equal to each other, preventing the output terminal 100 from being floating, enhancing voltage supply and enhancing performance of the high-voltage applications without utilizing additional control signals and without increasing circuit complexity and circuit area.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.