Data Recovery Method for Flash Memory

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Section 371 National Stage Application of International Application No. PCT/CN2021/085938 filed on Apr. 8, 2021, entitled “DATA RECOVERY METHOD FOR FLASH MEMORY”, the content of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a field of a nonvolatile memory of a semiconductor integrated circuit, and in particular, to a data recovery method for a flash memory.

BACKGROUND

A flash memory, especially an NAND flash memory, is a kind of non-volatile memory, which is widely used in storage fields such as a mobile phone, a notebook computer, a cloud storage, etc. A basic function of the flash memory is to save data, and a basic requirement of a storage system is to ensure a consistency between written data and read data. An Error Correcting Code (ECC) may correct an error of the read data, which is an important means to ensure the consistency between the written data and the read data and improve a reliability of the storage system. However, the error correcting code also has a certain error correction range. If the read data has a high original error rate, the high original error rate may exceed an error correction ability of the error correcting code, and the written data may not be recovered correctly.

In a process of data storage, the flash memory may be affected by data retention noise. When data is stored in the flash memory for a period of time, a charge stored in a flash memory storage unit may leak, and a threshold voltage distribution state of the flash memory may shift to a side with a smaller threshold voltage. If a read operation is performed by using a read voltage used in an initial stage of the data storage, a problem that a bit error rate of the read data exceeds the error correction ability of the error correcting code may occur.

SUMMARY

The present disclosure provides a data recovery method for a flash memory, including: reading data from the flash memory by using a preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to the operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform a data recovery.

Optionally, the method further includes: determining whether a current check node error rate is less than a preset threshold; and in response to the current check node error rate being less than the preset threshold, stopping the operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, so as to perform a data recovery with current read data.

Optionally, the method further includes: determining whether a current check node error rate is greater than a previous check node error rate, and in response to the current check node error rate being greater than the previous check node error rate, stopping the operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, so as to perform a data recovery with previous read data.

Optionally, the calculating a check node error rate corresponding to the data includes: calculating the check node error rate according to a formula:

R C = sum ⁢ ( H · D k ) / m

•

• where R C is the check node error rate, H is a parity check matrix, D k is data of a read codeword, and m is the number of check nodes.

Optionally, the calculating a read voltage adjustment step size according to the check node error rate includes: establishing a functional relationship between the check node error rate and a bit error rate and a functional relationship between the bit error rate and the read voltage adjustment step size, based on a threshold voltage distribution state of the flash memory; establishing a functional relationship between the check node error rate and the read voltage adjustment step size according to the functional relationship between the check node error rate and the bit error rate and the functional relationship between the bit error rate and the read voltage adjustment step size; and calculating the read voltage adjustment step size according to the functional relationship between the check node error rate and the read voltage adjustment step size.

Optionally, the establishing a functional relationship between the check node error rate and a bit error rate and a functional relationship between the bit error rate and the read voltage adjustment step size includes: calculating a bit error rate corresponding to the preset read voltage, wherein the calculating a bit error rate corresponding to the preset read voltage includes: calculating the bit error rate according to a formula:

P e = G σ i - 1 ( R V i - μ i - 1 , + ∞ ) + G σ i ( - ∞ , R V i - μ i )

•

• where P e is the bit error rate, i is a serial number of the threshold voltage distribution state, R V i is an i th preset read voltage, μ i is a mean value of an i th threshold voltage distribution state of the flash memory, μ i-1 is a mean value of an (i−1) th threshold voltage distribution state of the flash memory, G σ i-1 is a distribution function of Gaussian distribution corresponding to the threshold voltage distribution state with a mean value of 0 and a variance of σ i-1 , and G σ i is a distribution function of Gaussian distribution with a mean value of 0 and a variance of σ i .

Optionally, the i th preset read voltage and an i th optimal read voltage have a relationship:

R V i - R O i = D R i

•

• where R O i is the i th optimal read voltage, and D R i is a read voltage adjustment step size between the i th preset read voltage and the i th optimal read voltage; and • the i th optimal read voltage is calculated by:

R O i = c i - 1 ⁢ μ i - 1 + c i ⁢ μ i c i - 1 = σ i σ i - 1 + σ i , c i = σ i - 1 σ i - 1 + σ i

•

• where μ i is the mean value of the i th threshold voltage distribution state, σ i is a variance of the i th threshold voltage distribution state, μ i-1 is the mean value of the (i−1) th threshold voltage distribution state, and σ i-1 is a variance of the (i−1) th threshold voltage distribution state.

Optionally, the method further includes: quantizing the functional relationship between the check node error rate and the read voltage adjustment step size into a lookup table, and obtaining the read voltage adjustment step size by looking up the lookup table.

Optionally, the method further includes: establishing a functional relationship between a read voltage adjustment step size that between the i th preset read voltage and the i th optimal read voltage and a read voltage adjustment step size that between a j th preset read voltage and a j th optimal read voltage; and calculating, based on the functional relationship, the read voltage adjustment step size between the j th preset read voltage and the j th optimal read voltage according to the read voltage adjustment step size between the i th preset read voltage and the i th optimal read voltage.

Optionally, the selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory so as to perform a data recovery includes: performing the data recovery on the read data by using an error correcting code.

BRIEF DESCRIPTION OF THE DRAWINGS

Specific embodiments of the present disclosure will be further described in detail with reference to accompanying drawings.

In order to describe embodiments of the present disclosure or the technical solutions in the prior art more clearly, the accompanying drawings required to be used in the descriptions of the embodiments or the prior art will be briefly introduced below. It is obvious that the accompanying drawings in the following descriptions are only some embodiments of the present disclosure, and other accompanying drawings may also be obtained by those skilled in the art without any creative effort.

FIG. 1 schematically shows a flowchart of a data recovery method for a flash memory according to an embodiment of the present disclosure;

FIG. 2 schematically shows a flowchart of a method of calculating a read voltage adjustment step size according to a check node error rate according to an embodiment of the present disclosure;

FIG. 3 schematically shows a diagram of a threshold voltage distribution state of an NAND flash memory according to an embodiment of the present disclosure;

FIG. 4 schematically shows a curve diagram of a linear functional relationship between an i th threshold voltage offset ΔV T i and a j th threshold voltage offset ΔV T j according to an embodiment of the present disclosure;

FIG. 5 schematically shows a diagram of a threshold voltage distribution state of a TLC NAND flash memory according to an embodiment of the present disclosure.

FIG. 6 schematically shows a curve diagram of a functional relationship between a check node error rate and a read voltage adjustment step size according to an embodiment of the present disclosure;

FIG. 7 schematically shows a flowchart of a data recovery method for a flash memory according to another embodiment of the present disclosure;

FIG. 8 schematically shows a flowchart of a data recovery method for a flash memory according to yet another embodiment of the present disclosure;

FIG. 9 schematically shows a curve diagram of a monotonic functional relationship between a check node error rate and a bit error rate according to an embodiment of the present disclosure;

FIG. 10 schematically shows a flowchart of a data recovery method for a flash memory according to yet another embodiment of the present disclosure;

FIG. 11 schematically shows a structural diagram of a data recovery system for a flash memory according to an embodiment of the present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

Exemplary embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. The following embodiments are provided by way of examples, so as to fully convey the spirit of the present disclosure to those skilled in the art to which the present disclosure belongs. Therefore, the present disclosure is not limited to the embodiments disclosed herein.

FIG. 1 schematically shows a flowchart of a data recovery method for a flash memory according to an embodiment of the present disclosure.

As shown in FIG. 1 , the method may include, for example, operations S 101 to S 105 .

In operation S 101 , data is read from the flash memory by using a preset read voltage.

The preset read voltage is generally set as an initial read voltage, that is, an optimal read voltage with data hold time of 0. The read data may refer to data written into an NAND flash memory after an ECC encoding and data read when a storage system performs a read operation.

In operation S 102 , a check node error rate corresponding to the data is calculated.

In operation S 103 , a read voltage adjustment step size is calculated according to the check node error rate.

The read voltage adjustment step size may also be called a decision distance, which refers to a voltage value adjusted each time in a process of adjusting the initial read voltage to the optimal read voltage.

In operation S 104 , the preset read voltage is adjusted according to the read voltage adjustment step size, and data is read from the flash memory by using the adjusted preset read voltage, and the process returns to operation S 102 .

After returning to operation S 102 , the process continues to perform operations S 102 to S 104 , until the check node error rate is minimum.

In operation S 105 , a read voltage corresponding to the minimum check node error rate is selected to read data from the flash memory, so as to perform a data recovery.

In the data recovery method provided by the above-mentioned embodiments, the decision distance is calculated according to the check node error rate of the read data, and the read voltage is adjusted by using the decision distance as the read voltage adjustment step size. Data is read with a new read voltage after the read voltage is adjusted, and a check node error rate of read data of the new read voltage is calculated, and the decision distance is calculated according to the check node error rate. The process is repeated. The read voltage corresponding to the minimum check node error rate is selected as the optimal read voltage, so that the read voltage adjustment step size may be dynamically adjusted, extra read times required to find the optimal read voltage may be reduced, and time required for searching the optimal read voltage in a reread error correction algorithm may be reduced.

According to embodiments of the present disclosure, since the NAND flash memory uses a page as a minimum read unit, a page may contain a plurality of codewords in a practical engineering application. In such embodiments, a mean value of the check node errors rate of the codewords on a page is used as a check node error rate of a page. Specifically, a method of calculating a check node error rate may include, for example:

•

• calculating the check node error rate according to a formula:

R C = sum ( H · D k ) / m

•

• where R C is the check node error rate, H is a parity check matrix, D k is data of a read codeword, which is a part of read page data, and m is the number of check nodes, which is also the total number of rows of H matrix.

FIG. 2 schematically shows a flowchart of a method of calculating a read voltage adjustment step size according to a check node error rate according to an embodiment of the present disclosure.

FIG. 3 schematically shows a diagram of a threshold voltage distribution state of a flash memory according to an embodiment of the present disclosure.

According to embodiments of the present disclosure, as shown in FIG. 2 , the method may include, for example, operations S 201 to S 203 . In operation S 201 , a functional relationship between the check node error rate and a bit error rate and a functional relationship between the bit error rate and the read voltage adjustment step size are established based on a threshold voltage distribution state of the flash memory.

In general, a bit error rate of the NAND flash memory is related to the read voltage, as shown in FIG. 3 . R V i is an i th initial read voltage, which is generally the optimal read voltage with data hold time of 0, R O i is an i th optimal read voltage, which is the read voltage with the minimum bit error rate of the read data and is also an intersection point of two threshold voltage distribution states after a period of data hold time, P i is an i th threshold voltage distribution state, P i-1 is an (i−1) th threshold voltage distribution state, ΔV T is a threshold voltage offset of the i th threshold voltage distribution state, ΔV T i-1 is a threshold voltage offset of the (i−1) th threshold voltage distribution state, and D R i is a read voltage adjustment step size between the i th preset read voltage and the i th optimal read voltage. A dotted-line portion may represent an initial threshold voltage distribution state of the flash memory. When data is stored in the flash memory for a period of time, a charge stored in the storage unit of the flash memory may leak, and the threshold voltage distribution state of the flash memory may shift to a side with a smaller threshold voltage, that is, the threshold voltage distribution state of the flash memory may move to a threshold voltage distribution state represented by a solid-line portion. An area of a shaded portion in FIG. 3 is the bit error rate of the read data of the NAND flash memory, and the area of the shaded portion may be solved by integrating the threshold voltage distribution state. Therefore, the bit error rate between two threshold voltage distribution states is also called a bit error rate at an i th read voltage.

In a process of establishing the functional relationship, it is required to calculate a bit error rate corresponding to the preset read voltage. Referring to FIG. 3 , a method of calculating the bit error rate corresponding to the preset read voltage may include:

•

• calculating the bit error rate according to a formula:

P e = G σ i - 1 ( R V i - μ i - 1 , + ∞ ) + G σ i ( - ∞ , R V i - μ i )

•

• where P e is the bit error rate, i is a serial number of the threshold voltage distribution state, R V i is an i th preset read voltage, μ i is a mean value of an i th threshold voltage distribution state of the flash memory, μ i-1 is a mean value of an (i−1) th threshold voltage distribution state of the flash memory, G σ i-1 is a distribution function of Gaussian distribution corresponding to the threshold voltage distribution state with a mean value of 0 and a variance of σ i-1 , and G σ i is a distribution function of Gaussian distribution with a mean value of 0 and a variance of σ i .

The i th preset read voltage and an i th optimal read voltage have a relationship:

R V i - R O i = D R i

•

• where R O i is the i th optimal read voltage, and D R i is a read voltage adjustment step size between the i th preset read voltage and the i th optimal read voltage; and • the i th optimal read voltage is calculated by:

R O i = c i - 1 ⁢ μ i - 1 + c i ⁢ μ i c i - 1 = σ i σ i - 1 + σ i , c i = σ i - 1 σ i - 1 + σ i

•

• wherein, μ i is the mean value of the i th threshold voltage distribution state, σ i is a variance of the i th threshold voltage distribution state, μ i-1 is the mean value of the (i−1) th threshold voltage distribution state, and σ i-1 is a variance of the (i−1) th threshold voltage distribution state.

Specifically, a derivation process of the computational formula of the i th optimal read voltage includes:

•

• modeling the threshold voltage distribution state shown in FIG. 3 as the Gaussian distribution, where an intersection point of two Gaussian distributions is the i th optimal read voltage, which may be represented by:

1 σ i - 1 ⁢ exp ⁡ ( - ( R O i - μ i - 1 ) 2 2 ⁢ σ i - 1 2 ) = 1 σ i ⁢ exp ⁡ ( - ( R O i - μ i ) 2 2 ⁢ σ i 2 )

To solve the above-mentioned equation, when:

σ i - 1 ≠ σ i ,

•

• it may obtain:

R O i = μ i · σ i - 1 2 - μ i - 1 · σ i 2 - σ i - 1 · σ i · s σ i - 1 2 - σ i 2 s = 2 ⁢ σ i 2 ⁢ ln ⁢ σ i - 1 σ i - 2 ⁢ σ i - 1 2 ⁢ ln ⁢ σ i - 1 σ i + ( μ i - μ i - 1 ) 2

However, in an actual NAND flash memory, due to:

σ i - 1 ≈ σ i

•

• such embodiments may be simplified by using the following formula:

Therefore, a representation method of the i th optimal read voltage may be represented as:

s ≈ ( μ i - μ i - 1 ) 2 = μ i - μ i - 1 , μ i > μ i - 1.

Further, the functional relationship between the check node error rate and the bit error rate is established:

R O i = c i - 1 ⁢ μ i - 1 + c i ⁢ μ i c i - 1 = σ i σ i - 1 + σ i , c i = σ i - 1 σ i - 1 + σ i .

In a check matrix H of LDPC, bit with 1 in an i th row in H constitutes an i th parity check equation, and is also an i th check node in a Tanner graph. A probability R Ci of an error in the i th check equation may be calculated by:

R C i = 1 2 - 1 2 ⁢ ∏ i = 0 d i - 1 ( 1 - 2 · Pe ) .

In the formula, P e is a probability of an error in a single bit in an ECC codeword and is also an original error rate of the read data, and d i is the number of 1s in the i th row of the H matrix.

H is set to a matrix with m rows and n columns. Therefore, the number of check equations in ECC constituted by a null space of the H matrix is m (that is, the number of the check nodes in the Tanner graph is m). Then, an average error probability of the m check equations, that is, the check node error rate, may be calculated by:

R C = R C 1 · d 1 + R C 2 · d 2 + , … , + R C m · d m d 1 + d 2 + , … , + d m

For example, if the number of 1s in each row of the H matrix is the same, that is, d 1 =d 2 = . . . =d m =d, the check node error rate may be simplified as:

R C = R C i = 1 2 - 1 2 ⁢ ∏ i = 0 d - 1 ( 1 - 2 · Pe ) .

Based on the above-mentioned calculation, the functional relationship between the check node error rate and the bit error rate may be obtained.

The functional relationship between the bit error rate and the read voltage adjustment step size is established:

In such embodiments, as shown in FIG. 4 , a linear functional relationship is provided between an i th threshold voltage offset ΔV T i and a j th threshold voltage offset ΔV T j , which is shown as follows:

Δ ⁢ V T i = l i , j ( Δ ⁢ V T j )

A linear functional relationship is provided between an i th read voltage adjustment step size (decision distance) D R i and the i th threshold voltage offset ΔV T i , which is shown as follows:

D R i = l D i ( Δ ⁢ V T i )

According to the above-mentioned two linear relationships, the functional relationship between the bit error rate and the read voltage adjustment step size may be calculated as:

Pe = Pe σ i - 1 , σ i ( l D i - 1 ( D R i ) )

Similarly, as shown in FIG. 5 , for a TLC NAND flash memory, the functional relationship between the bit error rate of a Low Page and the read voltage adjustment step size is as follows:

Pe L = Pe σ 0 , σ 1 ( Δ ⁢ V T 1 ) + Pe σ 4 , σ 5 ( Δ ⁢ V T 5 ) = Pe σ 0 , σ 1 ( l 1 , 5 ( Δ ⁢ V T 5 ) ) + Pe σ 4 , σ 5 ( Δ ⁢ V T 5 ) = Pe σ 0 , σ 1 ( l 1 , 5 ( l D 5 - 1 ( D R 5 ) ) ) + Pe σ 4 , σ 5 ( l D 5 - 1 ( D R 5 ) ) .

The functional relationship between the bit error rate of a Middle Page and the read voltage adjustment step size is as follows:

Pe M = Pe σ 1 , σ 2 ( l 2 , 6 ( Δ ⁢ V T 6 ) ) + Pe σ 3 , σ 4 ( l 4 , 6 ( Δ ⁢ V T 6 ) ) + Pe σ 5 , σ 6 ( Δ ⁢ V T 6 ) = Pe σ 1 , σ 2 ( l 2 , 6 ( l D 6 - 1 ( D R 6 ) ) ) + Pe σ 3 , σ 4 ( l 4 , 6 ( l D 6 - 1 ( D R 6 ) ) ) + Pe σ 5 , σ 6 ( l D 6 - 1 ( D R 6 ) ) .

The functional relationship between the bit error rate of an Upper Page and the read voltage adjustment step size is as follows:

Pe U = Pe σ 2 , σ 3 ( l 3 , 7 ( Δ ⁢ V T 7 ) ) + Pe σ 6 , σ 7 ( Δ ⁢ V T 7 ) = Pe σ 2 , σ 3 ( l 3 , 7 ( l D 7 - 1 ( D R 7 ) ) ) + Pe σ 6 , σ 7 ( l D 7 - 1 ( D R 7 ) ) .

In operation S 202 , a functional relationship between the check node error rate and the read voltage adjustment step size is established according to the functional relationship between the check node error rate and the bit error rate and the functional relationship between the bit error rate and the read voltage adjustment step size.

In an embodiment of the present disclosure, the established functional relationship between the check node error rate and the read voltage adjustment step size is shown in FIG. 6 .

In operation S 203 , the read voltage adjustment step size is calculated according to the functional relationship between the check node error rate and the read voltage adjustment step size.

The functional relationship between the check node error rate and the read voltage adjustment step size may be quantized into a lookup table (LUT), and the read voltage adjustment step size may be obtained by looking up the lookup table.

Based on the above-mentioned calculation method of the check node error rate, the bit error rate and the functional relationship, an accuracy of the check node error rate and the bit error rate corresponding to each page of data may be guaranteed, and then a precision of the data recovery may be guaranteed.

According to embodiments of the present disclosure, when the read voltage corresponding to the minimum check node error rate is selected to read the data from the flash memory so as to perform the data recovery, the data recovery is performed on the read data by using an error correcting code.

FIG. 7 schematically shows a flowchart of a data recovery method for a flash memory according to another embodiment of the present disclosure.

As shown in FIG. 7 , the data recovery method provided by such embodiments may further include operations S 701 to S 702 .

In operation S 701 , a functional relationship between a read voltage adjustment step size that between the i th preset read voltage and the i th optimal read voltage and a read voltage adjustment step size that between a j th preset read voltage and a j th optimal read voltage is established.

In operation S 702 , based on the functional relationship, the read voltage adjustment step size between the j th preset read voltage and the j th optimal read voltage is calculated according to the read voltage adjustment step size between the i th preset read voltage and the i th optimal read voltage.

For example, for the TLC NAND flash memory, seven read voltages of the TLC NAND flash memory may be adjusted. Specifically, for a Low Page, D R 1 needs to be calculated based on D R 5 ; for a Middle Page, D R 2 and D R 4 need to be calculated based on D R 6 .

The method may quickly adjust other read voltage adjustment step sizes based on a read voltage adjustment step size.

FIG. 8 schematically shows a flowchart of a data recovery method for a flash memory according to yet another embodiment of the present disclosure.

As shown in FIG. 8 , the data recovery method provided by such embodiments may further include operations S 801 to S 802 .

In operation S 801 , whether a current check node error rate is less than a preset threshold is determined.

If the current check node error rate is less than the preset threshold, operation S 802 is performed.

According to embodiments of the present disclosure, as shown in FIG. 9 , a monotonic functional relationship is provided between the check node error rate and the bit error rate. Therefore, the bit error rate may be replaced with the check node error rate, and a size of the check node error rate may be used to determine whether the read data may be corrected by the ECC. When the check node error rate of the read data is less than a certain value, a read data error may be corrected by the ECC. For example, in a specific example, the check node error rate is less than 0.2338, which may be corrected by an ECC hard decision decoding, and the check node error rate is less than 0.3749, which may be corrected by an ECC soft decision decoding.

In operation S 802 , the operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage is stopped, so as to perform a data recovery with current read data.

The data recovery method for a flash memory according to such embodiments is to add a judgment on whether the read data may be corrected by the ECC on the basis of the above-mentioned method of determining the decision distance according to the check node error rate so as to adjust the read voltage, and to stop the operation of adjusting the read voltage when it is determined that the read data may be corrected by the ECC, which may improve a system performance.

FIG. 10 schematically shows a flowchart of a data recovery method for a flash memory according to yet another embodiment of the present disclosure. As shown in FIG. 10 , the data recovery method provided by such embodiments may further include operations S 1001 to S 1002 .

In operation S 1001 , whether a current check node error rate is greater than a previous check node error rate is determined.

The current check node error rate is greater than the previous check node error rate, which indicates that an error rate of the currently read data is higher than an error rate of a previously read data, and a read voltage of the previously read data is the optimal read voltage. Therefore, when the current check node error rate is greater than the previous check node error rate, operation S 1002 is performed.

In operation S 1002 , the operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading the data from the flash memory by using the adjusted preset read voltage is stopped, so as to perform a data recovery with previous read data.

The data recovery method for a flash memory according to such embodiments is to add a judgment on whether the read data may be corrected by the ECC on the basis of the above-mentioned method of determining the decision distance according to the check node error rate so as to adjust the read voltage, and to stop the operation of adjusting the read voltage when it is determined that the read data may be corrected by the ECC, which may improve the system performance.

FIG. 11 schematically shows a structural diagram of a data recovery system for a flash memory according to an embodiment of the present disclosure.

As shown in FIG. 11 , the system mainly includes:

•

• a check node error rate calculation circuit (Cal_CNER) which is used to calculate a check node error rate corresponding to calculated data; • a lookup table circuit (Fun_CNER) for finding a decision distance according to a check node error rate, which is used to calculate a read voltage adjustment step size according to the check node error rate and a bit error rate; and • a lookup table circuit (Cal_RVDD) for a functional relationship between an i th decision distance and a j th decision distance, which is used to calculate a read voltage adjustment step size between a j th preset read voltage and a j th optimal read voltage according to a read voltage adjustment step size between an i th preset read voltage and an i th optimal read voltage.

Details not covered in the device embodiments will not be repeated here, please refer to the method embodiments.

It should be noted that the check node, also called a check equation, is a parity check equation composed of positions 1 in each row of the check matrix of the ECC. The concept of the check node error rate in embodiments of the present disclosure includes both the concept of the check node error rate itself and the concept of the check equation. If the read voltage is adjusted by using a functional relationship between the check equation and the decision distance, it should be included in the scope of protection of the present disclosure.

Although the present disclosure has been described through specific embodiments with reference to the accompanying drawings, those skilled in the art will easily recognize that the above-mentioned embodiments are only exemplary and used to describe the principles of the present disclosure, which will not limit the scope of the present disclosure. Those skilled in the art may make various combinations, modifications and equivalent substitutions to the above-mentioned embodiments without departing from the spirit and scope of the present disclosure.