Voltage Generation Circuit

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-202823, filed Dec. 14, 2021, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a voltage generation circuit.

BACKGROUND

A semiconductor device may include an element whose characteristic varies depending on a temperature. In order to compensate for a temperature-dependent characteristic of such an element, a voltage generation circuit capable of adjusting the temperature-dependent characteristic is required.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to embodiments.

FIG. 2 is a circuit diagram showing a configuration of a voltage generation circuit according to a first embodiment.

FIG. 3 is a conceptual diagram showing the configuration of the voltage generation circuit according to the first embodiment.

FIG. 4 is a diagram showing electrical characteristics of the voltage generation circuit according to the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a voltage generation circuit according to a second embodiment.

FIG. 6 is a conceptual diagram showing the configuration of the voltage generation circuit according to the second embodiment.

FIG. 7 is a circuit diagram showing a configuration of a voltage generation circuit according to a third embodiment.

FIG. 8 is a conceptual diagram showing the configuration of the voltage generation circuit according to the third embodiment.

FIG. 9 is a circuit diagram showing a configuration of a voltage generation circuit according to a fourth embodiment.

FIG. 10 is a conceptual diagram showing the configuration of the voltage generation circuit according to the fourth embodiment.

FIG. 11 is a circuit diagram showing a configuration of a voltage generation circuit according to a fifth embodiment.

FIG. 12 is a conceptual diagram showing the configuration of the voltage generation circuit according to the fifth embodiment.

FIG. 13 is a circuit diagram showing a configuration of a voltage generation circuit according to a sixth embodiment.

FIG. 14 is a conceptual diagram showing the configuration of the voltage generation circuit according to the sixth embodiment.

FIG. 15 is a circuit diagram showing a configuration of a voltage generation circuit according to a seventh embodiment.

FIG. 16 is a conceptual diagram showing the configuration of the voltage generation circuit according to the seventh embodiment.

FIG. 17 is a conceptual diagram showing the configuration of the voltage generation circuit according to the seventh embodiment.

FIG. 18 is a conceptual diagram showing a configuration of a voltage generation circuit according to an eighth embodiment.

FIG. 19 is a conceptual diagram showing the configuration of the voltage generation circuit according to the eighth embodiment.

DETAILED DESCRIPTION

Embodiments provide a voltage generation circuit in which temperature-dependent characteristics are adjusted.

In general, according to one embodiment, a voltage generation circuit generates a first current indicating a first temperature-dependent characteristic in which a current value thereof changes with a predetermined change in temperature, and a second current indicating a second temperature-dependent characteristic different from the first temperature-dependent characteristic. The voltage generation circuit includes a first variable resistor and a second variable resistor connected in series. The second current flows through the first variable resistor, and a third current having a current value that is based on a difference between a current value of the first current and a current value of the second current, flows through the second variable resistor.

Hereinafter, a voltage generation circuit according to an embodiment will be described in detail with reference to the drawings. In the following description, elements having substantially the same functions and configurations are denoted by the same reference numerals, and the description will be repeated only when necessary. Each embodiment described below exemplifies an apparatus and a method for embodying the technical idea of this embodiment. The technical idea of the embodiments is not limited to the material, shape, structure, arrangement, and the like of the elements described later. The technical idea of the embodiments may be obtained by adding various modifications to the scope of the claims.

The following embodiments may be combined with one another as long as no technical contradiction occurs.

1. First Embodiment

A memory system in which a voltage generation circuit according to the embodiments is implemented will be described with reference to FIG. 1 . The memory system includes, for example, a nonvolatile memory, which is a semiconductor memory device, and a memory controller that controls the nonvolatile memory.

1-1. Configuration of Semiconductor Memory Device

A configuration example of a semiconductor memory device according to the first embodiment will be described with reference to FIG. 1 . As shown in FIG. 1 , a semiconductor memory device 10 includes a memory cell array 21 , an input/output circuit 22 , a ZQ calibration circuit 23 , a logic control circuit 24 , a temperature sensor 25 , a register 26 , a sequencer 27 , a voltage generation circuit 28 , a driver set 29 , a row decoder 30 , a sense amplifier 31 , an input/output pad group 32 , a ZQ calibration pad 33 , and a logic control pad group 34 .

The memory cell array 21 includes a plurality of nonvolatile memory cells associated with word lines and bit lines.

The input/output circuit 22 transmits and receives data signals (DQ<0> to DQ<7>), a data strobe signal (DQS), and an inversion signal (BDQS) thereof to and from the memory controller. The input/output circuit 22 transmits commands and addresses in the data signals to the register 26 . The input/output circuit 22 transmits and receives write data and read data to and from the sense amplifier 31 .

The ZQ calibration circuit 23 calibrates an output impedance of the semiconductor memory device 10 based on a reference resistance via the ZQ calibration pad 33 .

The logic control circuit 24 receives, for example, a chip enable signal (BCE), a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (BWE), a read enable signal (RE), an inversion signal (BRE) of the read enable signal, and a write protect signal (BWP) from the memory controller. The logic control circuit 24 transmits a ready busy signal (BRB) to the memory controller to notify a state of the semiconductor memory device 10 to the outside.

The temperature sensor 25 has a function of measuring a temperature inside the semiconductor memory device 10 . The temperature sensor 25 transmits information on the measured temperature to the sequencer 27 . The temperature sensor 25 is provided at any location inside the semiconductor memory device 10 within a range in which a temperature that can be deemed to be a temperature of the memory cell array 21 can be measured.

The register 26 stores the commands and the addresses. The register 26 transmits the addresses to the row decoder 30 and the sense amplifier 31 , and transmits the commands to the sequencer 27 .

The sequencer 27 receives the commands and controls the entire semiconductor memory device 10 according to a sequence based on the received commands. The sequencer 27 transmits information on the temperature received from the temperature sensor 25 to the memory controller via the input/output circuit 22 .

The voltage generation circuit 28 generates, based on an instruction from the sequencer 27 , a voltage necessary for operations on data such as a write operation, a read operation, and an erase operation. Details will be described later, and the voltage generation circuit 28 generates an appropriate voltage with respect to the temperature measured by the temperature sensor 25 when generating the voltage. The voltage generation circuit 28 supplies the generated voltage to the driver set 29 .

The driver set 29 includes a plurality of drivers, and supplies the voltage from the voltage generation circuit 28 to the row decoder 30 and the sense amplifier 31 based on the addresses from the register 26 . The driver set 29 supplies the voltage to the row decoder 30 based on, for example, a row address in the addresses.

The row decoder 30 receives the row address in the addresses from the register 26 , and selects a row of memory cells based on the row address. The voltage from the driver set 29 is applied to the selected row of memory cells via the row decoder 30 .

At the time of a data read operation, the sense amplifier 31 senses read data read from a memory cell to a bit line, and transmits the sensed read data to the input/output circuit 22 . At the time of a data write operation, the sense amplifier 31 transmits write data written via the bit line to the memory cell. The sense amplifier 31 receives a column address in the addresses from the register 26 , and outputs a column of data based on the column address.

The data signals DQ<0> to DQ<7>, the signal DQS, and the signal BDQS received from the memory controller are transmitted to the input/output circuit 22 via the input/output pad group 32 . The data signals DQ<0> to DQ<7> transmitted from the input/output circuit 22 are transmitted to the outside of the semiconductor memory device 5 via the input/output pad group 32 .

One end of the ZQ calibration pad 33 is connected to the reference resistance, and the other end thereof is connected to the ZQ calibration circuit 23 .

The signals BCE, CLE, ALE, BWE, RE, BRE, and BWP received from the memory controller are transmitted to the logic control circuit 24 via the logic control pad group 34 . The signal BRB transmitted from the logic control circuit 24 is transmitted to the memory controller via the logic control pad group 34 .

1-2. Configuration of Voltage Generation Circuit

FIG. 2 is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. In the following description, a voltage having a temperature-dependent characteristic in which the voltage increases with an increase in temperature is referred to as a “voltage V PTAT ”. A voltage having a temperature-dependent characteristic in which the voltage does not change with a change in temperature is referred to as a “voltage V FLAT ”. A voltage having a temperature-dependent characteristic in which the voltage decreases with an increase in temperature is referred to as a “voltage V CTAT ”.

A current that is generated based on the voltage V PTAT and that has a temperature-dependent characteristic in which a current value thereof increases with an increase in temperature is referred to as a “current I PTAT ”. A current that is generated based on the voltage V FLAT and that has a temperature-dependent characteristic in which a current value thereof does not change with a change in temperature is referred to as a “current I FLAT ”. A current that is generated based on the voltage V CTAT and that has a temperature-dependent characteristic in which a current value thereof decreases with an increase in temperature is referred to as a “current I CTAT ”.

In the following description, a current supplied to a circuit (e.g., a current input to an input terminal provided in the circuit) may be the current I PTAT or the current I CTAT . Thus, when it is not necessary to particularly distinguish the current I PTAT from the current I CTAT , the current may be referred to as a “current I P/C ”.

The voltage generation circuit 28 includes a first current generation circuit G 1 , a second current generation circuit G 2 , a plurality of current mirror circuits, a first variable resistor R 3 , a second variable resistor R 4 , an output terminal V OUT , a first power supply line VDD, and a second power supply line VSS. The first current generation circuit G 1 , the second current generation circuit G 2 , and the plurality of current mirror circuits are provided between the first power supply line VDD and the second power supply line VSS.

A high voltage (which may be referred to as a first power supply voltage) is supplied to the first power supply line VDD. A low voltage (which may be referred to as a second power supply voltage) is supplied to the second power supply line VSS. In the following embodiments, the second power supply line VSS is shown as a ground potential, but any fixed voltage may be supplied.

When the voltage V FLAT is input to an input terminal of the first current generation circuit G 1 , the first current generation circuit G 1 generates the current I FLAT . A voltage value of the voltage input to the input terminal of the first current generation circuit G 1 is V 1 . A resistance value of a resistance element of the first current generation circuit G 1 is R 1 .

When the voltage V PTAT or the voltage V CTAT is input to an input terminal of the second current generation circuit G 2 , the second current generation circuit G 2 generates the current I PTAT or the current I CTAT (the current I P/C ). A voltage value of the voltage input to the input terminal of the second current generation circuit G 2 is V 2 . A resistance value of a resistance element of the second current generation circuit G 2 is R 2 .

The configurations of the first current generation circuit G 1 and the second current generation circuit G 2 are merely examples, and are not limited to the configurations shown in FIG. 2 . The first current generation circuit G 1 may be any circuit as long as the circuit can provide a current (the current I FLAT ) having a temperature-dependent characteristic in which a current value thereof does not change with a change in temperature, and may be replaced with another circuit. The second current generation circuit G 2 may be any circuit as long as the circuit can provide a current (the current I P/C ) having a temperature-dependent characteristic in which a current value thereof changes with a change in temperature, and may be replaced with another circuit.

In other words, the voltage generation circuit 28 generates the current I PTAT or the current I CTAT having a temperature-dependent characteristic (which is referred to below as a first temperature-dependent characteristic) in which a current value thereof changes with a predetermined change in temperature, and the current I FLAT having a temperature-dependent characteristic (which is referred to below as a second temperature-dependent characteristic) different from the first temperature-dependent characteristic. The first temperature-dependent characteristic is a temperature-dependent characteristic in which the current value increases (the current I PTAT ) or decreases (the current I CTAT ) with an increase in temperature. The second temperature-dependent characteristic is a temperature-dependent characteristic in which the current value does not change (the current I FLAT ) with a change in temperature. The current I FLAT may have a temperature-dependent characteristic in which the current does not change at all with a change in temperature, and may have a temperature-dependent characteristic in which a change thereof is negligibly small as compared with those of the current I PTAT and the current I CTAT .

Each current mirror circuit includes a pair of transistors to which respective gate terminals are connected. The plurality of current mirror circuits shown in FIG. 2 include transistors T 1 to T 10 . Sizes of the transistors are the same. The transistor T 7 is denoted by “×2” to indicate that two transistors are connected in parallel. The transistors T 1 to T 3 , T 5 , T 7 , and T 9 are p-type transistors. The transistors T 4 , T 6 , T 8 , and T 10 are n-type transistors.

The first current generation circuit G 1 and the transistor T 1 are connected in series between the first power supply line VDD and the second power supply line VSS. The second current generation circuit G 2 and the transistor T 2 are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T 3 and T 4 are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T 5 and T 6 are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T 7 and T 8 are connected in series between the first power supply line VDD and the second power supply line VSS. The transistor T 9 , the second variable resistor R 4 , and the first variable resistor R 3 are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T 9 and T 10 are connected in series between the first power supply line VDD and the second power supply line VSS.

A node between the first variable resistor R 3 and the second variable resistor R 4 is referred to as a first node N 1 . A node between the transistor T 9 and the second variable resistor R 4 is referred to as a second node N 2 . The first variable resistor R 3 and the second variable resistor R 4 connected in series with each other and the transistor T 10 are connected in parallel between the second node N 2 (or the output terminal V OUT ) and the second power supply line VSS.

A pair of transistors T 1 and T 5 and a pair of transistors T 1 and T 7 each form a current mirror circuit. When a current generated by the first current generation circuit G 1 and flowing through the transistor T 1 is the current I FLAT , a current flowing through the transistor T 5 is also the current I FLAT . When a current flowing through the transistor T 1 is the current I FLAT , a current flowing through the transistor T 7 is a current (2×I FLAT ) that is twice the current I FLAT .

In the present embodiment, the current flowing through the transistor T 7 is a current that is twice the current I FLAT , but the present disclosure is not limited to this configuration. For example, the current flowing through the transistor T 7 may be a current (n×I FLAT ) that is n times the current I FLAT (n is a positive number excluding 1).

A value of n is not limited to an integer and may include a decimal. In the present embodiment, since the number of transistors T 7 is twice the number of transistors T 1 , the current flowing through the transistor T 7 is a current that is twice the current I FLAT . By adjusting a ratio of the number of transistors T 7 to the number of transistors T 1 , the value of n can include a decimal. For example, when two transistors are connected in parallel as the transistor T 1 and five transistors are connected in parallel as the transistor T 7 , n is 2.5, and the current flowing through the transistor T 7 is a current (2.5×I FLAT ) that is 2.5 times the current I FLAT .

A pair of transistors T 2 and T 3 and a pair of transistors T 2 and T 9 each form a current mirror circuit. When a current generated by the second current generation circuit G 2 and flowing through the transistor T 2 is the current I P/C , currents respectively flowing through the transistors T 3 and T 9 are also the current I P/C .

When a current flowing through the transistor T 3 is the current I P/C , a current flowing through the transistor T 4 connected in series with the transistor T 3 is also the current I P/C . A pair of transistors T 4 and T 8 form a current mirror circuit. When the current flowing through the transistor T 4 is the current I P/C , a current flowing through the transistor T 8 is also the current I P/C .

When a current flowing through the transistor T 5 is the current I FLAT , a current flowing through the transistor T 6 connected in series with the transistor T 5 is also the current I FLAT . A pair of transistors T 6 and T 10 form a current mirror circuit. When the current flowing through the transistor T 6 is the current I FLAT , a current flowing through the transistor T 10 is also the current I FLAT .

FIG. 3 is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. In FIG. 3 , only the first variable resistor R 3 , the second variable resistor R 4 , and the output terminal V OUT among circuit elements shown in FIG. 2 are shown, and other circuit elements are shown as input terminals and output terminals in the circuit shown in FIG. 3 .

The transistor T 7 in FIG. 2 corresponds to an input terminal V IN7 in FIG. 3 , the transistor T 8 in FIG. 2 corresponds to an output terminal V OUT8 in FIG. 3 , the transistor T 9 in FIG. 2 corresponds to an input terminal V IN9 in FIG. 3 , and the transistor T 10 in FIG. 2 corresponds to an output terminal V OUT10 in FIG. 3 . The current 2×I FLAT is input from the input terminal V IN7 , the current I P/C is input from the input terminal V IN9 , the current I P/C is output to the output terminal V OUT8 , and the current I FLAT is output to the output terminal V OUT10 .

As shown in FIG. 3 , the first node N 1 is a node between the first variable resistor R 3 , the second variable resistor R 4 , the input terminal V IN7 , and the output terminal V OUT8 . The second node N 2 is a node between the second variable resistor R 4 , the input terminal V IN9 , the output terminal V OUT , and the output terminal V OUT10 . Referring to FIG. 2 , since the second node N 2 is connected to the first power supply line VDD via the transistor T 9 , it can be said that the second node N 2 is a node between the second variable resistor R 4 , the output terminal V OUT , and the first power supply line VDD.

The voltage generation circuit 28 includes a first path PAS 1 , a second path PAS 2 , and a third path PAS 3 . The first path PAS 1 is a path from the input terminal V IN7 (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4 . The second path PAS 2 is a path from the second node N 2 to the output terminal V OUT10 (or the second power supply line VSS) without passing through the second variable resistor R 4 . The third path PAS 3 is a path from the first node N 1 to the output terminal V OUT8 (or the second power supply line VSS) without passing through the first variable resistor R 3 . A current flowing through the first path PAS 1 is 2×I FLAT , a current flowing through the second path PAS 2 is the current I FLAT , and a current flowing through the third path PAS 3 is the current I P/C .

1-3. Output of Voltage Generation Circuit

As described above, since the current flowing through the transistor T 7 (the current input from the input terminal V IN7 ) is “2×I FLAT ”, the current flowing through the transistor T 8 (the current output to the output terminal V OUT8 ) is “I P/C ”, the current flowing through the transistor T 9 (the current input from the input terminal V IN9 ) is “I P/C ”, and the current flowing through the transistor T 10 (the current output to the output terminal V OUT10 ) is “I FLAT ”, a voltage of the output terminal V OUT is calculated as in the following Equation (1-1).

V OUT = R 3 · ( I P / C - I FLAT + 2 · I FLAT - I P / C ) + R 4 · ( I P / C - I FLAT ) = R 3 · I FLAT + R 4 · ( I P / C - I FLAT ) ( 1 - 1 )

Referring to FIG. 2 , “I P/C ” and “I FLAT ” can be expressed by the following Equation (1-2).

I P / C = V 2 R 2 , ( 1 - 2 ) I FLAT = V 1 R 1

By substituting Equation (1-2) into Equation (1-1), V OUT can be expressed as the following Equation (1-3).

V OUT = R 3 R 1 · V 1 + R 4 · ( V 2 R 2 - V 1 R 1 ) ( 1 - 3 )

As shown in Equation (1-1), a current flowing through the first variable resistor R 3 is the current I FLAT , and a current flowing through the second variable resistor R 4 is a current based on a difference between the current I P/C and the current I FLAT . As shown in Equation (1-3), when V 2 /R 2 =V 1 /R 1 (that is, when I P/C =current I FLAT ) at a certain temperature Temp 1 , the term of R 4 is zero.

1-4. Electrical Characteristics of Voltage Generation Circuit

FIG. 4 is a diagram showing electrical characteristics of the voltage generation circuit according to the embodiment. As shown in FIG. 4 , at the temperature Temp 1 (for example, 25° C.), a value of V OUT changes in proportion to a value of the first variable resistor R 3 , and a gradient of the output voltage V OUT with respect to the temperature changes based on V OUT =(R 3 /R 1 )×V 1 by a value of the second variable resistor R 4 . In FIG. 4 , by increasing the value of the second variable resistor R 4 , the gradient of the output voltage V OUT is larger than a slope of “Initial”.

As described above, an absolute value of the output voltage V OUT at the temperature Temp 1 can be adjusted by the value of the first variable resistor R 3 , and a temperature gradient of the output voltage V OUT can be adjusted by the value of the second variable resistor R 4 . Since the values of the first variable resistor R 3 and the second variable resistor R 4 can be independently controlled, the absolute value of the output voltage V OUT and the temperature gradient of the output voltage V OUT can be independently adjusted.

In the present embodiment, the transistor T 7 has a configuration in which two transistors are connected in parallel, but the present disclosure is not limited to this configuration. For example, the number of transistors connected in parallel may be three or more. Alternatively, an L length of the transistor T 7 (a distance between a source and a drain) and an L length of the transistor T 1 are the same, and a W length (a width in a direction orthogonal to an L length direction) of the transistor T 7 may be n times a W length of the transistor T 1 . In the present embodiment, since n=2, a coefficient of “R 3 ·I FLAT ” in Equation (1-1) is 1, when the value of n is changed, only the coefficient changes, and the above-mentioned effect can be obtained.

In the present embodiment, the current I FLAT generated by the first current generation circuit G 1 does not change with a change in temperature, but the first current generation circuit G 1 may generate a current varying as the change in temperature, such as the current I P/C . However, in this case, a temperature-dependent characteristic of a current generated by the first current generation circuit G 1 is different from a temperature-dependent characteristic of the current I P/C generated by the second current generation circuit G 2 . In such a case as well, since I FLAT is replaced with I P/C ′ in Equation (1-1), the above-mentioned effect can be obtained.

2. Second Embodiment

A voltage generation circuit according to a second embodiment will be described with reference to FIGS. 5 and 6 . A voltage generation circuit 28 A according to the second embodiment is similar to the voltage generation circuit 28 according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit 28 according to the first embodiment will be omitted, and differences from the voltage generation circuit 28 will be mainly described.

2-1. Configuration of Voltage Generation Circuit

FIG. 5 is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown in FIG. 5 , in the voltage generation circuit 28 A, transistors T 11 to T 13 are provided instead of the transistors T 5 to T 10 that are provided in the voltage generation circuit 28 shown in FIG. 2 . The transistors T 11 and T 12 are p-type transistors. The transistor T 13 is an n-type transistor.

The transistor T 11 is provided between the first power supply line VDD and the first node N 1 . The transistor T 12 , the second variable resistor R 4 , and the first variable resistor R 3 are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T 12 and T 13 are connected in series between the first power supply line VDD and the second power supply line VSS. The first variable resistor R 3 and the second variable resistor R 4 connected in series with each other and the transistor T 13 are connected in parallel between the second node N 2 (or the output terminal V OUT ) and the second power supply line VSS.

A pair of transistors T 1 and T 12 , a pair of transistors T 2 and T 11 , and a pair of transistors 14 and T 13 each form a current mirror circuit. In this configuration, a current flowing through the transistor T 11 is the current I P/C , a current flowing through the transistor T 12 is the current I FLAT , and a current flowing through the transistor T 13 is the current I P/C .

FIG. 6 is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. The transistor T 11 in FIG. 5 corresponds to an input terminal V IN11 in FIG. 6 , the transistor T 12 in FIG. 5 corresponds to an input terminal V IN12 in FIG. 6 , and the transistor T 13 in FIG. 5 corresponds to an output terminal V OUT13 in FIG. 6 . The current I P/C is input from the input terminal V IN11 , the current I FLAT is input from the input terminal V IN12 , and the current I P/C is output to the output terminal V OUT13 .

As shown in FIG. 6 , the first node N 1 is a node between the first variable resistor R 3 , the second variable resistor R 4 , and the input terminal V IN11 . The second node N 2 is a node between the second variable resistor R 4 , the input terminal V IN12 , the output terminal V OUT , and the output terminal V OUT13 . Referring to FIG. 5 , since the second node N 2 is connected to the first power supply line VDD via the transistor T 12 , it can be said that the second node N 2 is a node between the second variable resistor R 4 , the output terminal V OUT , and the first power supply line VDD.

The voltage generation circuit 28 A includes the first path PAS 1 and the second path PAS 2 . The first path PAS 1 is a path from the input terminal V IN11 (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4 . The second path PAS 2 is a path from the second node N 2 to the output terminal V OUT13 (or the second power supply line VSS) without passing through the second variable resistor R 4 . A current flowing through each of the first path PAS 1 and the second path PAS 2 is the current I P/C .

2-2. Output of Voltage Generation Circuit

As described above, since a current flowing through the transistor T 11 (a current input from the input terminal V IN11 ) is “I P/C ”, a current flowing through the transistor T 12 (a current input from the input terminal V IN12 ) is “I FLAT ”, and a current flowing through the transistor T 13 (a current output to the output terminal V OUT13 ) is “I P/C ”, a voltage of the output terminal V OUT is calculated as in the following Equation (2-1).

V OUT = R 3 · ( I FLAT - I P / C + I P / C ) + R 4 · ( I FLAT - I P / C ) = R 3 · I FLAT + R 4 · ( I FLAT - I P / C ) ( 2 - 1 )

As described above, “I P/C ” and “I FLAT ” can be expressed as in the Equation (1-2) described above.

By substituting Equation (1-2) into Equation (2-1), V OUT can be expressed as in the following Equation (2-2).

V OUT = R 3 R 1 · V 1 + R 4 · ( V 1 R 1 - V 2 R 2 ) ( 2 - 2 )

As shown in Equation (2-1), a current flowing through the first variable resistor R 3 is the current I FLAT , and a current flowing through the second variable resistor R 4 is a current based on a difference between the current I P/C and the current I FLAT . As shown in Equation (2-2), when V 2 /R 2 =V 1 /R 1 is satisfied at a certain temperature Temp 1 (that is, when I P/C =current I FLAT ), the term of R 4 is zero.

Therefore, as in the voltage generation circuit 28 according to the first embodiment, the voltage generation circuit 28 A according to the present embodiment can adjust an absolute value of the output voltage V OUT at a certain temperature by a value of the first variable resistor R 3 , and can adjust a temperature gradient of the output voltage V OUT by a value of the second variable resistor R 4 . Since the values of the first variable resistor R 3 and the second variable resistor R 4 can be independently controlled, the absolute value of the output voltage V OUT and the temperature gradient of the output voltage V OUT can be independently adjusted.

3. Third Embodiment

A voltage generation circuit according to a third embodiment will be described with reference to FIGS. 7 and 8 . A voltage generation circuit 28 B according to the third embodiment is similar to the voltage generation circuit 28 according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit 28 according to the first embodiment will be omitted, and differences from the voltage generation circuit 28 will be mainly described.

3-1. Configuration of Voltage Generation Circuit

FIG. 7 is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown in FIG. 7 , in the voltage generation circuit 28 B, a second current generation circuit G 2 provided in the voltage generation circuit 28 shown in FIG. 2 is divided into a positive characteristic second current generation circuit G 2 p and a negative characteristic second current generation circuit G 2 c . Similarly, the transistor T 2 in FIG. 2 is divided into transistors T 2 p and T 2 c . Also, in this configuration, the transistor T 3 in FIG. 2 is divided into transistors T 3 p and T 3 c . Similarly, the transistor T 9 in FIG. 2 is divided into transistors T 9 p and T 9 c.

When the voltage V PTAT is input to an input terminal of the positive characteristic second current generation circuit G 2 p , the positive characteristic second current generation circuit G 2 p generates the current I PTAT . A resistance value of a resistance element of the positive characteristic second current generation circuit G 2 p is R 2p . When the voltage V CTAT is input to an input terminal of the negative characteristic second current generation circuit G 2 c , the negative characteristic second current generation circuit G 2 c generates the current I CTAT . A resistance value of a resistance element of the negative characteristic second current generation circuit G 2 c is R 2c .

The transistors T 2 p , T 2 c , T 3 p , T 3 c , T 9 p , and T 9 c are all p-type transistors.

A pair of transistors T 2 p and T 3 p and a pair of transistors T 2 p and T 9 p each form a current mirror circuit. When a current generated by the positive characteristic second current generation circuit G 2 p and flowing through the transistor T 2 p is the current I PTAT , currents flowing through the transistors T 3 p and T 9 p are also the current I PTAT .

A pair of transistors T 2 c and T 3 c and a pair of transistors T 2 c and T 9 c each form a current mirror circuit. When a current generated by the negative characteristic second current generation circuit G 2 c and flowing through the transistor T 2 c is the current I CTAT , currents flowing through the transistors T 3 c and T 9 c are also the current I CTAT .

The transistors T 3 p and T 3 c are connected to the transistor T 4 via a switch SW 3 . The transistor T 4 becomes connected to either the transistor T 3 p or the transistor T 3 c by controlling the switch SW 3 . That is, a state in which the transistor T 3 p and the transistor T 4 are connected in series and a state in which the transistor T 3 c and the transistor T 4 are connected in series are switched by the switch SW 3 .

When the transistor T 3 p is selected by the switch SW 3 , since a current flowing through the transistor T 3 p is the current I PTAT , a current flowing through the transistor T 4 connected in series with the transistor T 3 p is also the current I PTAT . Since the pair of transistors T 4 and T 8 form a current mirror circuit, a current flowing through the transistor T 8 is also the current I PTAT .

When the transistor T 3 c is selected by the switch SW 3 , since a current flowing through the transistor T 3 c is the current I CTAT , a current flowing through the transistor T 4 connected in series with the transistor T 3 c is also the current I CTAT . Since the pair of transistors T 4 and T 8 form a current mirror circuit, the current flowing through the transistor T 8 is also the current I CTAT .

As described above, the current flowing through the transistor T 8 is controlled to be the current I PTAT or the current I CTAT by the switch SW 3 .

The transistors T 9 p and T 9 c are connected to the second variable resistor R 4 via a switch SW 9 . The second variable resistor R 4 becomes connected to either the transistor T 9 p or the transistor T 9 c by controlling the switch SW 9 . That is, a state in which the transistor T 9 p , the second variable resistor R 4 , and the first variable resistor R 3 are connected in series and a state in which the transistor T 9 c , the second variable resistor R 4 , and the first variable resistor R 3 are connected in series are switched by the switch SW 9 .

The switch SW 3 and the switch SW 9 are interlocked with each other. The switches are controlled such that when the switch SW 3 selects the transistor T 3 p , the switch SW 9 selects the transistor T 9 p . The switches are controlled such that when the switch SW 3 selects the transistor T 3 c , the switch SW 9 selects the transistor T 9 c.

FIG. 8 is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. In FIG. 8 , only the first variable resistor R 3 , the second variable resistor R 4 , and the output terminal V OUT among circuit elements shown in FIG. 7 are shown, and other circuit elements are shown as input terminals and output terminals in the circuit shown in FIG. 8 . The transistor T 7 in FIG. 7 corresponds to the input terminal V IN7 in FIG. 8 , the transistor T 8 in FIG. 7 corresponds to output terminals V OUT8p and V OUT8c in FIG. 8 , the transistors T 9 p and T 9 c in FIG. 7 correspond to input terminals V IN9p and V IN9c in FIG. 8 , and the transistor T 10 in FIG. 7 corresponds to the output terminal V OUT10 in FIG. 8 .

The input terminals V IN9p and V IN9c are switched by the switch SW 9 . Since the switch SW 3 is connected to the transistors T 3 p and T 3 c in FIG. 7 , and the current flowing through the transistor T 8 is controlled by the switching of the switch SW 3 as described above, the output terminals V OUT8p and the V OUT8c are shown to be switched by the switch SW 3 in FIG. 8 .

In the following description, a case in which the switch SW 3 is connected to the output terminal V OUT8p and the switch SW 9 is connected to the input terminal V IN9p is referred to as “during a PTAT operation”. Meanwhile, a case in which the switch SW 3 is connected to the output terminal V OUT8c and the switch SW 9 is connected to the input terminal V IN9c is referred to as “during a CTAT operation”.

As shown in FIG. 8 , the voltage generation circuit 28 B includes the first path PAS 1 , the second path PAS 2 , and the third path PAS 3 . The first path PAS 1 is a path from the input terminal V IN7 (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4 . The second path PAS 2 is a path from the second node N 2 to the output terminal V OUT10 (or the second power supply line VSS) without passing through the second variable resistor R 4 . The third path PAS 3 is a path from the first node N 1 to the output terminal V OUT8p or V OUT8c (or the second power supply line VSS) without passing through the first variable resistor R 3 .

When the switch SW 3 is connected to the output terminal V OUT8p and the switch SW 9 is connected to the input terminal V IN9p , a current 2×I FLAT ( 3 ) is input from the input terminal V IN7 , a current I PTAT ( 1 ) is input from the input terminal V IN9p , a current I PTAT ( 4 ) is output to the output terminal V OUT8p , and a current I FLAT ( 2 ) is output to the output terminal V OUT10 . Although the details will be described later, a current flowing through the first variable resistor R 3 is determined to be a current I FLAT ( 5 ) due to the above input and output.

The numbers described in parentheses attached after the reference numerals indicating the above currents are given to distinguish currents flowing through different paths. Therefore, the same reference numerals before parentheses indicate the same current value. That is, for example, I PTAT ( 1 ) and I PTAT ( 4 ) are currents that flow in different paths, but current values are the same.

When the switch SW 3 is connected to the output terminal V OUT8c and the switch SW 9 is connected to the input terminal V IN9c , the current 2×I FLAT ( 3 ) is input from the input terminal V IN7 , a current I CTAT ( 6 ) is input from the input terminal V IN9c , a current I CTAT ( 7 ) is output to the output terminal V OUT8c , and the current I FLAT ( 2 ) is output to the output terminal V OUT10 . Although the details will be described later, the current flowing through the first variable resistor R 3 is determined to be the current I FLAT ( 5 ) due to the above input and output.

“During the PTAT operation”, a current (I R3 ) flowing through the first variable resistor R 3 and a current (I R4 ) flowing through the second variable resistor R 4 are expressed by the following Equations (3-1) and (3-2), respectively. I R4 =I PTAT (1)− I FLAT (2) (3-1) I R3 =2× I FLAT (3)+( I PTAT (1)− I FLAT (2))− I PTAT (4) (3-2)

“During the CTAT operation”, the current (I R3 ) flowing through the first variable resistor R 3 and the current (I R4 ) flowing through the second variable resistor R 4 are expressed as in the following Equations (3-3) and (3-4), respectively. I R4 =I CTAT (6)− I FLAT (2) (3-3) I R3 =2× I FLAT (3)+( I CTAT (6)− I FLAT (2))− I CTAT (7) (3-4)

In the case of Equation (3-2), the term of I PTAT disappears and only I FLAT remains. In the case of Equation (3-4), the term of I CTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 5 ). That is, the current (I R3 ) flowing through the first variable resistor R 3 is I FLAT ( 5 ) both “during the PTAT operation” and “during the CTAT operation”.

In other words, “during the PTAT operation”, when a current flowing through the second node N 2 is the current I PTAT ( 1 ), a current flowing through the first path PAS 1 is the current 2×I FLAT ( 3 ), a current flowing through the second path PAS 2 is the current I FLAT ( 2 ), and a current flowing through the third path PAS 3 is the current I PTAT ( 4 ).

“During the CTAT operation”, when the current flowing through the second node N 2 is the current I CTAT ( 6 ), the current flowing through the first path PAS 1 is the current 2×I FLAT ( 3 ), the current flowing through the second path PAS 2 is the current I FLAT ( 2 ), and the current flowing through the third path PAS 3 is the current I CTAT ( 7 ). The current flowing through the first path PAS 1 may be a current (n×I FLAT ) that is n times the current I FLAT (n is a positive number excluding 1).

3-2. Output of Voltage Generation Circuit 28 B

A voltage of the output terminal V OUT differs during the PTAT operation and during the CTAT operation. In each case, the voltage of the output terminal V OUT is calculated as follows.

3-2-1. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (3-1) and (3-2), the voltage of the output terminal V OUT is calculated as in the following Equation (3-5). V OUT =R 3 ·I FLAT (5)+ R 4 ·( I PTAT (1)− I FLAT (2)) (3-5)

3-2-2. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (3-3) and (3-4), the voltage of the output terminal V OUT is calculated as in the following Equation (3-6). V OUT =R 3 ·I FLAT (5)+ R 4 ·( I CTAT (6)− I FLAT (2)) (3-6)

As shown in Equations (3-5) and (3-6), the current flowing through the first variable resistor R 3 is the current I FLAT ( 5 ), and a current flowing through the second variable resistor R 4 is a current based on a difference between the current I PTAT ( 1 ) and the current I FLAT ( 2 ) or a current based on a difference between the current I CTAT ( 6 ) and the current I FLAT ( 2 ). As shown in Equation (3-5), when I PTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero. As shown in Equation (3-6), when I CTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero.

Therefore, as in the voltage generation circuit 28 according to the first embodiment, the voltage generation circuit 28 B according to the present embodiment can adjust an absolute value of the output voltage V OUT at a certain temperature by a value of the first variable resistor R 3 , and can adjust a temperature gradient of the output voltage V OUT by a value of the second variable resistor R 4 . Since the values of the first variable resistor R 3 and the second variable resistor R 4 can be independently controlled, the absolute value of the output voltage V OUT and the temperature gradient of the output voltage V OUT can be independently adjusted. Further, by switching the switches SW 3 and SW 9 , it is possible to supply both the output voltage V OUT in which the voltage value increases with an increase in temperature and the output voltage V OUT in which the voltage value decreases with the increase in temperature.

4. Fourth Embodiment

A voltage generation circuit according to a fourth embodiment will be described with reference to FIGS. 9 and 10 . A voltage generation circuit 28 C according to the fourth embodiment is similar to the voltage generation circuit 28 B according to the third embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit 28 B according to the third embodiment will be omitted, and differences from the voltage generation circuit 28 B will be mainly described.

4-1. Configuration of Voltage Generation Circuit

FIG. 9 is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown in FIG. 9 , in the voltage generation circuit 28 C, the transistors T 11 to T 13 are provided instead of the transistors T 5 to T 10 that are provided in the voltage generation circuit 28 B shown in FIG. 7 . Since the transistors T 12 and T 13 in FIG. 9 are the same as the transistors T 12 and T 13 in FIG. 5 , detailed descriptions will be omitted.

Transistors T 11 p and T 11 c are connected to the first node N 1 via a switch SW 11 . A state in which the transistor T 11 p is connected to the first node N 1 and a state in which the transistor T 11 c is connected to the first node N 1 are switched by the switch SW 11 .

The transistors T 11 p , T 11 c , and T 12 are p-type transistors. The transistor T 13 is an n-type transistor.

A pair of transistors T 2 p and T 11 p form a current mirror circuit. Therefore, when a current generated by the positive characteristic second current generation circuit G 2 p and flowing through the transistor T 2 p is the current I PTAT , a current flowing through the transistor T 11 p when the transistor T 11 p is selected by the switch SW 11 is also the current I PTAT .

A pair of transistors T 2 c and T 11 c form a current mirror circuit. Therefore, when a current generated by the negative characteristic second current generation circuit G 2 c and flowing through the transistor T 2 c is the current I CTAT , a current flowing through the transistor T 11 c when the transistor T 11 c is selected by the switch SW 11 is also the current I CTAT .

When the transistor T 3 p is selected by the switch SW 3 , since a current flowing through the transistor T 3 p is the current I PTAT , a current flowing through the transistor T 4 connected in series with the transistor T 3 p is also the current I PTAT . Since a pair of transistors T 4 and T 13 form a current mirror circuit, a current flowing through the transistor T 13 is also the current I PTAT .

When the transistor T 3 c is selected by the switch SW 3 , since a current flowing through the transistor T 3 c is the current I CTAT , a current flowing through the transistor T 4 connected in series with the transistor T 3 c is also the current I CTAT . Since the pair of transistors T 4 and T 13 form a current mirror circuit, the current flowing through the transistor T 13 is also the current I CTAT .

As described above, the current flowing through the transistor T 13 is controlled to be the current I PTAT or the current I CTAT by the switch SW 3 .

The switch SW 3 and the switch SW 11 are interlocked with each other. The switches are controlled such that when the switch SW 3 selects the transistor T 3 p , the switch SW 11 selects the transistor T 11 p . The switches are controlled such that when the switch SW 3 selects the transistor T 3 c , the switch SW 11 selects the transistor T 11 c.

FIG. 10 is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. In FIG. 10 , only the first variable resistor R 3 , the second variable resistor R 4 , and the output terminal V OUT among circuit elements shown in FIG. 9 are shown, and other circuit elements are shown as input terminals and output terminals in the circuit shown in FIG. 10 . The transistors T 11 p and T 11 c in FIG. 9 correspond to input terminals V IN11p and V IN11c in FIG. 10 , the transistor T 12 in FIG. 9 corresponds to the input terminal V IN12 in FIG. 10 , and the transistor T 13 in FIG. 9 corresponds to output terminals V OUT13p and V OUT13c in FIG. 10 .

The input terminals V IN11p and V IN11c are switched by the switch SW 11 . Since the switch SW 3 is connected to the transistors T 3 p and T 3 c in FIG. 9 , and the current flowing through the transistor T 13 is controlled by the switching of the switch SW 3 as described above, the output terminals V OUT13p and V OUT13c are shown to be switched by the switch SW 3 in FIG. 10 .

As shown in FIG. 10 , the voltage generation circuit 28 C includes the first path PAS 1 and the second path PAS 2 . The first path PAS 1 is a path from the input terminal V IN11p or V IN11c (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4 . The second path PAS 2 is a path from the second node N 2 to the output terminal V OUT13p or V OUT13c (or the second power supply line VSS) without passing through the second variable resistor R 4 .

When the switch SW 3 is connected to the output terminal V OUT13p and the switch SW 11 is connected to the input terminal V IN11p , a current I PTAT ( 3 ) is input from the input terminal V IN11p , a current I FLAT ( 1 ) is input from the input terminal V IN12 , a current I PTAT ( 2 ) is output to the output terminal V OUT13p . Although the details will be described later, a current flowing through the first variable resistor R 3 is determined to be a current I FLAT ( 4 ) due to the above input and output.

Meanwhile, when the switch SW 3 is connected to the output terminal V OUT13c and the switch SW 11 is connected to an input terminal V IN11c , a first current I CTAT ( 6 ) is input from the input terminal V IN11C , the current I FLAT ( 1 ) is input from the input terminal V IN12 , and a current I CTAT ( 5 ) is output to the output terminal V OUT13c . Although the details will be described later, a current flowing through the first variable resistor R 3 is determined to be a current I FLAT ( 4 ) due to the above input and output.

When the switch SW 3 is connected to the output terminal V OUT13p and the switch SW 11 is connected to the input terminal V IN11p , a current (I R3 ) flowing through the first variable resistor R 3 and a current (I R4 ) flowing through the second variable resistor R 4 are expressed by the following Equations (4-1) and (4-2), respectively. I R4 =I FLAT (1)− I PTAT (2) (4-1) I R3 =I PTAT (3)+( I FLAT (1)− I PTAT (2)) (4-2)

In this case, since a current of a value based on I FLAT ( 1 )−I PTAT ( 2 ) is output to the output terminal V OUT , the case of performing such an operation is referred to “during a CTAT operation”.

When the switch SW 3 is connected to the output terminal V OUT13c and the switch SW 11 is connected to the input terminal V IN11c , the current (I R3 ) flowing through the first variable resistor R 3 and the current (I R4 ) flowing through the second variable resistor R 4 are expressed as in the following Equations (4-3) and (4-4), respectively. I R4 =I FLAT (1)− I CTAT (5) (4-3) I R3 =I CTAT (6)+( I FLAT (1)− I CTAT (5)) (4-4)

In this case, since a current of a value based on I FLAT ( 1 )−I CTAT ( 5 ) is output to the output terminal V OUT , the case of performing such an operation is referred to as “during a PTAT operation”.

In the case of Equation (4-2), the term of I PTAT disappears and I FLAT remains. In the case of Equation (4-4), the term of I CTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 4 ). That is, the current (I R3 ) flowing through the first variable resistor R 3 is I FLAT ( 4 ) both “during the CTAT operation” and “during the PTAT operation”.

In other words, “during the CTAT operation”, when a current flowing through the first path PAS 1 to the first node N 1 is the current I PTAT ( 3 ), a current supplied to the second node N 2 is the current I FLAT ( 1 ), and a current flowing through the second path PAS 2 is the current I PTAT ( 2 ). “During the PTAT operation”, when the current flowing through the first path PAS 1 to the first node N 1 is the current I CTAT ( 6 ), the current supplied to the second node N 2 is the current I FLAT ( 1 ), and the current flowing through the second path PAS 2 is the current I CTAT ( 5 ).

4-2. Output of Voltage Generation Circuit

A voltage of the output terminal V OUT differs during the CTAT operation and during the PTAT operation. In each case, the voltage of the output terminal V OUT is calculated as follows.

4-2-1. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (4-1) and (4-2), the voltage of the output terminal V OUT is calculated as in the following Equation (4-5). V OUT =R 3 ·I FLAT (4)+ R 4 ·( I FLAT (1)− I PTAT (2)) (4-5) 4-2-2. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (4-3) and (4-4), the voltage of the output terminal V OUT is calculated as in the following Equation (4-6). V OUT =R 3 ·I FLAT (4)+ R 4 ·( I FLAT (1)− I CTAT (5)) (4-6)

As shown in Equations (4-5) and (4-6), a current flowing through the first variable resistor R 3 is the current I FLAT ( 4 ), and a current flowing through the second variable resistor R 4 is a current based on a difference between the current I PTAT ( 2 ) and the current I FLAT ( 1 ) or a current based on a difference between the current I CTAT ( 5 ) and the current I FLAT ( 1 ). As shown in Equation (4-5), when I PTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero. As shown in Equation (4-6), when I CTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero.

Therefore, the voltage generation circuit 28 C according to the present embodiment can obtain the same effect as the voltage generation circuit 28 B according to the third embodiment. Specifically, an absolute value of the output voltage V OUT at a temperature can be adjusted by a value of the first variable resistor R 3 , and a temperature gradient of the output voltage V OUT can be adjusted by a value of the second variable resistor R 4 . Since the values of the first variable resistor R 3 and the second variable resistor R 4 can be independently controlled, the absolute value of the output voltage V OUT and the temperature gradient of the output voltage V OUT can be independently adjusted. Further, by switching the switches SW 3 and SW 11 , it is possible to supply both the output voltage V OUT in which the voltage value increases with an increase in temperature and the output voltage V OUT in which the voltage value decreases with the increase in temperature.

5. Fifth Embodiment

A voltage generation circuit according to a fifth embodiment will be described with reference to FIGS. 11 and 12 . A voltage generation circuit 28 D according to the fifth embodiment is similar to the voltage generation circuit 28 according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit 28 according to the first embodiment will be omitted, and differences from the voltage generation circuit 28 will be mainly described.

5-1. Configuration of Voltage Generation Circuit

As shown in FIG. 11 , the voltage generation circuit 28 D includes a first voltage generation circuit 28 Dp, a second voltage generation circuit 28 Dc, the output terminal V OUT , and a switch SW 28 . The switch SW 28 switches between a connection between the first voltage generation circuit 28 Dp and the output terminal V OUT and a connection between the second voltage generation circuit 28 Dc and the output terminal V OUT .

Each of the first voltage generation circuit 28 Dp and the second voltage generation circuit 28 Dc has the same configuration as that of the voltage generation circuit 28 according to the first embodiment. When the voltage V PTAT is input to an input terminal of a second current generation circuit G 2 p of the first voltage generation circuit 28 Dp, the second current generation circuit G 2 p generates the current I PTAT . Meanwhile, when the voltage V CTAT is input to an input terminal of a second current generation circuit G 2 c of the second voltage generation circuit 28 Dc, the second current generation circuit G 2 c generates the current I CTAT . When the voltage V FLAT is input to a first current generation circuit G 1 p of the first voltage generation circuit 28 Dp and a first current generation circuit G 1 c of the second voltage generation circuit 28 Dc, the current I FLAT is generated.

In the present embodiment, the first current generation circuits G 1 p and G 1 c that generate the current I FLAT are provided in the first voltage generation circuit 28 Dp and the second voltage generation circuit 28 Dc respectively, but the present disclosure is not limited to this configuration. For example, the current I FLAT generated by the first current generation circuit G 1 p of the first voltage generation circuit 28 Dp may be supplied to the second voltage generation circuit 28 Dc. In this case, a pair of transistors T 1 p and T 5 c and a pair of transistors T 1 p and T 7 c each form a current mirror circuit. In the case of the above configuration, the first current generation circuit G 1 c and a transistor T 1 c of the second voltage generation circuit 28 Dc are omitted. Contrary to the above configuration, the current I FLAT generated by the first current generation circuit G 1 c of the second voltage generation circuit 28 Dc may be supplied to the first voltage generation circuit 28 Dp. In this case, a pair of transistors T 1 c and T 5 p and a pair of transistors T 1 c and T 7 p each form a current mirror circuit. In the case of the above configuration, the first current generation circuit G 1 p and the transistor T 1 p of the first voltage generation circuit 28 Dp are omitted.

In the present embodiment, for convenience of explanation, a current generated by the second current generation circuit G 2 p is referred to as a “first current I PTAT ”, and a current generated by the first current generation circuit G 1 p is referred to as a “second current I FLAT ”. A current generated by the second current generation circuit G 2 c is referred to as a “third current I CTAT ”, and a current generated by the first current generation circuit G 1 c is referred to as a “fourth current I FLAT ”. Variable resistors provided in the first voltage generation circuit 28 Dp are referred to as a first variable resistor R 3p and a second variable resistor R 4p . Variable resistors provided in the second voltage generation circuit 28 Dc are referred to as a third variable resistor R 3c and a fourth variable resistor R 4c . In the first voltage generation circuit 28 Dp, the first variable resistor R 3p and the second variable resistor R 4p are connected in series. In the second voltage generation circuit 28 Dc, the third variable resistor R 3c and the fourth variable resistor R 4c are connected in series.

In other words, the first voltage generation circuit 28 Dp generates the first current I PTAT having a temperature-dependent characteristic (the first temperature-dependent characteristic) in which a current value thereof changes with a predetermined change in temperature, and the second current I FLAT having a temperature-dependent characteristic (the second temperature-dependent characteristic) different from the first temperature-dependent characteristic. The second voltage generation circuit 28 Dc generates the third current I CTAT having a temperature-dependent characteristic (a third temperature-dependent characteristic) in which a current value thereof changes in reverse to the first temperature-dependent characteristic with the predetermined change in temperature, and the fourth current I FLAT having a temperature-dependent characteristic (a fourth temperature-dependent characteristic) different from the third temperature-dependent characteristic.

In the present embodiment, the first temperature-dependent characteristic is a temperature-dependent characteristic in which the current value increases with an increase in temperature. The third temperature-dependent characteristic is a temperature-dependent characteristic in which the current value decreases with an increase in temperature. The second temperature-dependent characteristic and the fourth temperature-dependent characteristic are temperature-dependent characteristics in which current values do not change with a change in temperature. Alternatively, the second temperature-dependent characteristic and the fourth temperature-dependent characteristic may be temperature-dependent characteristics in which current values change with a change in temperature.

FIG. 12 is a conceptual diagram showing a configuration of the voltage generation circuit according to the embodiment. Each of the first voltage generation circuit 28 Dp and the second voltage generation circuit 28 Dc has the same configuration as that of the voltage generation circuit 28 in FIG. 3 .

The first voltage generation circuit 28 Dp includes the first path PAS 1 , the second path PAS 2 , and the third path PAS 3 . The first path PAS 1 is a path from an input terminal V IN7p (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4p . The second path PAS 2 is a path from the second node N 2 to an output terminal V OUT10p (or the second power supply line VSS) without passing through the second variable resistor R 4p . The third path PAS 3 is a path from the first node N 1 to the output terminal V OUT8p (or the second power supply line VSS) without passing through the first variable resistor R 3p .

As shown in FIG. 12 , in the first voltage generation circuit 28 Dp, a current 2×I FLAT ( 3 ) is input from the input terminal V IN7p , a first current I PTAT ( 1 ) is input from the input terminal V IN9p , a first current I PTAT ( 4 ) is output to the output terminal V OUT8p , and a second current I FLAT ( 2 ) is output to the output terminal V OUT10p . Although the details will be described later, a current flowing through the first variable resistor R 3p is determined to be the current I FLAT ( 5 ) due to the above input and output.

The second voltage generation circuit 28 Dc includes a fourth path PAS 4 , a fifth path PAS 5 , and a sixth path PAS 6 . The fourth path PAS 4 is a path from an input terminal V IN7c (or the first power supply line VDD) to a third node N 3 without passing through the fourth variable resistor R 4c . The fifth path PAS 5 is a path from a fourth node N 4 to an output terminal V OUT10c (or the second power supply line VSS) without passing through the fourth variable resistor R 4c . The sixth path PAS 6 is a path from the third node N 3 to an output terminal V OUT8c (or the second power supply line VSS) without passing through the third variable resistor R 3c .

As in the first voltage generation circuit 28 Dp, in the second voltage generation circuit 28 Dc, a current 2×I FLAT ( 8 ) is input from the input terminal V IN7c , a third current I CTAT ( 6 ) is input from the input terminal V IN9c , a third current I CTAT ( 9 ) is output to the output terminal V OUT8c , and a fourth current I FLAT ( 7 ) is output to the output terminal V OUT10c . Although the details will be described later, a current flowing through the third variable resistor R 3c is determined to be a current I FLAT ( 10 ) due to the above input and output.

In the first voltage generation circuit 28 Dp, a current (I R3p ) flowing through the first variable resistor R 3p and a current (I R4p ) flowing through the second variable resistor R 4p are expressed as in the following Equations (5-1) and (5-2), respectively. I R4p =I PTAT (1)− I FLAT (2) (5-1) I R3p =2× I FLAT (3)+( I PTAT (1)− I FLAT (2))− I PTAT (4) (5-2)

In the case of Equation (5-2), the term of I PTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 5 ). That is, in the first voltage generation circuit 28 Dp, the current (I R3p ) flowing through the first variable resistor R 3p is I FLAT ( 5 ). I FLAT ( 5 ) is equivalent to the second current I FLAT generated by the first current generation circuit G 1 p.

In the second voltage generation circuit 28 Dc, a current (I R3c ) flowing through the third variable resistor R 3c and a current (I R4c ) flowing through the fourth variable resistor R 4c are expressed as in the following Equations (5-3) and (5-4), respectively. I R4c =I CTAT (6)− I FLAT (7) (5-3) I R3c =2× I FLAT (8)+( I CTAT (6)− I FLAT (7))− I CTAT (9) (5-4)

In the case of Equation (5-4), the term of I CTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 10 ). That is, in the second voltage generation circuit 28 Dc, the current (I R3c ) flowing through the third variable resistor R 3c is I FLAT ( 10 ). I FLAT ( 10 ) is equivalent to the fourth current I FLAT generated by the second voltage generation circuit 28 Dc.

In other words, in the first voltage generation circuit 28 Dp, the current flowing through the first variable resistor R 3p is the second current I FLAT (I FLAT ( 5 )). A current flowing through the second variable resistor R 4p is a current (I PTAT ( 1 )−I FLAT ( 2 )) based on a difference between the first current I PTAT and the second current I FLAT . Similarly, in the second voltage generation circuit 28 Dc, the current flowing through the third variable resistor R 3c is the fourth current I FLAT (I FLAT ( 10 )). A current flowing through the fourth variable resistor R 4c is a current (I CTAT ( 6 )−I FLAT ( 7 )) based on a difference between the third current I CTAT and the fourth current I FLAT .

Furthermore, in the first voltage generation circuit 28 Dp, a current flowing through the first path PAS 1 is the current (2×I FLAT ( 3 )) that is twice the second current I FLAT , a current flowing through the second path PAS 2 is the second current I FLAT ( 2 ), and a current flowing through the third path PAS 3 is the first current I PTAT ( 4 ). Similarly, in the second voltage generation circuit 28 Dc, a current flowing through the fourth path PAS 4 is the current (2×I FLAT ( 8 )) that is twice the fourth current, a current flowing through the fifth path PAS 5 is the fourth current I FLAT ( 7 ), and a current flowing through the sixth path PAS 6 is the third current I CTAT ( 9 ). The current flowing through the first path PAS 1 and the current flowing through the fourth path PAS 4 may be currents (n×I FLAT ) that are n times the second current I FLAT and the fourth current I FLAT (n is a positive number excluding 1), respectively.

5-2. Output of Voltage Generation Circuit 28 D

A voltage of the output terminal V OUT differs when the switch SW 28 is connected to the first voltage generation circuit 28 Dp and when the switch SW 28 is connected to the second voltage generation circuit 28 Dc. The voltage output by each of the first voltage generation circuit 28 Dp and the second voltage generation circuit 28 Dc is calculated as follows.

5-2-1. Output of First Voltage Generation Circuit 28 Dp

Based on Equations (5-1) and (5-2), the voltage of the output terminal V OUT when the switch SW 28 is connected to the first voltage generation circuit 28 Dp is calculated by the following Equation (5-5). V OUT =R 3p ·I FLAT (5)+ R 4p ·( I PTAT (1)− I FLAT (2)) (5-5)

5-2-2. Output of Second Voltage Generation Circuit 28 Dc

Based on Equations (5-3) and (5-4), the voltage of the output terminal V OUT when the switch SW 28 is connected to the second voltage generation circuit 28 Dc is calculated as in the following Equation (5-6). V OUT =R 3c ·I FLAT (10)+ R 4c ·( I CTAT (6)− I FLAT (7)) (5-6)

As shown in Equation (5-5), the current flowing through the first variable resistor R 3p is the second current I FLAT ( 5 ), and the current flowing through the second variable resistor R 4p is a current based on a difference between the first current I PTAT ( 1 ) and the second current I FLAT ( 2 ). As shown in Equation (5-6), a current flowing through the third variable resistor R 3c is the fourth current I FLAT ( 10 ), and the current flowing through the fourth variable resistor R 4c is a current based on a difference between the third current I CTAT ( 6 ) and the fourth current I FLAT ( 7 ). As shown in Equation (5-5), when I PTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero. As shown in Equation (5-6), when I CTAT =I FLAT at a certain temperature Temp 1 , the term of R 4c is zero.

Therefore, as in the voltage generation circuit 28 according to the first embodiment, the voltage generation circuit 28 D according to the present embodiment can adjust an absolute value of the output voltage V OUT at a certain temperature by values of the first variable resistor R 3p and the third variable resistor R 3c , and can adjust a temperature gradient of the output voltage V OUT by values of the second variable resistor R 4p and the fourth variable resistor R 4c . Since the values of the first variable resistor R 3p , the second variable resistor R 4p , the third variable resistor R 3c , and the fourth variable resistor R 4c can be independently controlled, the absolute value of the output voltage V OUT and the temperature gradient of the output voltage V OUT can be independently adjusted. Further, by switching the switch SW 28 , it is possible to supply both the output voltage V OUT in which the voltage value increases with an increase in temperature and the output voltage V OUT in which the voltage value decreases with the increase in temperature.

6. Sixth Embodiment

A voltage generation circuit according to a sixth embodiment will be described with reference to FIGS. 13 and 14 . A voltage generation circuit 28 E according to the sixth embodiment is similar to the voltage generation circuit 28 D according to the fifth embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit 28 D according to the fifth embodiment will be omitted, and differences from the voltage generation circuit 28 D will be mainly described.

6-1. Configuration of Voltage Generation Circuit

As shown in FIG. 13 , the voltage generation circuit 28 E includes a first voltage generation circuit 28 Ep, a second voltage generation circuit 28 Ec, the output terminal V OUT , and the switch SW 28 . The switch SW 28 switches between a connection between the first voltage generation circuit 28 Ep and the output terminal V OUT and a connection between the second voltage generation circuit 28 Ec and the output terminal V OUT .

Each of the first voltage generation circuit 28 Ep and the second voltage generation circuit 28 Ec has the same configuration as that of the voltage generation circuit 28 A according to the second embodiment. The second current generation circuit G 2 p provided in the first voltage generation circuit 28 Ep and the second current generation circuit G 2 c provided in the second voltage generation circuit 28 Ec have the same configurations as those of the second current generation circuits G 2 p and G 2 c according to the fifth embodiment, respectively. Therefore, detailed descriptions of the first voltage generation circuit 28 Ep and the second voltage generation circuit 28 Ec will be omitted.

In the present embodiment, as in the fifth embodiment, a current generated by the second current generation circuit G 2 p is referred to as the “first current I PTAT ”, and a current generated by the first current generation circuit G 1 p is referred to as the “second current I FLAT ”. A current generated by the second current generation circuit G 2 c is referred to as a “third current I CTAT ”, and a current generated by the first current generation circuit G 1 c is referred to as a “fourth current I FLAT ”. Variable resistors provided in the first voltage generation circuit 28 Ep are referred to as the first variable resistor R 3p and the second variable resistor R 4p . Variable resistors provided in the second voltage generation circuit 28 Ec are referred to as the third variable resistor R 3c and the fourth variable resistor R 4c . In the first voltage generation circuit 28 Ep, the first variable resistor R 3p and the second variable resistor R 4p are connected in series. In the second voltage generation circuit 28 Ec, the third variable resistor R 3c and the fourth variable resistor R 4c are connected in series.

In the present embodiment, the first current generation circuits G 1 p and G 1 c that generate the current I FLAT are provided in the first voltage generation circuit 28 Ep and the second voltage generation circuit 28 Ec, respectively, but the present disclosure is not limited to this configuration. For example, the current I FLAT generated by the first current generation circuit G 1 p of the first voltage generation circuit 28 Ep may be supplied to the second voltage generation circuit 28 Ec. In this case, a pair of transistors T 1 p and T 12 c form a current mirror circuit. In the case of the above configuration, the first current generation circuit G 1 c and the transistor T 1 c of the second voltage generation circuit 28 Ec are omitted. Contrary to the above configuration, the current I FLAT generated by the first current generation circuit G 1 c of the second voltage generation circuit 28 Ec may be supplied to the first voltage generation circuit 28 Ep. In this case, a pair of transistors T 1 c and T 12 p form a current mirror circuit. In the case of the above configuration, the first current generation circuit G 1 p and the transistor T 1 p of the first voltage generation circuit 28 Ep are omitted.

FIG. 14 is a conceptual diagram showing a configuration of the voltage generation circuit according to the embodiment. Each of the first voltage generation circuit 28 Ep and the second voltage generation circuit 28 Ec has the same configuration as that of the voltage generation circuit 28 A in FIG. 6 .

The first voltage generation circuit 28 Ep includes the first path PAS 1 and the second path PAS 2 . The first path PAS 1 is a path from the input terminal V IN11p (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4p . The second path PAS 2 is a path from the second node N 2 to the output terminal V OUT13p (or the second power supply line VSS) without passing through the second variable resistor R 4p .

As shown in FIG. 14 , in the first voltage generation circuit 28 Ep, a first current I FLAT ( 3 ) is input from the input terminal V IN11p , a second current I FLAT ( 1 ) is input from the input terminal V IN12p , and a first current I PTAT ( 2 ) is output to the output terminal V OUT13p . Although the details will be described later, a current flowing through the first variable resistor R 3p is determined to be the current I FLAT ( 4 ) due to the above input and output.

The second voltage generation circuit 28 Ec includes the fourth path PAS 4 and the fifth path PAS 5 . The fourth path PAS 4 is a path from the input terminal V IN11c (or the first power supply line VDD) to the third node N 3 without passing through the fourth variable resistor R 4c . The fifth path PAS 5 is a path from the fourth node N 4 to the output terminal V OUT13c (or the second power supply line VSS) without passing through the fourth variable resistor R 4c .

As in the first voltage generation circuit 28 Ep, in the second voltage generation circuit 28 Ec, a third current I CTAT ( 7 ) is input from the input terminal V IN11c , a fourth current I FLAT ( 5 ) is input from the input terminal V IN12c , and the third current I CTAT ( 6 ) is output to the output terminal V OUT13c . Although the details will be described later, a current flowing through the third variable resistor R 3c is determined to be a current I FLAT ( 8 ) due to the above input and output.

In the first voltage generation circuit 28 Ep, a current (I R3p ) flowing through the first variable resistor R 3p and a current (I R4p ) flowing through the second variable resistor R 4p are expressed by the following Equations (6-1) and (6-2), respectively. I R4p =I FLAT (1)− I PTAT (2) (6-1) I R3p =I PTAT (3)+( I FLAT (1)− I PTAT (2)) (6-2)

In this case, since a current of a value based on I FLAT ( 1 )−I PTAT ( 2 ) is output to the output terminal V OUT the case of performing such an operation is referred to as “during a CTAT operation”.

In the case of Equation (6-2), the term of I PTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 4 ). That is, in the first voltage generation circuit 28 Ep, the current (I R3p ) flowing through the first variable resistor R 3p is I FLAT ( 4 ). I FLAT ( 4 ) is equivalent to the second current I FLAT generated by the first current generation circuit G 1 p.

In the second voltage generation circuit 28 Ec, a current (I R3c ) flowing through the third variable resistor R 3c and a current (I R4c ) flowing through the fourth variable resistor R 4c are expressed by the following Equations (6-3) and (6-4), respectively. I R4c =I FLAT (5)− I CTAT (6) (6-3) I R3c =I CTAT (7)+( I FLAT (5)− I CTAT (6)) (6-4)

In this case, since a current of a value based on I FLAT ( 5 )−I CTAT ( 6 ) is output to the output terminal V OUT , the case of performing such an operation is referred to as “during a PTAT operation”.

In the case of Equation (6-4), the term of I CTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 8 ). That is, in the second voltage generation circuit 28 Ec, the current (I R3c ) flowing through the third variable resistor R 3c is I FLAT ( 8 ). I FLAT ( 8 ) is equivalent to the fourth current I FLAT generated by the second voltage generation circuit 28 Ec.

In other words, in the first voltage generation circuit 28 Ep, the current flowing through the first variable resistor R 3p is the second current I FLAT (I FLAT ( 4 )). A current flowing through the second variable resistor R 4p is a current (I FLAT ( 1 )−I PTAT ( 2 )) based on a difference between the first current I PTAT and the second current I FLAT . Similarly, in the second voltage generation circuit 28 Ec, the current flowing through the third variable resistor R 3c is the fourth current I FLAT (I FLAT ( 8 )). A current flowing through the fourth variable resistor R 4c is a current (I FLAT ( 5 )−I CTAT ( 6 )) based on a difference between the third current I CTAT and the fourth current I FLAT .

Furthermore, in the first voltage generation circuit 28 Ep, a current flowing through the first path PAS 1 is the first current I PTAT ( 3 ), and a current flowing through the second path PAS 2 is the first current I PTAT ( 2 ). Similarly, in the second voltage generation circuit 28 Ec, a current flowing through the fourth path PAS 4 is the third current I CTAT ( 7 ), and a current flowing through the fifth path PAS 5 is the third current I CTAT ( 6 ).

6-2. Output of Voltage Generation Circuit 28 E

A voltage of the output terminal V OUT differs when the switch SW 28 is connected to the first voltage generation circuit 28 Ep and when the switch SW 28 is connected to the second voltage generation circuit 28 Ec. The voltage output by each of the first voltage generation circuit 28 Ep and the second voltage generation circuit 28 Ec is calculated as follows.

6-2-1. Output of First Voltage Generation Circuit 28 Ep During CTAT Operation

Based on Equations (6-1) and (6-2), the voltage of the output terminal V OUT when the switch SW 28 is connected to the first voltage generation circuit 28 Ep is calculated by the following Equation (6-5). V OUT =R 3p ·I FLAT (4)+ R 4p ·( I FLAT (1)− I PTAT (2)) (6-5) 6-2-2. Output of Second Voltage Generation Circuit 28 Ec During PTAT Operation

Based on Equations (6-3) and (6-4), the voltage of the output terminal V OUT when the switch SW 28 is connected to the second voltage generation circuit 28 Ec is calculated as in the following Equation (6-6). V OUT =R 3c ·I FLAT (8)+ R 4c ·( I FLAT (5)− I CTAT (6) (6-6)

As shown in Equation (6-5), the current flowing through the first variable resistor R 3p is a second current I FLAT ( 4 ), and the current flowing through the second variable resistor R 4p is a current based on a difference between the first current I PTAT ( 2 ) and the second current I FLAT ( 1 ). As shown in Equation (6-6), the current flowing through the third variable resistor R 3c is a fourth current I FLAT ( 8 ), and the current flowing through the fourth variable resistor R 4c is a current based on a difference between the third current I CTAT ( 6 ) and the fourth current I FLAT ( 5 ). As shown in Equation (6-5), when I PTAT =I FLAT at a certain temperature Temp 1 , the term of R 4p is zero. As shown in Equation (6-6), when I CTAT =I FLAT at a certain temperature Temp 1 , the term of R 4c is zero.

Therefore, the voltage generation circuit 28 E according to the present embodiment can obtain the same effect as the voltage generation circuit 28 D.

7. Seventh Embodiment

A voltage generation circuit according to a seventh embodiment will be described with reference to FIGS. 15 to 17 . A voltage generation circuit 28 F according to the seventh embodiment is similar to the voltage generation circuit 28 according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit 28 according to the first embodiment will be omitted, and differences from the voltage generation circuit 28 will be mainly described.

7-1. Configuration of Voltage Generation Circuit

FIG. 15 is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown in FIG. 15 , in the voltage generation circuit 28 F, transistors T 14 to T 17 and switches SW 10 and SW 14 to SW 17 are provided instead of the transistors T 7 to T 9 that are provided in the voltage generation circuit 28 shown in FIG. 2 . The transistors T 14 to T 16 are p-type transistors. The transistor T 17 is an n-type transistor. In the present embodiment, when the voltage V PTAT is input to an input terminal of the second current generation circuit G 2 , the second current generation circuit G 2 generates the current I PTAT .

The transistor T 10 and the switch SW 10 are connected in series between the output terminal V OUT and the second power supply line VSS.

The transistor T 14 and the switch SW 14 are connected in series between the first power supply line VDD and the second node N 2 . In a state in which the switch SW 15 is connected to a second node N 2 side, the transistor T 15 and the switch SW 15 are connected in series between the first power supply line VDD and the second node N 2 . The transistor T 14 and the switch SW 14 are connected in parallel with the transistor T 15 and the switch SW 15 between the first power supply line VDD and the second node N 2 . A state in which the transistor T 14 is connected to the second node N 2 and a state in which the transistor T 15 is connected to the second node N 2 are switched by the switches SW 14 and SW 15 .

In a state in which the switch SW 15 is connected to a first node N 1 side, the transistor T 15 and the switch SW 15 are connected in series between the first power supply line VDD and the first node N 1 . The transistor T 16 and the switch SW 16 are connected in series between the first power supply line VDD and the first node N 1 . The transistor T 15 and the switch SW 15 are connected in parallel with the transistor T 16 and the switch SW 16 between the first power supply line VDD and the first node N 1 . A state in which the transistor T 15 is connected to the first node N 1 and a state in which the transistor T 16 is connected to the first node N 1 are switched by the switches SW 15 and SW 16 .

In a state in which the switch SW 17 is connected to a first node N 1 side, the transistor T 17 and the switch SW 17 are connected in series between the first node N 1 and the second power supply line VSS. In a state in which the switch SW 17 is connected to the second node N 2 side, the transistor T 17 and the switch SW 17 are connected in series between the second node N 2 and the second power supply line VSS. A state in which the transistor T 17 is connected to the first node N 1 and a state in which the transistor T 17 is connected to the second node N 2 are switched by the switch SW 17 .

A pair of transistors T 1 and T 14 , a pair of transistors T 1 and T 16 , a pair of transistors T 2 and T 15 , and a pair of transistors T 4 and T 17 each form a current mirror circuit. Sizes of the transistors are the same. As the transistor T 16 denoted by “×2”, two transistors are connected in parallel. In this configuration, a current flowing through the transistor T 14 is the current I FLAT , a current flowing through the transistor T 15 is the current I PTAT , a current flowing through the transistor T 16 is the current 2×I FLAT , and a current flowing through the transistor T 17 is the current I PTAT .

FIG. 16 and FIG. 17 are conceptual diagrams showing the configuration of the voltage generation circuit according to the embodiment. The transistors T 14 , T 15 , and T 16 in FIG. 15 correspond to input terminals V IN14 , V IN15 , and V IN16 in FIGS. 16 and 17 , respectively, and the transistors T 10 and T 17 in FIG. 15 correspond to output terminals V OUT10 and V OUT17 in FIGS. 16 and 17 , respectively. The current I FLAT is input from the input terminal V IN14 , the current I PTAT is input from the input terminal V IN15 , and the current 2×I FLAT is input from the input terminal V IN16 . The current I FLAT is output to the output terminal V OUT10 , and the current I PTAT is output to the output terminal V OUT17 .

An input terminal connected to the second node N 2 is switched to the input terminal V IN14 or the input terminal V IN15 , and a current supplied to the second node N 2 is switched to the current I FLAT or the current I PTAT by the switches SW 14 and SW 15 . An input terminal connected to the first node N 1 is switched to the input terminal V IN15 or the input terminal V IN16 , and a current supplied to the first node N 1 is switched to the current I PTAT or 2×I FLAT by the switches SW 15 and SW 16 .

The switches SW 10 and SW 14 to SW 17 are interlocked with one another. As shown in FIG. 16 , when the switch SW 10 is in an ON state (a conductive state), the switch SW 14 is in an OFF state (a non-conductive state), the switch SW 15 is connected to the second node N 2 side, the switch SW 16 is in the ON state, and the switch SW 17 is connected to the first node N 1 side. As shown in FIG. 17 , when the switch SW 10 is in the OFF state, the switch SW 14 is in the ON state, the switch SW 15 is connected to the first node N 1 side, the switch SW 16 is in the OFF state, and the switch SW 17 is connected to the second node N 2 side.

As shown in FIGS. 16 and 17 , the voltage generation circuit 28 F includes the first path PAS 1 , the second path PAS 2 , and the third path PAS 3 . The first path PAS 1 is a path from the input terminal V IN16 (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4 , and a path from the input terminal V IN15 (or the first power supply line VDD) to the first node N 1 without passing through the second variable resistor R 4 . The second path PAS 2 is a path from the second node N 2 to the output terminal V OUT10 or the output terminal V OUT17 (or the second power supply line VSS) without passing through the second variable resistor R 3 . The third path PAS 3 is a path from the first node N 1 to the output terminal V OUT17 (or the second power supply line VSS) without passing through the first variable resistor R 3 .

As shown in FIG. 16 , the current I PTAT ( 1 ) is supplied from the input terminal V IN15 to the second node N 2 , a current 2×I FLAT ( 4 ) is supplied from the input terminal V IN16 to the first node N 1 , the current I FLAT ( 2 ) is output from the second node N 2 to the output terminal V OUT10 , and the current I PTAT ( 3 ) is output from the first node N 1 to the output terminal V OUT17 . Although the details will be described later, the current flowing through the first variable resistor R 3 is determined to be the current I FLAT ( 5 ) due to the above input and output.

As shown in FIG. 17 , a current I FLAT ( 6 ) is supplied from the input terminal V IN14 to the second node N 2 , a current I PTAT ( 8 ) is supplied from the input terminal V IN15 to the first node N 1 , and a current I PTAT ( 7 ) is output from the second node N 2 to the output terminal V OUT17 . Although the details will be described later, the current flowing through the first variable resistor R 3 is determined to be the current I FLAT ( 5 ) due to the above input and output.

In the state shown in FIG. 16 , a current (I R3 ) flowing through the first variable resistor R 3 and a current (I R4 ) flowing through the second variable resistor R 4 are expressed by the following Equations (7-1) and (7-2), respectively. I R4 =I PTAT (1)− I FLAT (2) (7-1) I R3 =2× I FLAT (4)+( I PTAT (1)− I FLAT (2))− I PTAT (3) (7-2)

In this case, since a current of a value based on I PTAT ( 1 )−I FLAT ( 2 ) is output to the output terminal V OUT , the case of performing such an operation is referred to as “during a PTAT operation”.

In the state shown in FIG. 17 , a current (I R3 ) flowing through the first variable resistor R 3 and a current (I R4 ) flowing through the second variable resistor R 4 are expressed by the following Equations (7-3) and (7-4), respectively. I R4 =I FLAT (6)− I PTAT (7) (7-3) I R3 =I PTAT (8)+( I FLAT (6)− I PTAT (7)) (7-4)

In this case, since a current of a value based on I FLAT ( 6 )−I PTAT ( 7 ) is output to the output terminal V OUT , the case of performing such an operation is referred to as “during a CTAT operation”.

In the case of Equation (7-2), the term of I PTAT disappears and only I FLAT remains. In the case of Equation (7-4), the term of I PTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 5 ). That is, the current (I R3 ) flowing through the first variable resistor R 3 is I FLAT ( 5 ) even in the case of both “during the PTAT operation” and “during the CTAT operation”.

In other words, “during the PTAT operation” shown in FIG. 16 , when a current supplied to the second node N 2 is the current I PTAT ( 1 ), a current flowing through the first path PAS 1 is the current (2×I FLAT ( 4 )) that is twice the current I FLAT , a current flowing through the second path PAS 2 is the current I FLAT ( 2 ), and a current flowing through the third path PAS 3 is the current I PTAT ( 3 ). The current flowing through the first path PAS 1 may be a current (n×I FLAT ) that is n times the current I FLAT (n is a positive number excluding 1).

“During the CTAT operation” shown in FIG. 17 , when a current supplied to the second node N 2 is the current I FLAT ( 6 ), the current flowing through the first path PAS 1 is the current I PTAT ( 8 ), the current flowing through the second path PAS 2 is the current I PTAT ( 7 ), and the third path PAS 3 is cut off.

7-2. Output of Voltage Generation Circuit

A voltage of the output terminal V OUT differs during the PTAT operation and during the CTAT operation. In each case, the voltage of the output terminal V OUT is calculated as follows.

7-2-1. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (7-1) and (7-2), the voltage of the output terminal V OUT is calculated as in the following Equation (7-5). V OUT =R 3 ·I FLAT (5)+ R 4 ·( I PTAT (1)− I FLAT (2)) (7-5) 7-2-2. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (7-3) and (7-4), the voltage of the output terminal V OUT is calculated as in the following Equation (7-6). V OUT =R 3 ·I FLAT (5)+ R 4 ·( I FLAT (6)− I PTAT (7)) (7-6)

As shown in Equations (7-5) and (7-6), the current flowing through the first variable resistor R 3 is the current I FLAT ( 5 ), and a current flowing through the second variable resistor R 4 is a current based on a difference between the current I PTAT ( 1 ) and the current I FLAT ( 2 ) or a current based on a difference between the current I PTAT ( 7 ) and the current I FLAT ( 6 ). As shown in Equations (7-5) and (7-6), when I PTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero.

Therefore, the voltage generation circuit 28 F according to the present embodiment can obtain the same effect as the voltage generation circuit 28 according to the first embodiment. Further, by switching the switches SW 10 and SW 14 to SW 17 , it is possible to supply both the output voltage V OUT in which the voltage value increases with an increase in temperature and the output voltage V OUT in which the voltage value decreases with the increase in temperature.

8. Eighth Embodiment

A voltage generation circuit according to an eighth embodiment will be described with reference to FIGS. 18 and 19 . A voltage generation circuit 28 G according to the eighth embodiment has substantially the same circuit configuration as that of the voltage generation circuit 28 F according to the seventh embodiment, and is different from the voltage generation circuit 28 F in a switching method of the switches SW 10 and SW 14 to SW 17 . In the following description, a description of the same configuration as that of the voltage generation circuit 28 F according to the seventh embodiment will be omitted, and differences from the voltage generation circuit 28 F will be mainly described.

FIGS. 18 and 19 are conceptual diagrams showing a configuration of the voltage generation circuit according to the embodiment. A correspondence relationship between each transistor shown in FIG. 15 and each input terminal and each output terminal shown in FIGS. 18 and 19 is the same as that of the seventh embodiment.

In the present embodiment, when the voltage V CTAT is input to an input terminal of the second current generation circuit G 2 , the second current generation circuit G 2 generates the current I CTAT . Therefore, the current I CTAT is supplied from the input terminal V IN15 , and the current I CTAT is output to the output terminal V OUT17 .

As shown in FIG. 18 , the current I FLAT ( 1 ) is supplied from the input terminal V IN14 to the second node N 2 , a current I CTAT ( 3 ) is supplied from the input terminal V IN15 to the first node N 1 , and a current I CTAT ( 2 ) is output from the second node N 2 to the output terminal V OUT17 . Although the details will be described later, a current flowing through the first variable resistor R 3 is determined to be a current I FLAT ( 4 ) due to the above input and output.

As shown in FIG. 19 , the current I CTAT ( 5 ) is supplied from the input terminal V IN15 to the second node N 2 , the current 2×I FLAT ( 8 ) is supplied from the input terminal V IN16 to the first node N 1 , the current I FLAT ( 6 ) is output from the second node N 2 to the output terminal V OUT10 , and the current I CTAT ( 7 ) is output from the first node N 1 to the output terminal V OUT17 . Although the details will be described later, a current flowing through the first variable resistor R 3 is determined to be a current I FLAT ( 4 ) due to the above input and output.

In the state shown in FIG. 18 , a current (I R3 ) flowing through the first variable resistor R 3 and a current (I R4 ) flowing through the second variable resistor R 4 are expressed by the following Equations (8-1) and (8-2), respectively. I R4 =I FLAT (1)− I CTAT (2) (8-1) I R3 =I FLAT (1)− I CTAT (2)+ I CTAT (3) (8-2)

In this case, since a current of a value based on I FLAT ( 1 )−I CTAT ( 2 ) is output to the output terminal V OUT , the case of performing such an operation is referred to as “during a PTAT operation”.

In the state shown in FIG. 19 , the current (I R3 ) flowing through the first variable resistor R 3 and the current (I R4 ) flowing through the second variable resistor R 4 are expressed as in the following Equations (8-3) and (8-4), respectively. I R4 =I CTAT (5)− I FLAT (6) (8-3) I R3 =2× I FLAT (8)+ I CTAT (5)− I FLAT (6)− I CTAT (7) (8-4)

In this case, since a current of a value based on I CTAT ( 5 )−I FLAT ( 6 ) is output to the output terminal V OUT , the case of performing such an operation is referred to as “during a CTAT operation”.

In the case of Equation (8-2), the term of I CTAT disappears and only I FLAT remains. In the case of Equation (8-4), the term of I CTAT disappears and only I FLAT remains. As described above, the remaining I FLAT is referred to as I FLAT ( 4 ). That is, the current (I R3 ) flowing through the first variable resistor R 3 is I FLAT ( 4 ) even in the case of both “during the PTAT operation” and “during the CTAT operation”.

In other words, “during the PTAT operation” shown in FIG. 18 , when a current supplied to the second node N 2 is the current I FLAT ( 1 ), a current flowing through the first path PAS 1 is the current I CTAT ( 3 ), a current flowing through the second path PAS 2 is the current I CTAT ( 2 ), and the third path PAS 3 is cut off.

“During the CTAT operation” shown in FIG. 19 , when the current supplied to the second node N 2 is the current I CTAT ( 5 ), the current flowing through the first path PAS 1 is a current (2×I FLAT ( 8 )) that is twice the current I FLAT , the current flowing through the second path PAS 2 is the current I FLAT ( 6 ), and a current flowing through the third path PAS 3 is the current I CTAT ( 7 ). The current flowing through the first path PAS 1 may be a current (n×I FLAT ) that is n times the current I FLAT (n is a positive number excluding 1).

8-2. Output of Voltage Generation Circuit

A voltage of the output terminal V OUT differs during the PTAT operation and during the CTAT operation. In each case, the voltage of the output terminal V OUT is calculated as follows.

8-2-1. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (8-1) and (8-2), the voltage of the output terminal V OUT is calculated as in the following Equation (8-5). V OUT =R 3 ·I FLAT (4)+ R 4 ·( I FLAT (1)− I CTAT (2)) (8-5) 8-2-2. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (8-3) and (8-4), the voltage of the output terminal V OUT is calculated as in the following Equation (8-6). V OUT =R 3 ·I FLAT (4)+ R 4 ·( I CTAT (5)− I FLAT (6)) (8-6)

As shown in Equations (8-5) and (8-6), a current flowing through the first variable resistor R 3 is the current I FLAT ( 4 ), and a current flowing through the second variable resistor R 4 is a current based on a difference between the current I FLAT ( 1 ) and the current I CTAT ( 2 ) or a current based on a difference between the current I CTAT ( 5 ) and the current I FLAT ( 6 ). As shown in Equations (8-5) and (8-6), when I CTAT =I FLAT at a certain temperature Temp 1 , the term of R 4 is zero.

Therefore, the voltage generation circuit 28 G according to the present embodiment can obtain the same effect as the voltage generation circuit 28 F according to the seventh embodiment.

While certain embodiments have been described with reference to the accompanying drawings, these embodiments are not intended to limit the scope of the disclosure, and may be embodied in a variety of other forms. For example, a device to which additions, omissions, or modifications of elements are made by those skilled in the art based on the voltage generation circuit according to the present embodiment falls within the scope of the present disclosure as long as the gist of the present disclosure is provided. Further, the embodiments may be appropriately combined if there is no contradiction with each other, and technical matters common to each embodiment are included in each embodiment even if there is no explicit description.

Even with other actions and effects different from the actions and effects brought about by the aspects of the above-described embodiments, it is understood that, as a matter of course, actions and effects apparent from the description of the present specification, or actions and effects that can be easily predicted by those skilled in the art are brought about by the present disclosure.