Package Substrate, Package Using the Same, and Method of Manufacturing the Same

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from continuous reductions in minimum feature size, which allows more smaller components to be integrated into a given area. These smaller electronic components also demand smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor components include quad flat packages (QFPs), pin grid array (PGA) packages, ball grid array (BGA) packages, flip chips (FC), three-dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices and so on. The formation of the redistribution circuit structure also plays an important role during packaging process.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1 A through 1 O illustrate cross-sectional views of intermediate steps of forming a package using a package substrate having a semiconductor device embedded therein, in accordance with some embodiments.

FIGS. 2 A and 2 B illustrate top views of cavity substrates.

FIGS. 3 A through 3 D illustrate cross-sectional views of intermediate steps of forming a semiconductor device, in accordance with some embodiments.

FIGS. 4 A and 4 B are various views of device components of a semiconductor device, in accordance with another embodiment.

FIGS. 5 A and 5 B illustrate cross-sectional views of device components of a semiconductor device, in accordance with yet another embodiment.

FIG. 5 C illustrate cross-sectional views of intermediate steps of a package using a package substrate having a semiconductor device embedded therein, in accordance with other some embodiments.

FIGS. 6 A and 6 B illustrate cross-sectional views of device components of a semiconductor device, in accordance with some other embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such thon the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments discussed below provide a package using a package substrate having a semiconductor device embedded therein. The semiconductor device may have electrical terminals on its two sides to couple to a component attached on the package substrate through redistribution structures of the package substrate.

FIGS. 1 A through 1 O illustrate cross-sectional views of intermediate steps of forming a package using a package substrate having a semiconductor device embedded therein, in accordance with some embodiments.

Referring first to FIG. 1 A there is shown a substrate (or referred to as a substrate core) 112 including an insulation layer 100 with conductive layers 110 on both sides of the insulation layer 100 , in accordance with some embodiments. In some embodiments, substrate 112 is a double-sided copper clad laminate (CCL). The insulation layer 100 may be a pre-impregnated composite fiber (prepreg), ajinomoto build-up film (ABF), paper, glass fiber, non-woven glass fabric, other insulating materials or combinations thereof. The conductive layers 110 may be one or more layers of copper, nickel, aluminum, other conductive materials or combination thereof laminated or formed onto opposing sides 100 -FS and 100 -BS of the insulation layer 100 .

Referring to FIG. 1 B , through holes 114 are formed in the substrate 112 . In some embodiments, the through holes 114 are formed by laser drilling. Other processes, e.g., mechanical drilling, etching, or the like, may also be used. The top-view shape of through holes 114 may be circular (shown in FIGS. 2 A and 2 B ), rectangular (not shown), or any other shape.

Referring to FIG. 1 C , a conductive material is formed on the conductive layers 110 and sidewalls of the through holes 114 to form a conductive layer 115 . The conductive material of the conductive layers 115 may be formed by, for example, plating, or the like. Prior to forming the conductive material on the conductive layers 110 and sidewalls of the through holes 114 , a surface preparation process may be performed. The surface preparation process may include cleaning the exposed surfaces of the substrate 112 (e.g., surfaces of conductive layers 110 and surfaces of the insulation layer 100 in through holes 114 ) with one or more cleaning solutions (e.g., sulfuric acid, chromic acid, neutralizing alkaline solution, water rinse etc.) to remove or reduce soil, oils, and/or native oxide films. A desmear process may be performed to clean the area near the through holes 114 , which may have been smeared with the material of the insulation layer 100 that was removed to form the through holes 114 . The desmearing may be accomplished mechanically (e.g., blasting with a fine abrasive in a wet slurry), chemically (e.g., rinsing with a combination of organic solvents, permanganate etc.), or by a combination of mechanical and chemical desmearing. Following cleaning, treatment with a chemical conditioner, which facilitates adsorption of an activator used during subsequent electroless plating, may be used. In some embodiments, the conditioning step may be followed by micro-etching conductive layers 110 to micro-roughen the conductive surface for better bonding between the metal foil and the later deposited conductive material.

Referring to FIG. 1 D , the conductive layers are patterned to form conductive traces 116 . The conductive traces 116 may include conductive traces 116 F, 116 B, and 116 P connected each other. The conductive trace 116 F is formed on the sides 100 -FS of the insulation layer 100 . The conductive traces 116 B is formed on the sides 100 -BS of the insulation layer 100 . The conductive traces 116 P are formed on the sidewalls of the insulation layer 100 in the through holes 114 , and connect to a portions of the conductive trace 116 F and 116 B.

Referring to FIG. 1 D , a cavity hole 118 is formed for form a cavity substrate 120 illustrated in FIG. 2 A . The cavity hole 118 is formed in a region R 1 of the substrate 112 , and the through holes 114 are formed in a region R 2 of the substrate 112 . The region R 1 is a region for forming a semiconductor device therein, and may be referred to as a semiconductor device region. The region R 2 is a region outside the semiconductor device region. The cavity hole 118 may be formed by removing a portion of the conductive layers 115 on the opposing sides 100 -FS and 100 -BS of the insulation layer 100 , and the insulation layer 100 in accordance with some embodiments. In some embodiments, the cavity hole 118 are formed by laser drilling. Other processes, e.g., mechanical drilling, etching, or the like, may also be used. The top-view shape of cavity hole 118 may be rectangular (shown in FIGS. 2 A and 2 B ), circular (not shown), or any other shape.

Although FIGS. 1 D and 2 A illustrates one cavity hole 118 formed in the substrate 112 , it should be appreciated that multiple cavity holes 118 may also be formed in the substrate 112 , as shown in FIG. 2 B . In FIG. 2 B , the cavity holes 118 may have a same size or different sizes, and may be have a same shape or different shapes. The cavity holes 118 each are surrounded by the through hole 114 in accordance with some embodiments, but it is not limited thereto. The number of the cavity holes 118 in the cavity substrate 120 may be 2 to 50, or more.

Referring to FIG. 1 E , the cavity substrate 120 shown in FIG. 1 D is attached to a tape TP. The tape TP may be attached to a frame (not shown). A semiconductor device 600 may be placed inside the cavity hole 118 (shown in FIG. 1 D ) of the cavity substrate 120 using a pick-and-place (PnP) tool. The semiconductor device 600 may be an integrated circuit die, a packaged die, an integrated passive device (IPD), an interposer, an antenna-in-package (AIP), a micro-electro-mechanical system (MEMS) package, or the like. In some embodiments, the semiconductor device 600 is adhered to the tape TP, as illustrated in FIG. 1 E . Although FIG. 1 E illustrates one semiconductor device 600 placed in each cavity hole 118 , it should be appreciated that multiple dies may also be placed in the cavity hole 118 of the cavity substrate 120 . For example, in some embodiments, the semiconductor device 600 may be a plurality of devices placed laterally adjacent one another and/or stacked upon each other, wherein the multiple devices may have the same or different sizes.

In the example illustrated in FIG. 1 E , the semiconductor device 600 has double-sided electrical terminals. That is the semiconductor device 600 has two terminal sides 600 -FS and 600 -BS. The semiconductor device 600 may be a semiconductor device, e.g., an integrated circuit die such as, a passive die, a logic die (e.g., microprocessor, microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), etc.), a system-on-a-chip (SoC) die (e.g., power management integrated circuit (PMIC), mixed signal integrated circuit, etc.), a radio frequency integrated circuit (RFIC) die, a digital signal processing (DSP) die, the like, or a combination thereof.

Before being placed onto the cavity substrate 120 , the semiconductor device 600 may be processed according to applicable manufacturing processes to form the respective device structure. For example, the semiconductor device 600 may have been processed to form integrated circuits within the semiconductor device 600 . As illustrated in FIG. 1 E , in some embodiments, the semiconductor device 600 includes device components 200 and 300 , and an adhesive 400 therebetween.

The device components 200 and 300 may be passive components such as capacitors, resistors, and inductors. The device components 200 and 300 may be passive components with same type or different types. In some embodiments, the device components 200 and 300 are capacitor components. In alternative, the device component 200 is a capacitor component, and the device component 300 is an inductor component or a resistor component.

In some embodiments in which the device components 200 and 300 of the semiconductor device 600 are capacitor components, the semiconductor device 600 may be a semiconductor device 600 A shown in FIG. 3 D , a semiconductor device 600 B shown in FIG. 5 A , a semiconductor device 600 C shown in FIG. 6 A , or a semiconductor device 600 D shown in FIG. 6 B .

In FIG. 3 D , the semiconductor device 600 A includes device components 200 and 300 A. The device component 200 is bonded to the device component 300 A through an adhesive 400 in back-to-back manner. Further, sidewalls of the device components 200 and 300 A are laterally encapsulated by an encapsulation layer 500 .

The semiconductor device 600 A shown in FIG. 3 D may be processed according to a manufacturing processes shown in FIGS. 3 A to 3 D . The more detailed structure of the device components 200 and 300 A are shown in FIG. 4 A .

Referring to FIGS. 3 A and 4 A , the device component 200 may be a passive component including a semiconductor substrate 202 , a capacitor 210 , an interconnect structure 230 , conductive pads 250 , and a passivation layer 260 . In some embodiments, the device component 200 may be referred to as a silicon cap. The semiconductor substrate 202 may be a bulk substrate or an active layer of a semiconductor-on-insulator (SOI) substrate and may include a group-IV semiconductor such as silicon and germanium, a compound semiconductor, and/or an alloy semiconductor; doped or undoped.

Referring to FIG. 4 A , the semiconductor substrate 202 includes a number of trenches 212 to establish a capacitor 210 in an upper surface of the semiconductor substrate 202 . The device component 200 may include one capacitor 210 or multiple capacitors 210 . The capacitor 210 may be referred to as a metal-insulator-metal (MIM) capacitor, a MIM capacitor cell, or a trench capacitor. The capacitor 210 includes a bottom electrode layer 214 , an insulating layer 216 , and a top electrode layer 218 conformally arranged within the trenches 212 and on the semiconductor substrate 202 .

The bottom electrode layer 214 and the top electrode layer 218 each may be or comprise, for example, doped polysilicon, titanium nitride (e.g., TiN), tantalum nitride (e.g., TaN), aluminum copper (e.g., AlCu), some other suitable metal(s) and/or material(s), or any combination of the foregoing. In some embodiments, the bottom electrode layers 214 and the top electrode layer 218 each comprises a tantalum nitride layer and an aluminum copper layer stacked upon each other. The insulating layer 216 may, for example, be or comprise silicon oxide, a high κ dielectric, some other suitable dielectric(s), or any combination of the foregoing. The high κ dielectric has a dielectric constant κ greater than that of silicon nitride and/or greater than about 10, 20, or 50. Other values are, however, amenable. The high κ dielectric may be or comprise, for example, hafnium oxide (e.g., HfO 2 ), zirconium oxide (e.g., ZrO 2 ), aluminum oxide (e.g., Al 2 O 3 ), tantalum oxide (e.g., Ta 2 O 5 ), titanium oxide (e.g., TiO 2 ), some other suitable high κ dielectric(s), or any combination of the foregoing.

The interconnect structure 230 may include, for example, metallization patterns 240 in one or more dielectric layers 232 formed on the semiconductor substrate 202 to interconnect the capacitor 210 formed in and/or semiconductor substrate 202 to form an integrated circuit. The interconnect structure 230 may further include etch stop layers 234 between the dielectric layers 232 . The dielectric layer 232 and the etch stop layers 234 each may be or comprise, for example, silicon nitride, silicon oxide, or any combination of the foregoing.

The metallization patterns 240 include conductive vias 242 and conductive layers 244 to form conductive paths between the capacitor 210 and the conductive pads 250 . The conductive vias 242 includes conductive vias 242 a and 242 b , and the conductive layers 244 includes conductive layers 244 a and 244 b . The conductive vias 242 and conductive layers 244 may be or comprise, for example, copper, aluminum copper, tungsten, some other suitable metal(s), or any combination of the foregoing.

The conductive pads 250 may be metal pads to which external connections are made. The conductive pads 250 may be or comprise, for example, copper, aluminum copper, tungsten, some other suitable metal(s), or any combination of the foregoing. The passivation layer 260 is formed on the dielectric layer 232 or the etch stop layer 234 of the interconnect structure 230 and on portions of the conductive pads 250 . The passivation layer 260 may be one or more layers of conductive materials. The passivation layer 260 may be or comprise, for example, silicon oxide, silicon nitride, polyimide, some other suitable dielectric(s), or any combination of the foregoing.

In some embodiments, the conductive vias 242 a , the conductive layers 244 a and conductive pad 250 a are coupled the top electrode layer 218 , through the dielectric layers 232 and etch stop layers 234 to make electrical contact with the top electrode layer 218 ; and the conductive vias 242 b , the conductive layers 244 b and conductive pad 250 b are coupled the top electrode layer 214 , through the dielectric layers 232 and etch stop layers 234 to make electrical contact with the bottom electrode layer 214 .

In FIGS. 3 A and 4 A , the device component 300 A may be a passive component, and the structure of the device component 300 A may be similar to or different from the device component 200 . In some embodiments, the device component 300 A includes a semiconductor substrate 302 , a capacitor 310 , an interconnect structure 330 , and conductive pads 350 . The semiconductor substrate 302 , the capacitor 310 , the interconnect structure 330 , and the conductive pads 350 of the device component 300 B may be similar to corresponding components of the device component 200 . In some embodiments, the device component 300 A is free of passivation layer, and thus top surface and sidewall surfaces of the conductive pads 350 are exposed. In alternative some embodiments, a device component 300 B includes a passivation layer 360 shown in FIGS. 5 A and 5 B , and it will be described in detail later. In some embodiments, the top area A 3 of the conductive pads 350 each is greater than the top area A 2 of the conductive pad 250 as shown in FIG. 4 B , but it is not limited thereto.

Referring to FIG. 3 B , a backside 200 -BS of the device component 200 is bonded to a backside 300 -BS of the device component 300 A through the adhesive 400 . The adhesive 400 may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive 400 may be applied to the backside 200 -BS of the device component 200 , such as to a backside of the respective semiconductor wafer prior to singulation. The device component 200 , and the device component 300 may be respectively singulated, such as by sawing or dicing, and adhered each other by the adhesive 400 using, for example, PnP tool.

Referring to FIG. 3 C , the encapsulation layer 500 is formed to encapsulate the device components 200 and 300 A. The encapsulation layer 500 laterally encapsulates sidewalls of the device components 200 and 300 A, and the encapsulation layer 500 may extend laterally to sidewalls and top surfaces of the conductive pads 350 of the device component 300 A. The material of the encapsulation layer 500 is different form the material of the insulation layer 100 . In some embodiments, the material of the encapsulation layer 500 includes a molding compound, a molding underfill, a resin such as epoxy, a combination thereof, or the like. In alternative some embodiments, the material of encapsulation layer 500 may be a polymer such as polybenzoxazole (PBO), benzocyclobutene (BCB) based polymer, polyimide, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or combinations thereof, and may be formed, for example, by spin coating, lamination, CVD, or the like.

Referring to FIG. 3 D , a portion of the encapsulation layer 500 is removed, and the top surfaces of the conductive pads 350 of the device component 300 are exposed. Removal of the portion of the encapsulation layer 500 may be performed by a planarization process, such as chemical mechanical polish (CMP) or grinding. Thereafter, the current structure may be singulated by, for example, a sawing process, a laser ablation process, an etching process or the like. As a result, a singulated semiconductor device 600 A is formed.

The side of the semiconductor device 600 A where the conductive pads 250 , the passivation layer 260 , and the encapsulation layer 500 are located may be referred to as the terminal side 600 -FS of the semiconductor device 600 . The side opposite the terminal side 600 -FS where the conductive pads 350 and the encapsulation layer 500 are located may be referred to as the terminal side 600 -BS of the semiconductor device 600 A. On the terminal side 600 -FS of the semiconductor device 600 A, the top surface of the encapsulation layer 500 is coplanar with the top surface of the passivation layer 260 , and the top surface of the conductive pads 250 is lower than the top surface of the passivation layer 260 and the top surface of the encapsulation layer 500 . On the terminal side 600 -BS of the semiconductor device 600 A, the top surface of the encapsulation layer 500 is coplanar with the top surface of the conductive pads 350 .

In FIG. 1 E , after the semiconductor device 600 is placed inside and embedded in the cavity hole 118 (shown in FIG. 1 D ) of the cavity substrate 120 , the top surfaces of the passivation layer 260 and the encapsulation layer 500 are coplanar with the top surface of the conductive trace 116 F. The top surface of the conductive pads 350 and another top surface of the encapsulation layer 500 on the terminal side 600 -BS is lower than the top surface of the conductive trace 116 B, and thus form a step S therebetween in accordance with some embodiments, but it is not limited thereto. In alternative embodiments, the top surface of the conductive pads 350 and another top surface of the encapsulation layer 500 on the terminal side 600 -BS is coplanar with the top surface of the conductive trace 116 B.

FIGS. 1 F through 1 K illustrate the formation of a redistribution structure 180 F over the side 100 -FS of the insulation layer 100 and the terminal side 600 -FS of the semiconductor device 600 , and the formation of a redistribution structure 180 B over the side 100 -BS of the insulation layer 100 and the terminal side 600 -BS of the semiconductor device 600 after removal of the tape TP shown in FIG. 1 E . The redistribution structure 180 F and 180 B each includes a vertical stack of alternating layers of dielectric and conductive traces. Each layer of conductive traces is separated from vertically adjacent layers of conductive traces by a dielectric layer. The conductive traces extend through underlying dielectric layers to form conductive vias used to interconnect vertically adjacent conductive traces.

In FIG. 1 F , in some embodiments, a dielectric layer 122 is formed over the insulation layer 100 and filled in the through holes 114 (shown in FIG. 1 E ) of the insulation layer 100 and the space between the semiconductor device 600 and the adjacent insulation layer 100 .

In some embodiments, the dielectric layer 122 may also be formed of materials which are not photo-sensitive such as ajinomoto build-up film (ABF), silicon nitride, silicon oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like. In alternative embodiments, the dielectric layer 122 is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In alternative embodiments, the dielectric layer 122 is formed of or the like. The dielectric layer 122 may be formed by spin coating, lamination, chemical vapor deposition (CVD), the like, or a combination thereof.

In detail, the dielectric layer 122 may include dielectric layers 122 F and 122 B, and dielectric plugs 122 P. The dielectric layer 122 further includes a dielectric part 122 R in accordance with some embodiments.

The dielectric layers 122 F is located over the insulation layer 100 , the conductive traces 116 F, and the conductive pads 250 , the passivation layer 260 and the encapsulation layer 500 on the terminal side 600 -FS of the semiconductor device 600 . The dielectric layers 122 B is formed over the insulation layer 100 , the conductive traces 116 B, and over the conductive pads 350 and the encapsulation layer 500 on the terminal side 600 -FS of the semiconductor device 600 . In some embodiments, the thickness T 1 of the dielectric layer 122 F on the conductive pads 250 and the thickness T 2 of the dielectric layer 122 B on the conductive pads 350 may be non-uniform. For example, the thickness T 1 is less than the thickness T 2 . In alternative some embodiments, the thickness T 1 is equal to the thickness T 2 .

The dielectric plugs 122 P are embedded in the insulation layer 100 , and connected to the dielectric layer 122 F and the dielectric layer 122 B. The dielectric part 122 R is buried between the semiconductor device 600 and the adjacent insulation layer 100 , and connected to the dielectric layer 122 F and the dielectric layer 122 B. In some embodiments, the dielectric portion 122 R may have a ring shape or a semi-ring shape, but it is not limited thereto.

In FIG. 1 G , via holes 124 F and 126 F are formed in the dielectric layers 122 F to expose portions of the conductive trace 116 F in the region R 2 and portions of the conductive pads 250 in the region R 1 , respectively. Via holes 124 B and 126 B are formed in the dielectric layers 122 B to expose portions of the conductive trace 116 B in the region R 2 and portions of the conductive pads 350 in the region R 1 , respectively. In some embodiments in which the thickness T 1 is less than the thickness T 2 (shown in 1 F), the width W 1 of the via hole 126 F and the width W 2 of the via hole 126 B may be different. For example, the width W 1 is less than the width W 2 . In alternative some embodiments in which the thickness T 1 is equal to the thickness T 2 (shown in 1 F), the width W 1 is equal to the width W 2 .

In some embodiments, the via holes 124 F, 126 F, 124 B and 126 B are formed by laser drilling when the dielectric layer 122 is formed of a material which is not photo-sensitive such as ajinomoto build-up film (ABF). In alternative embodiments, the via holes 124 F, 126 F, 124 B and 126 B are formed by a patterning process by a suitable etching process (e.g., anisotropic reactive ion etching) through a patterned photoresist mask. In other some embodiments, the via holes 124 F, 126 F, 124 B and 126 B may be formed by exposing the dielectric layer 122 to light when the dielectric layer 122 is a photo-sensitive material.

FIGS. 1 H through 1 J show a metallization pattern M 11 formed on and extending through the patterned dielectric layer 122 F, and a metallization pattern M 21 formed on and extending through the patterned dielectric layer 122 B. In some embodiments the metallization patterns M 11 and M 21 formed by first forming a metallic seed layer 128 F on the dielectric layer 122 F, and a metallic seed layer 128 B on the dielectric layer 122 B. The metallic seed layers 128 F and 128 B may be referred to as seed layers 128 F and 128 B.

Referring to FIG. 1 H , in detail, the seed layer 128 F is formed over the dielectric layer 122 F, the sidewalls in the via holes 124 F and 126 F through the dielectric layer 122 F, and over exposed portions of the conductive trace 116 F on the bottom of the via hole 124 F and the conductive pads 250 on the bottom of the via hole 126 F. The seed layer 128 B is formed over the dielectric layer 122 B, the sidewalls in the via holes 124 B and 126 B through the dielectric layer 122 B, and over exposed portions of the conductive trace 116 B on the bottom of the via hole 124 B and the conductive pads 350 on the bottom of the via hole 126 B. The seed layers 128 F and 128 B each may include one or more layers of conductive materials, such as a copper layer or a composite layer of a titanium layer and a copper layer over the titanium layer. A layer of some other conductive material or a composite layer of several other conductive materials, or the like may also be used to form a seed layer. Any suitable deposition process (e.g., physical vapor deposition (PVD), CVD, or the like) may be used to form the seed layer.

In FIG. 1 H , patterned mask layers 130 F and 130 B, such as patterned photoresist masking layers, are then respectively formed over the seed layers 128 F and 128 B to expose portions of the seed layer 128 F and 128 B through openings 132 F and 132 B in the patterned mask layers 130 F and 130 B.

Referring to 1 I, a conductive layer 138 F may be formed on the exposed portions of the seed layers 128 F in the openings 132 F of the patterned mask layers 130 F. A conductive layer 138 B may be formed on the exposed portions of the seed layers 128 B in the openings 132 B of the patterned mask layers 130 B. The material used to form the conductive layers 138 F and 138 B each may include a metal such as copper, titanium, tungsten, aluminum, or the like, and may be deposited using a suitable deposition process, such as electroplating or electroless plating, or the like.

In FIG. 1 J , after the deposition process to form the conductive layers 138 F and 138 B is completed, the patterned mask layers 130 F and 130 B (shown in FIG. 1 I ) are stripped using an acceptable process such as ashing, or exposing to oxygen plasma, or the like. Stripping the photoresist pattern exposes portions of the seed layer over which the material deposited using the photoresist mask was not formed. These exposed portions of the seed layer 128 F and 128 B are removed using any acceptable chemical etching process (e.g., wet chemical etching or plasma etching, or the like). The remaining portions of the seed layer 128 F and the conductive layer 138 F are included in the metallization pattern M 11 . The remaining portions of the seed layer 128 B and the conductive layer 138 B are included in the metallization pattern M 21 .

The metallization pattern M 11 includes conductive traces t 11 and t 11 ′ formed along the top surface of the dielectric layer 122 F and conductive vias V 11 and V 11 ′ through the dielectric layer 122 F. The conductive vias V 11 are formed in the region R 2 and connect the conductive traces t 11 of metallization M 1 l to the conductive trace 116 F. The conductive vias V 11 ′ are formed in the region R 1 and connect the conductive traces t 11 ′ of the metallization M 11 to electrically and physically the conductive pads 250 of the semiconductor device 600 .

The metallization pattern M 21 includes conductive traces t 21 and t 21 ′ formed along the top surface of the dielectric layer 122 B and conductive vias V 21 and V 21 ′ through the dielectric layer 122 B. The conductive vias V 21 are formed in region R 2 and connect the conductive traces t 21 of the metallization M 21 to the conductive trace 116 B directly below the dielectric 122 B. The conductive vias V 21 ′ are formed in the region R 1 and connect the conductive traces t 21 ′ of the metallization M 21 to the conductive pads 350 of the semiconductor device 600 .

In some embodiments, the width W 11 ′ of the conductive via V 11 ′ may be different from the width W 21 ′ of the conductive via V 21 ′. For example, the width W 11 ′ is less than the widths W 21 ′. In alternative some embodiments, the width W 11 ′ of the conductive via V 11 ′ in the region R 1 may be different from the width W 11 of the conductive via V 11 in the region R 2 . The width W 21 ′ of the conductive via V 21 ′ in the region R 1 may be different from the width W 21 of the conductive via V 21 in the region R 2 . For example, the width W 11 ′ is greater than the width W 11 , and the width W 21 ′ is greater than the width W 21 .

The method of forming the patterned dielectric layers 122 F and 122 B (shown in FIG. 1 G ) and conductive traces t 11 , t 11 ′, t 21 , and t 21 ′ and conductive vias V 11 , V 11 ′, V 21 and V 21 ′ of metallization patterns M 11 and M 21 (shown in FIGS. 1 H through 1 I ) is described as an example. It should be appreciated thon the processes for forming the dielectric layers 122 F and 122 B and metallization patterns M 11 and M 21 may be varied based on the specifications of the design, e.g., the desired minimum dimensions of the patterns. For example, in some embodiments a damascene process (single or dual damascene process) may be utilized. The redistribution structures 180 F and 180 B each may be built up by vertically stacking more of dielectric and metallization patterns.

FIG. 1 K illustrates a patterned dielectric layer 142 F formed over the top surface of the dielectric layer 122 F and the metallization pattern M 11 , and a patterned dielectric layer 142 B formed over the top surface of the dielectric layer 122 B and the metallization pattern M 21 .

Also shown in FIG. 1 K is metallization patterns M 12 and M 22 . Metallization pattern M 12 includes conductive traces t 12 and t 12 ′ formed along the top surface of the dielectric layer 142 F, and conductive vias V 12 and V 12 ′ through the dielectric layer 142 F. The conductive vias V 12 and V 12 ′ of metallization pattern M 12 connect conductive traces t 12 and t 12 ′ of metallization pattern M 12 to the metal pattern directly below the dielectric 142 F (e.g., the metallization pattern M 11 ), respectively. Metallization pattern M 22 includes conductive traces t 22 and t 22 ′ formed along the top surface of the dielectric layer 142 B, and conductive vias V 22 and V 22 ′ through the dielectric layer 142 B. The conductive vias V 22 and V 22 ′ of metallization pattern M 22 connect conductive traces t 22 and t 22 ′ of metallization pattern M 22 to the metal pattern directly below the dielectric 142 B (e.g., the metallization pattern M 21 ), respectively.

In some embodiments, the width W 12 ′ of the conductive via V 12 ′ may be the same as or different from the width W 12 of the conductive via V 12 , and may be different from the width W 11 ′ of the conductive via V 11 ′. The width W 22 ′ of the conductive via V 22 ′ may be the same as or different from the width W 22 of the conductive via V 22 , and may be different from the width W 21 ′ of the conductive via V 21 ′. For example, the width W 12 ′ is equal to the widths W 12 , and less than the width W 11 ′; and the width W 22 ′ is equal to the widths W 22 , and less than the width W 21 ′.

In some embodiments, the width W 13 ′ of the conductive via V 13 ′ may be the same as or different from the width W 13 of the conductive via V 13 , and may be the same as or different from the width W 12 ′ of the conductive via V 12 ′. The width W 23 ′ of the conductive via V 23 ′ may be the same as or different from the width W 23 of the conductive via V 23 , and may be the same as or different from the width W 22 ′ of the conductive via V 22 ′. For example, the width W 13 ′ is equal to the widths W 13 and W 12 ′; and the width W 23 ′ is equal to the widths W 23 and W 22 ′.

FIG. 1 K also illustrates a patterned dielectric layer 162 F formed over a top surface of the dielectric layer 142 F and the metallization pattern M 12 , and a patterned dielectric layer 162 B formed over a top surface of the dielectric layer 142 B and the metallization pattern M 22 .

Also shown in FIG. 1 K is metallization patterns M 13 and M 23 . The metallization pattern M 13 includes conductive traces t 13 and t 13 ′ formed along the top surface of the dielectric layer 162 F, and conductive vias V 13 and V 13 ′ through the dielectric layer 162 F. The conductive vias V 13 and V 13 ′ of metallization pattern M 13 connect conductive traces t 13 and t 13 ′ of metallization pattern M 13 to the metal pattern directly below the dielectric 162 F (e.g., the metallization pattern M 12 ), respectively. The metallization pattern M 23 includes conductive traces t 23 and t 23 ′ formed along the top surface of the dielectric layer 162 B, and conductive vias V 23 and V 23 ′ through the dielectric layer 162 B. The conductive vias V 23 and V 23 ′ of the metallization pattern M 23 connect conductive traces t 23 and t 23 ′ of metallization pattern M 23 to the metal pattern directly below the dielectric 162 B (e.g., the metallization pattern M 22 ), respectively.

In some embodiments, one of the conductive vias V 13 ′ is directly stacked upon the conductive via V 12 ′, and the conductive via V 12 ′ is directly stacked on the conductive via V 11 ′ to form a stacked via SV 1 ′. Also, the conductive vias V 23 ′, V 22 ′ and V 21 ′ may be combined or not combined to a stacked via SV 2 ′. The conductive vias V 13 , V 12 and V 11 may be combined to a stacked via SV 1 or not. The conductive vias V 23 , V 22 and V 21 may be combined to a stacked via SV 2 or not.

The processes and materials used to form the dielectric layers 142 F, 142 B, 162 F and 162 B, and the metallization patterns M 12 , M 22 , M 13 and M 23 may be repeated to form the dielectric layers 122 F and 122 B and the metallization patterns M 11 and M 12 . More or fewer dielectric layers and metallization patterns may be formed in the redistribution structures 180 F and 180 B. If fewer dielectric layers and metallization patterns are to be formed, steps and process discussed above may be omitted. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed above may be repeated.

Referring now to FIG. 1 L , in some embodiments, a protective layers 182 F (e.g., solder resist) is formed over the metallization patterns M 13 and the dielectric layer 162 F to protect exposed areas of the dielectric layer 162 F from external damage. A protective layer 180 B (e.g., solder resist) is formed over the metallization patterns M 23 and the dielectric layer 162 B to protect exposed areas of the dielectric layer 162 B from external damage. In some embodiments, the protective layers 182 F and 182 B each is formed by depositing a layer of photosensitive material, exposing the layer with an optical pattern, and developing the exposed layer to form openings 184 F and 184 B, respectively. In other embodiments, the protective layers 182 F and 182 B each may be formed by depositing a non-photosensitive dielectric layer (e.g., silicon oxide, or silicon nitride, or the like), forming a patterned photoresist mask over the dielectric layer using photolithography techniques, and etching the dielectric to form the openings 184 F and 184 B using a suitable etching process (e.g., dry etching), respectively. Other processes and materials may also be used. The openings 184 F expose underlying portions of the conductive traces t 13 ′ that may be used as conductive pads P 13 ′ to which conductive connectors such as die connectors may be attached. The openings 184 B expose underlying portions of the conductive traces t 23 and t 23 ′ that may be used as conductive pads P 23 ′ to which external connectors can be attached.

In FIG. 1 M , conductive connectors 188 F are formed on the conductive pads P 13 ′ to form a package substrate 190 A in some embodiments. The conductive connectors 188 F may be ball grid array (BGA) connectors, solder balls, conductive pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors 188 F may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 188 F are formed by initially forming a layer of solder through such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors 188 F are conductive pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The conductive pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the conductive pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

FIG. 1 N illustrates the package substrate 190 A bonded to a component 191 using the conductive connectors 188 F, in accordance with some embodiments. The component 191 may be made of a semiconductor material, such as silicon, germanium, a compound semiconductor, or an alloy semiconductor; doped or undoped; or an active layer of a semiconductor-on-insulator (SOI) substrate. The component 191 may include a die, a package, a packaging substrate, an interposer, PCB, or the like. For example, the component 191 may be a die.

The component 191 may include active and passive device components (not shown). A wide variety of device components such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the integrated circuits included in package substrate 190 A or any other package connected to package substrate 190 A to form a multi-chip module. The device components may be formed using any suitable methods.

The component 191 may also include metallization layers and vias (not shown) and bond pads 193 over the metallization layers and vias. The metallization layers may be formed over the active and passive device components and are designed to connect the various device components to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). The electronic device components and the interconnect system may be formed using any suitable methods.

In some embodiments, the component 191 may be an integrated circuit, such as a memory integrated circuit, a PMIC, a digital logic integrated circuit, an RFIC, and the like. The conductive connectors 188 F electrically and/or physically couple the package substrate 190 A to the component 191 , including metallization layers in the component 191 .

In some embodiments, the conductive connectors 188 F are reflowed to attach the package substrate 190 A to the bond pads 193 of the component 191 . In some embodiments, the component 191 has conductive connectors 195 that may be attached to the conductive connectors 188 F of package substrate 190 A to electrically couple the component 191 to the package substrate 190 A. The conductive connectors 188 F may have an epoxy flux (not shown) formed thereon before they are reflowed with at least some of the epoxy portion of the epoxy flux remaining after the package substrate 190 A is attached to the component 191 . This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors 188 F. In some embodiments, an underfill (not shown) may be formed between the package substrate 190 A and the component 191 and surrounding the conductive connectors 188 F. The underfill may be formed by a capillary flow process after the package substrate 190 A is attached or may be formed by a suitable deposition method before the package substrate 190 A is attached.

Referring to FIG. 1 O , in some embodiments, the package substrate 190 A is bonded to additional component 196 using conductive connectors 188 B formed on conductive pads P 23 ′ of the conductive trace t 23 ′ located on the side 100 -BS and the terminal sides 600 -BF. The additional component 196 may be coupled electrically to the package substrate 190 A by attaching bond pads 198 of the component 196 to the conductive connectors 188 B of the package substrate 190 A. in some embodiments, the additional component 196 has conductive connectors (not shown) that may be attached to the conductive connectors 188 B of the package substrate 190 A to electrically couple the additional component 196 .

The capacitor 210 and the capacitor 310 of the semiconductor device 600 may be coupled in parallel or in series through the redistribution structures 180 F and 180 B, and/or the metallization layers and the vias of the component 191 . In some embodiments in which the capacitor 210 and the capacitor 310 are coupled in parallel, the conductive pads 250 s and 350 s are coupled to a first electrical terminal such as a negative supply voltage (V SS ), and the conductive pads 250 d and 350 d are coupled to a second electrical terminal such as a positive supply voltage (V DD ) through the redistribution structures 180 F and 180 B, the UBMs 186 F, the conductive connectors 188 F and the bond pads 193 .

The conductive pads 250 s and 350 s are electrically connected each other in the package substrate 190 A through the redistribution structures 180 F and 180 B, and then coupled to a first electrical terminal such as a negative supply voltage (V SS ), while the conductive pads 250 d and 350 d are connected each other package substrate 190 A through the redistribution structures 180 F and 180 B, and then coupled to a second electrical terminal such as a positive supply voltage (V DD ) in accordance with some embodiments.

The conductive pads 250 s and 350 s are electrically isolated each other in the package substrate 190 A, but connected each other through the metallization layers and the vias of the component 191 so as to couple to a first electrical terminal such as anegative supply voltage (V SS ), while the conductive pads 250 d and 350 d are isolated each other in the package substrate 190 A, but connected each other through the metallization layers and the vias of the component 191 so as to couple to a second electrical terminal such as a positive supply voltage (V DD ) in accordance with alternative some embodiments.

The semiconductor device 600 may be configured by various device components. In alternative some embodiments, the semiconductor device 600 may be the semiconductor device 600 B shown in FIG. 5 A . The more detailed structure of the device semiconductor device 600 B is shown in FIG. 5 B .

Referring to FIGS. 5 A and 5 B , the semiconductor device 600 B may include device components 200 and 300 B. The device component 200 is bonded to the device component 300 B through an adhesive 400 in back-to-back manner. The semiconductor device 600 B is free of the encapsulation layer 500 shown in FIG. 2 D , and thus the sidewalls of the device components 200 and 300 B, and the adhesive 400 are exposed.

In FIGS. 5 A and 5 B , the device component 200 may be a passive component, and may be similar to the device component 200 shown in FIG. 4 A . The device component 300 A may be a passive component, and may be similar to the device component 200 shown in FIG. 4 A . In some embodiments, the device component 300 B includes a semiconductor substrate 302 , a capacitor 310 , an interconnect structure 330 , conductive pads 350 , and a passivation layer 360 . The semiconductor substrate 302 , the capacitor 310 , the interconnect structure 330 , the conductive pads 350 , and the passivation layer 360 of the device component 300 B may be similar to corresponding components of the device component 200 . The passivation layer 360 is formed on a dielectric layer of the interconnect structure 330 and on portions of the conductive pads 350 . The passivation layer 360 may be or comprise, for example, silicon oxide, silicon nitride, polyimide, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, the top area A 3 of the conductive pads 350 each is greater than the top area A 2 of the conductive pad 250 as shown in FIG. 4 B , but it is not limited thereto.

Referring to FIG. 5 C , there is shown a package substrate 190 B boned to a component 191 using conductive connectors 188 F, and boned to a component 196 using conductive connectors 188 b in accordance with some embodiments. The package substrate 190 B is similar to the package substrate 190 A, but the semiconductor device 600 A is replaced by the semiconductor device 600 B.

In FIG. 5 C , the semiconductor device 600 B is encapsulated by the dielectric layer 122 R, and the sidewalls of the device components 200 and 300 B, and the adhesive 400 of the semiconductor device 600 B are in physically contact with the dielectric layer 122 R.

The semiconductor device 600 may be varied based on the specifications of the design. The semiconductor device 600 may configured by two tiers or more tiers (not shown). In some embodiments, the semiconductor device 600 is configured by two tiers including one upper device component (such as the device component 200 shown in FIGS. 3 D and 5 A ) and one lower device component (such as the device component 300 shown in FIGS. 3 D and 5 A ) in accordance with some embodiments. The semiconductor device 600 may be a semiconductor device 600 C which is configured by two or more upper device components (such as the device component 200 1 and 200 2 ) and one lower device component (such as the device component 300 1 ), as shown in FIG. 6 A . The semiconductor device 600 may be a semiconductor device 600 D which is configured by two or more upper device components (such as the device component 200 1 and 200 2 ) and two or more lower device component (such as the device component 300 1 and 300 2 ) in accordance with alternative some embodiments, as shown in FIG. 6 B . The device components 200 1 , 200 2 , 300 1 and 300 2 may have a same size or different sizes, and a same shape or different shapes. The device components 200 1 and 200 2 may be separated by an encapsulation layer 500 1 , and the components 300 1 and 300 2 may be separated by another encapsulation layer 500 2 . The device components 200 1 , 200 2 , 300 1 and 300 2 , and the adhesive 400 may be encapsulated by an encapsulation layer 500 or not. The device components 200 1 , 200 2 , 300 1 and 300 2 each may be a passive component or an active component. The device components 200 1 , 200 2 , 300 1 and 300 2 are passive components having a same type or different types. The device components 200 1 and 200 2 may be similar to or different from the device component 200 , while the components 300 1 and 300 2 may be similar to or different from the device component 300 .

Embodiments such as those discussed herein provide greater integration capabilities by allowing the semiconductor device having double side electrical terminals embedded in a package substrate to couple to a component attached on the package substrate through redistribution structures of the package substrate. Embodiments such as those discussed herein also provide a better via/dielectric design for preventing the reliability issue.

In accordance with some embodiment, a package substrate is provided. The package substrate comprises a substrate having a cavity hole therein, and a semiconductor device in the cavity hole. The semiconductor device has first terminal side and a second terminal side opposite to the first terminal side. The package substrate further includes a first redistribution structure on the first terminal side of the cavity substrate to electrically couple to a first pad and a second pad on the first terminal side of the semiconductor device; and a second redistribution structure on the second side of the cavity substrate to electrically couple to a third pad and fourth pad on the second terminal side of the semiconductor device.

In accordance with another embodiment, a package is provided. The package comprises a component bonded to and electrically coupled to a package substrate, wherein the package substrate comprises: a cavity substrate comprising a cavity hole therein; a semiconductor device in the cavity hole, wherein the semiconductor device has a first device component and a second device component bonded through a back-to-back bonding, the first device component comprising a first capacitor and the second device component comprising a second capacitor; a first redistribution structure on a first side of the cavity substrate to electrically couple to a first electrode and a second electrode of the first capacitor; and a second redistribution structure on the second side of the cavity substrate to electrically couple to a third electrode and a fourth electrode of the second capacitor. The first pad and the third pad are coupled to a first terminal, and the second pad and fourth pad are couple to a second terminal through the first redistribution structure and the second redistribution structure.

In accordance with yet another embodiments, a method of manufacturing a semiconductor device is provided. The method comprising: providing a semiconductor device; placing the semiconductor device in a cavity hole of a cavity substrate, wherein the semiconductor device has first terminal side and a second terminal side opposite to the first terminal side; forming a dielectric layer along sidewalls, the first terminal side and the second terminal side of the semiconductor device, and the cavity hole, a first side and a second side opposite to the first side of the cavity substrate; forming a first redistribution structure on the first side of the cavity substrate to electrically couple to the first terminal side of the semiconductor device; and forming a second redistribution structure on the second side of the cavity substrate to electrically couple to the second terminal side of the semiconductor device.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate thon they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and thon they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.