Inverter Circuit Based on a Heric Topology, Inverter, and Photovoltaic Power System

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Application No. PCT/CN2020/091982, filed on May 25, 2020, which claims priority to Chinese Patent Application No. 201910469584.X, filed on May 31, 2019. The disclosures of the aforementioned applications are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

This application relates to the field of voltage conversion technologies, and in particular, to an inverter circuit, an inverter, and a photovoltaic power system.

BACKGROUND

As a type of renewable clean energy, the photovoltaic power industry has been developing rapidly in recent years. A photovoltaic power system includes a plurality of components, such as a photovoltaic module, an inverter, a transformer, and a cable. The inverter is a core component for energy conversion of the photovoltaic power system, and converts a direct current output by the photovoltaic module into an alternating current available for a grid. In addition, inverters are also widely used in other systems that need to convert a direct current into an alternating current.

HERIC topologies generated based on a highly efficient and reliable inverter concept (HERIC) are widely used in photovoltaic inverter products thanks to their low cost. As shown in FIG. 1 , in the conventional technology, a HERIC topology includes a first longitudinal bridge and a second longitudinal bridge. Two ends of the first longitudinal bridge are respectively connected to a first switching transistor and a second switching transistor. Two ends of the second longitudinal bridge are respectively connected to a third switching transistor and a fourth switching transistor. In an upper half cycle of inverter output, the first switching transistor and the fourth switching transistor are turned on. In a freewheeling phase, the first switching transistor and the fourth switching transistor are simultaneously turned off. In practice, turn-off speeds of the first switching transistor and the fourth switching transistor cannot maintain complete consistency. For example, a turn-off speed of the fourth switching transistor is faster than that of the first switching transistor. In this case, a voltage on a bus, the first longitudinal bridge, and the second longitudinal bridge increases. After the first switching transistor is turned off, the voltage falls back. A resonance phenomenon occurs in this process. Consequently, this impacts the electromagnetic compatibility (EMC) for a device and a system, which need to work normally in their electromagnetic environment without causing unacceptable electromagnetic interference to anything in the environment. As a result, conduction and radiation test results of the EMC exceed thresholds.

Therefore, the HERIC topology in the conventional technology still needs to be improved.

SUMMARY

Embodiments of this application provide an inverter circuit, an inverter, and a photovoltaic power system. A solution in which a capacitor is bridge-connected to a bus at a location of a connection point between a longitudinal bridge and a transverse bridge in a HERIC topology can suppress resonance caused by different turn-off speeds of switching transistors when a power circuit works normally.

A first aspect of this application provides an inverter circuit, including a bus, a first longitudinal bridge, a second longitudinal bridge, a transverse bridge, and a filter. A capacitor group is disposed on the bus, the bus is connected in parallel to a direct current power supply, and the capacitor group includes a first capacitor and a second capacitor that are disposed in series. The first capacitor is disposed on a side of the bus and is connected to a positive electrode of the direct current power supply, the second capacitor is disposed on a side of the bus and is connected to a negative electrode of the direct current power supply, and the first capacitor and the second capacitor are configured to be charged by the direct current power supply, to provide a direct current voltage to the first longitudinal bridge, the second longitudinal bridge, and the transverse bridge. The bus is connected in parallel to the first longitudinal bridge, the first longitudinal bridge is connected in parallel to the second longitudinal bridge, the first longitudinal bridge includes a first switching transistor and a second switching transistor that are connected in series, the second longitudinal bridge includes a third switching transistor and a fourth switching transistor that are connected in series, and two ends of the transverse bridge are respectively connected to the first longitudinal bridge and the second longitudinal bridge. The filter is connected in parallel to the transverse bridge, the filter is connected to an alternating current power grid, and the transverse bridge is configured to supply power to the alternating current power grid by using the filter. The inverter circuit further includes: a third capacitor, where the third capacitor is connected between the bus and the first longitudinal bridge, and a connection point between the third capacitor and the first longitudinal bridge is located between the first switching transistor and the second switching transistor; and a fourth capacitor, where the fourth capacitor is connected between the bus and the second longitudinal bridge, and a connection point between the fourth capacitor and the second longitudinal bridge is located between the third switching transistor and the fourth switching transistor. The first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor may be MOS transistors or IGBT devices.

In this embodiment, based on an existing inverter circuit in a HERIC topology, the third capacitor and the fourth capacitor are respectively bridge-connected between the first longitudinal bridge and the bus and between the second longitudinal bridge and the bus, so that in a process in which the first switching transistor and the fourth switching transistor are turned off, the third capacitor can stabilize a voltage difference generated by different turn-off speeds of the two switching transistors. This prevents a resonance phenomenon, and effectively avoids an EMC problem caused by the resonance phenomenon. Similarly, in a process in which the second switching transistor and the third switching transistor are turned off, the fourth capacitor can stabilize a voltage difference generated by different turn-off speeds of the two switching transistors. This stabilizes a voltage in a negative half cycle of converting a direct current into an alternating current, and prevents the resonance phenomenon.

With reference to the first aspect, in a first possible implementation, at least one inductor is disposed in series on a line on which the third capacitor is located, and/or at least one inductor is disposed in series on a line on which the fourth capacitor is located.

In this embodiment, the at least one inductor connected in series to the third capacitor and/or the at least one inductor connected in series to the fourth capacitor can protect the third capacitor and/or the fourth capacitor in a charging and discharging process.

With reference to the first aspect, in a second possible implementation, at least one resistor is disposed in series on a line on which the third capacitor is located, and/or at least one resistor is disposed in series on a line on which the fourth capacitor is located.

In this embodiment, the at least one resistor connected in series to the third capacitor and/or the at least one resistor connected in series to the fourth capacitor can protect the third capacitor and/or the fourth capacitor by charging and discharging a current in a charging and discharging process.

With reference to the first aspect, in a third possible implementation, at least one inductor and at least one resistor are disposed in series on a line on which the third capacitor is located, and/or at least one inductor and at least one resistor are disposed in series on a line on which the fourth capacitor is located.

In this embodiment, the at least one resistor and the at least one inductor that are connected in series to the third capacitor and/or the at least one resistor and the at least one inductor that are connected in series to the fourth capacitor can work together to protect the third capacitor and/or the fourth capacitor in a charging and discharging process.

With reference to the first aspect and the first to the third possible implementations of the first aspect, in a fourth possible implementation, both a connection point between the line on which the third capacitor is located and the bus and a connection point between the line on which the fourth capacitor is located and the bus are disposed between the first capacitor and the second capacitor.

In this embodiment, both the third capacitor and the fourth capacitor are bridge-connected between the first capacitor and the second capacitor on the bus, so that the first capacitor and the third capacitor form a parallel circuit, and the second capacitor and the fourth capacitor form a parallel circuit. In this way, when the first switching transistor and the fourth switching transistor are turned on, a voltage of the third capacitor is equal to a voltage of the first capacitor, stabilizing a voltage on the bus, the first longitudinal bridge, and the second longitudinal bridge in a positive half cycle of inverter output. When the second switching transistor and the third switching transistor are turned on, a voltage of the fourth capacitor is equal to a voltage of the second capacitor, stabilizing a voltage on the bus, the first longitudinal bridge, and the second longitudinal bridge in a negative half cycle of inverter output. This prevents resonance. Further, when the first switching transistor, the second switching transistor, the third switching transistor, and the fourth switching transistor are all turned off, the voltage of the first capacitor causes a circuit to sequentially pass through the third capacitor, a first inductor, the alternating current power grid, a second inductor, the fourth capacitor, and the second capacitor. In this case, the third capacitor and the fourth capacitor are charged with ½ bus voltage. When the first switching transistor and the fourth switching transistor are turned on, or the second switching transistor and the third switching transistor are turned on, a voltage discharged by the third capacitor or the fourth capacitor and a voltage discharged by the first capacitor or the second capacitor are equal, and both are ½ bus voltage. Therefore, the circuit loss is relatively small. This not only can effectively prevent resonance caused by different turn-on/turn-off speeds, but also can effectively reduce circuit loss.

With reference to the first aspect and the first to the third possible implementations of the first aspect, in a fifth possible implementation, neither a connection point between the line on which the third capacitor is located and the bus nor a connection point between the line on which the fourth capacitor is located and the bus is disposed between the first capacitor and the second capacitor. Specifically, the connection point between the line on which the third capacitor is located and the bus and the connection point between the line on which the fourth capacitor is located and the bus both are disposed between the first capacitor and the direct current power supply. Alternatively, the connection point between the line on which the third capacitor is located and the bus and the connection point between the line on which the fourth capacitor is located and the bus both are disposed between the second capacitor and the direct current power supply. Alternatively, the connection point between the line on which the third capacitor is located and the bus is disposed between the first capacitor and the direct current power supply, and the connection point between the line on which the fourth capacitor is located and the bus is disposed between the second capacitor and the direct current power supply. Alternatively, the connection point between the line on which the third capacitor is located and the bus is disposed between the second capacitor and the direct current power supply, and the connection point between the line on which the fourth capacitor is located and the bus is disposed between the first capacitor and the direct current power supply.

In this embodiment, neither a bridge-connection point of the third capacitor nor a bridge-connection point of the fourth capacitor is disposed between the first capacitor and the second capacitor. In this case, at a moment at which the first switching transistor and the fourth switching transistor are turned off, the third capacitor can absorb a voltage fluctuation. This stabilizes the circuit. Similarly, at a moment at which the second switching transistor and the third switching transistor are turned off, the fourth capacitor can absorb a voltage fluctuation. This stabilizes the circuit. Therefore, resonance caused by different turn-on/turn-off speeds can be effectively prevented.

With reference to the first aspect and the first to the third possible implementations of the first aspect, in a sixth possible implementation, only one of a connection point between the line on which the third capacitor is located and the bus and a connection point between the line on which the fourth capacitor is located and the bus is disposed between the first capacitor and the second capacitor. Specifically, the connection point between the third capacitor and the bus may be disposed between the first capacitor and the second capacitor, and the connection point between the line on which the fourth capacitor is located and the bus may be disposed between the first capacitor and the direct current power supply or between the second capacitor and the direct current power supply. Alternatively, the connection point between the fourth capacitor and the bus may be disposed between the first capacitor and the second capacitor, and the connection point between the line on which the third capacitor is located and the bus may be disposed between the first capacitor and the direct current power supply or between the second capacitor and the direct current power supply.

In this embodiment, one of the third capacitor or the fourth capacitor is bridge-connected between the first capacitor and the second capacitor, and the other capacitor is bridge-connected between the capacitor group and the direct current power supply, so that the third capacitor can absorb a voltage fluctuation at a moment at which the first switching transistor and the fourth switching transistor are turned off. This stabilizes the circuit. Similarly, the fourth capacitor can absorb a voltage fluctuation at a moment at which the second switching transistor and the third switching transistor are turned off. This can effectively prevent resonance caused by different turn-on/turn-off speeds, but causes a specific circuit loss.

With reference to the first aspect and the first to the sixth possible implementations of the first aspect, in a seventh possible implementation, the filter includes the first inductor and the second inductor, and the transverse bridge includes a freewheeling switch group. The first inductor is connected between the first longitudinal bridge and the alternating current power grid, the second inductor is connected between the alternating current power grid and the second longitudinal bridge, and the freewheeling switch group is connected in parallel between the first inductor and the second inductor.

In this embodiment, optionally, the inverter circuit further includes a fifth capacitor. The fifth capacitor is connected in parallel between the first inductor and the second inductor, and the fifth capacitor is configured to stabilize a voltage of the filter.

With reference to the seventh possible implementation of the first aspect, in an eighth possible implementation, the freewheeling switch group includes a fifth switching transistor and a sixth switching transistor that are connected in series. The fifth switching transistor and the sixth switching transistor may be MOS transistors or IGBT devices.

In this embodiment, the fifth switching transistor and the sixth switching transistor are controlled to control a circuit from a starting phase to a freewheeling phase, so that the first inductor and the second inductor that are excited are connected to the alternating current power grid.

It can be learned from the foregoing technical solutions that this embodiment of this application has the following advantages:

In the inverter circuit provided in this embodiment of this application, the capacitors may be bridge-connected to the bus on the first longitudinal bridge and the second longitudinal bridge. In this way, in a working process of the HERIC topology, when the first switching transistor and the fourth switching transistor are turned off or the second switching transistor and the third switching transistor are turned off, the capacitors bridge-connected to the bus can stabilize a voltage fluctuation caused by different turn-off speeds of the switching transistors, and suppress the resonance caused by different turn-on/turn-off speeds of the switching transistors when a power circuit works normally. This resolves an EMC-related problem caused by the resonance.

A second aspect of this application provides an inverter, including a control unit and an inverter power unit, where the control unit is configured to control work of the inverter power unit, and the inverter power unit includes the inverter circuit according to the first aspect or any possible implementations of the first aspect.

It can be learned from the foregoing technical solutions that this embodiment of this application has the following advantages:

In the inverter circuit of the inverter provided in this embodiment of this application, capacitors may be bridge-connected to the bus on the first longitudinal bridge and the second longitudinal bridge. In this way, in a working process of the HERIC topology, when the first switching transistor and the fourth switching transistor are turned off or the second switching transistor and the third switching transistor are turned off, the capacitors bridge-connected to the bus can stabilize a voltage fluctuation caused by different turn-off speeds of the switching transistors, and suppress resonance caused by different turn-on/turn-off speeds of the switching transistors when a power circuit works normally. This resolves an EMC-related problem caused by the resonance.

A third aspect of this application provides a photovoltaic power system, including a photovoltaic panel, an inverter, and an alternating current power grid, where the photovoltaic panel is connected to the inverter, and the inverter is connected to the alternating current power grid; the photovoltaic panel is configured to convert light energy into a direct current; the inverter includes the inverter circuit according to the first aspect or any possible implementations of the first aspect, and is configured to convert the direct current into an alternating current; the alternating current power grid is configured to transmit the alternating current.

It can be learned from the foregoing technical solutions that this embodiment of this application has the following advantages:

In the photovoltaic power system provided in this embodiment of this application, the inverter implements conversion from the direct current into the alternating current. In the inverter circuit of the inverter, capacitors may be bridge-connected to the bus on the first longitudinal bridge and the second longitudinal bridge. In this way, in a working process of the HERIC topology, when the first switching transistor and the fourth switching transistor are turned off or the second switching transistor and the third switching transistor are turned off, the capacitors bridge-connected to the bus can stabilize a voltage fluctuation caused by different turn-off speeds of the switching transistors, and suppress resonance caused by different turn-on/turn-off speeds of the switching transistors when a power circuit works normally. This resolves an EMC-related problem caused by the resonance.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a HERIC topology structure of an inverter circuit in the conventional technology;

FIG. 2 is a circuit diagram of an implementation of an inverter circuit according to an embodiment of this application;

FIG. 3 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 4 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 5 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 6 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 7 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 8 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 9 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 10 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 11 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 12 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 13 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application;

FIG. 14 is a schematic structural diagram of an inverter according to an embodiment of this application;

FIG. 15 is a schematic structural diagram of a photovoltaic power system according to an embodiment of this application;

FIG. 16 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application; and

FIG. 17 is a circuit diagram of another implementation of an inverter circuit according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

The following describes the embodiments of this application with reference to the accompanying drawings. It is clear that the described embodiments are merely some but not all of the embodiments of this application. A person of ordinary skill in the art may learn that the technical solutions provided in the embodiments of this application are also applicable to a similar technical problem as technology evolves and new scenarios emerge.

In the specification, claims, and accompanying drawings of this application, the terms “first”, “second”, and so on are intended to distinguish between similar objects, but do not necessarily indicate a specific order or sequence. It should be understood that the data termed in such a way are interchangeable in proper circumstances so that the embodiments described herein can be implemented in an order other than the order illustrated or described herein. Moreover, the terms “include”, “comprise” and any other variants mean to cover the non-exclusive inclusion, for example, a process, method, system, product, or device that includes a list of steps or units is not necessarily limited to those units, but may include other units not expressly listed or inherent to such a process, method, system, product, or device.

Inverters are apparatuses that convert a direct current into an alternating current, and have been rapidly developing in recent years along with the development of photovoltaic power industry. A photovoltaic power system includes a plurality of components, such as a photovoltaic module, an inverter, a transformer, and a cable. The inverter is a core component for energy conversion of the photovoltaic power system, and converts a direct current output by the photovoltaic module into an alternating current available for a grid. In addition, inverters are also widely used in other systems that need to convert a direct current into an alternating current.

HERIC topologies generated based on a highly efficient and reliable inverter concept (HERIC) are widely used in photovoltaic inverter products thanks to its low costs. As shown in FIG. 1 , in the conventional technology, a HERIC topology includes a first longitudinal bridge 10 and a second longitudinal bridge 20 . Two ends of the first longitudinal bridge 10 are respectively connected to a first switching transistor T 1 and a second switching transistor T 2 . Two ends of the second longitudinal bridge 20 are respectively connected to a third switching transistor T 3 and a fourth switching transistor T 4 . In an upper half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned on. When a freewheeling phase is entered, the first switching transistor T 1 and the fourth switching transistor T 4 are simultaneously turned off. In practice, turn-off speeds of the first switching transistor T 1 and the fourth switching transistor T 4 cannot maintain complete consistency. For example, a turn-off speed of the fourth switching transistor T 4 is faster than that of the first switching transistor T 1 . In this case, a voltage on a bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 increases. After the first switching transistor T 1 is turned off, the voltage falls back. A resonance phenomenon occurs in this process. Consequently, this impacts the electromagnetic compatibility (EMC) for a device and a system, which need to work normally in their electromagnetic environment without causing unacceptable electromagnetic interference to anything in the environment. As a result, conduction and radiation test results of the EMC exceed thresholds.

Therefore, to resolve the foregoing problem, an embodiment of this application provides an inverter circuit. A solution in which a capacitor is bridge-connected to a bus at a location of a connection point between a longitudinal bridge and a transverse bridge in a HERIC topology can suppress resonance caused by different turn-off speeds of switching transistors when a power circuit works normally.

It should be noted that the inverter circuit and the inverter provided in the embodiments of this application may be a photovoltaic inverter used in a photovoltaic power system, or may be used in another circuit or apparatus that needs to convert a direct current into an alternating current. This is not limited in the embodiments of this application. For ease of understanding, a photovoltaic inverter is used as an example in this embodiment of this application to describe in detail the inverter provided in this embodiment of this application.

The following describes in detail the inverter circuit provided in this embodiment of this application with reference to the accompanying drawings.

As shown in FIG. 1 , based on the HERIC topology in the conventional technology, the inverter circuit provided in this embodiment of this application specifically includes the bus, the first longitudinal bridge 10 , the second longitudinal bridge 20 , a transverse bridge, and a filter. A capacitor group is disposed on the bus, the bus is connected in parallel to a direct current power supply, and the capacitor group includes a first capacitor Cs 1 and a second capacitor Cs 2 that are disposed in series. The first capacitor Cs 1 is connected to a positive electrode DC+ of the direct current power supply, the second capacitor Cs 2 is connected to a negative electrode DC− of the direct current power supply, and the first capacitor Cs 1 and the second capacitor Cs 2 are configured to be charged by the direct current power supply to provide a direct current voltage to the first longitudinal bridge 10 , the second longitudinal bridge 20 , and the transverse bridge.

The bus is connected in parallel to the first longitudinal bridge 10 , the first longitudinal bridge 10 is connected in parallel to the second longitudinal bridge 20 , the first longitudinal bridge 10 includes a first switching transistor T 1 and a second switching transistor T 2 that are connected in series, and a line that connects the first switching transistor T 1 and the second switching transistor T 2 . The second longitudinal bridge 20 includes a third switching transistor T 3 and a fourth switching transistor T 4 that are connected in series, and a line that connects the third switching transistor T 3 and the fourth switching transistor T 4 . Two ends of the transverse bridge are respectively connected to the first longitudinal bridge 10 and the second longitudinal bridge 20 . Specifically, the transverse bridge specifically includes a circuit structure that sequentially passes through a connection point A, a connection point B, a connection point C, and a connection point D. The connection point A is a connection point between the transverse bridge and a first bridge arm 10 , and the connection point D is a connection point between the transverse bridge and a second bridge arm 20 .

It should be noted that the first longitudinal bridge 10 and the second longitudinal bridge 20 are not limited to the foregoing structure, and may also be a related topology structure variant. For example, the first longitudinal bridge 10 or the second longitudinal bridge 20 have more than two switching transistors. The transverse bridge is also not limited to the foregoing structure, but may also be a related topology structure variant such as a topology structure including a part of the structure of the transverse bridge. This is not limited in this embodiment of this application.

Further, a source of the first switching transistor T 1 is connected to a drain of the second switching transistor T 2 through a wire, a drain of the first switching transistor T 1 is connected to the first capacitor Cs 1 through a wire, and a source of the second switching transistor T 2 is connected to the second capacitor Cs 2 through a wire.

Specifically, the first switching transistor T 1 , the second switching transistor T 2 , the third switching transistor T 3 , and the fourth switching transistor T 4 may be MOS transistors, IGBT devices, or other semiconductor devices that have a switching function. This is not limited in this embodiment of this application. In an optional implementation, when the first switching transistor T 1 , the second switching transistor T 2 , the third switching transistor T 3 , and the fourth switching transistor T 4 are MOS transistors, a diode and a capacitor may be connected in parallel to each switching transistor. Specifically, a capacitor C 1 , a capacitor C 2 , a capacitor C 3 , and a capacitor C 4 may be respectively connected in parallel to the first switching transistor T 1 , the second switching transistor T 2 , the third switching transistor T 3 , and the fourth switching transistor T 4 . When the switching transistors are MOS transistors, the MOS transistors may be gallium nitride MOS transistors or silicon carbide MOS transistors.

It should be noted that, in an actual physical implementation process of the first capacitor Cs 1 and the second capacitor Cs 2 , the first capacitor Cs 1 or the second capacitor Cs 2 may be implemented by using one capacitor, or may be implemented by using a plurality of capacitors. This is not limited in this embodiment of this application.

The filter is connected in parallel to the transverse bridge, the filter is connected to an alternating current power grid AC, and the transverse bridge is configured to supply power to the alternating current power grid AC by using the filter. The filter specifically includes a circuit structure that sequentially passes through a connection point B, a connection point E, a connection point F, and a connection point C. The filter is connected in parallel to the transverse bridge through the connection point B and the connection point C, and the filter is connected to the alternating current power grid AC through the connection point E and the connection point F.

Specifically, the filter includes a first inductor L 1 and a second inductor L 2 , and the transverse bridge includes a freewheeling switch group.

The first inductor L 1 is connected between the first longitudinal bridge 10 and the alternating current power grid AC, the second inductor L 2 is connected between the alternating current power grid AC and the second longitudinal bridge 20 , and the freewheeling switch group is connected in parallel between the first inductor L 1 and the second inductor L 2 . The first inductor L 1 is connected to the transverse bridge through the connection point B, the second inductor L 2 is connected to the transverse bridge through the connection point C, and the first inductor L 1 and the second inductor L 2 are respectively connected to the alternating current power grid AC through the connection point E and the connection point F.

The first inductor L 1 and the second inductor L 2 are excited by the direct current power supply when the first switching transistor T 1 and the fourth switching transistor T 4 are turned on or the second switching transistor T 2 and the third switching transistor T 3 are turned on.

The freewheeling switch group is turned on when the first switching transistor T 1 and the fourth switching transistor T 4 are turned off or the second switching transistor T 2 and the third switching transistor T 3 are turned off, so that the first inductor L 1 and the second inductor L 2 supply power to the output.

Further, the freewheeling switch group includes a fifth switching transistor T 5 and a sixth switching transistor T 6 that are connected in series.

The fifth switching transistor T 5 is configured to maintain a turned-on state.

The sixth switching transistor T 6 is turned on when the first switching transistor T 1 and the fourth switching transistor T 4 are turned off or the second switching transistor T 2 and the third switching transistor T 3 are turned off, so that the first inductor L 1 and the second inductor L 2 supply power to the output.

Further, the inverter further includes a fifth capacitor Cx 1 . The fifth capacitor Cx 1 is connected in parallel between the first inductor L 1 and the second inductor L 2 through the connection point E and the connection point F, and the fifth capacitor Cx 1 is configured to stabilize a voltage of the transverse bridge, so that the transverse bridge outputs a stable voltage to the alternating current power grid AC.

Optionally, the fifth switching transistor T 5 and the sixth switching transistor T 6 are MOS transistors, and the MOS transistors may be MOS transistors, IGBT devices, or other semiconductor devices that have a switching function. This is not limited in this embodiment of this application. In an optional implementation, when the fifth switching transistor T 5 and the sixth switching transistor T 6 are MOS transistors, a diode and a capacitor C 5 may be connected in parallel to the fifth switching transistor T 5 , and a diode and a capacitor C 6 may be connected in parallel to the sixth switching transistor T 6 . The MOS transistors may be gallium nitride MOS transistors or silicon carbide MOS transistors.

It should be noted that a topology structure on which the inverter circuit in this embodiment of this application is based may be a related topology structure variant of the HERIC topology in addition to the foregoing HERIC topology. This is not limited in this embodiment of this application.

When specifically working, the direct current power supply charges the first capacitor Cs 1 and the second capacitor Cs 2 on the bus because the bus is connected in parallel to the direct current power supply.

In a starting phase of a positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned on. In this case, the first capacitor Cs 1 provides the voltage through a positive electrode DC+ of the bus. A current sequentially passes through the first switching transistor T 1 , the first inductor L 1 , the second inductor L 2 , and the fourth switching transistor T 4 , and finally flows to a negative electrode DC− of the bus, to complete a loop. In this process, the first inductor L 1 and the second inductor L 2 are charged to excite the first inductor L 1 and the second inductor L 2 .

In a freewheeling phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned off, and the freewheeling switch group is turned on. A specific turn-on implementation of the freewheeling switch group is as follows: The fifth switching transistor T 5 always maintains a turn-on state; when the freewheeling switch group needs to change from turn-off to turn-on, the sixth switching transistor T 6 changes from turn-off to turn-on, so as to turn on the freewheeling switch group. The first inductor L 1 and the second inductor L 2 discharge, and a current flows in a loop among the alternating current power grid AC, the first inductor L 1 , the freewheeling switch group, and the second inductor L 2 . In this way, in the freewheeling phase, the first inductor L 1 and the second inductor L 2 continuously charge the alternating current power grid AC, so that the transverse bridge supplies power to the output in a positive half cycle of the alternating current.

In a starting phase of a negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned on. In this case, the second capacitor Cs 2 provides a voltage through the negative electrode DC− of the bus. A current sequentially passes through the second switching transistor T 2 , the first inductor L 1 , the second inductor L 2 , and the third switching transistor T 3 , and finally flows to the positive electrode DC+ of the bus, to complete a loop. In this process, the first inductor L 1 and the second inductor L 2 are charged to excite the first inductor L 1 and the second inductor L 2 .

In a freewheeling phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned off, and the freewheeling switch group is turned on. A specific turn-on implementation of the freewheeling switch group is as follows: The fifth switching transistor T 5 always maintains a turn-on state; when the freewheeling switch group needs to change from turn-off to turn-on, the sixth switching transistor T 6 changes from turn-off to turn-on, so as to turn on the freewheeling switch group. The first inductor L 1 and the second inductor L 2 discharge, and a current flows in the loop among the alternating current power grid AC, the first inductor L 1 , the freewheeling switch group, and the second inductor L 2 . In this way, in the freewheeling phase, the first inductor L 1 and the second inductor L 2 continuously charge the alternating current power grid AC, so that the transverse bridge supplies power to the output in a negative half cycle of the alternating current.

In the foregoing working process, the inverter circuit in the HERIC topology converts a direct current output by the direct current power supply into an alternating current, to supply power to the alternating current power grid AC.

In some instances, in the process in which the starting phase is changed to the freewheeling phase in the positive half cycle or the negative half cycle, a turn-off speed of the first switching transistor T 1 cannot be synchronized with a turn-off speed of the fourth switching transistor T 4 . For example, the turn-off speed of the fourth switching transistor T 4 is faster than the turn-off speed of the first switching transistor T 1 . When the fourth switching transistor T 4 is turned off but the first switching transistor T 1 is not turned off, the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 is pulled up to a positive voltage of the bus. After the first switching transistor T 1 is turned off, the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 falls back to a midpoint voltage of the bus. In this process, a voltage fluctuation phenomenon causes a resonance phenomenon. Consequently, this impacts the electromagnetic compatibility (EMC) for a device and a system, which need to work normally in their electromagnetic environment without causing unacceptable electromagnetic interference to anything in the environment. As a result, conduction and radiation test results of the EMC exceed thresholds. Similarly, a same problem is also encountered in a process in which the second switching transistor T 2 and the third switching transistor T 3 are turned off.

To resolve the foregoing problem, a third capacitor Csy 1 and a fourth capacitor Csy 2 are bridge-connected to the inverter circuit provided in this embodiment of this application based on the existing HERIC topology.

As shown in FIG. 2 , the third capacitor Csy 1 is connected between the bus and the first longitudinal bridge 10 , and a connection point H between the third capacitor Csy 1 and the first longitudinal bridge 10 is located between the first switching transistor T 1 and the second switching transistor T 2 .

The fourth capacitor Csy 2 is connected between the bus and the second longitudinal bridge 20 , and a connection point J between the fourth capacitor Csy 2 and the second longitudinal bridge 20 is located between the third switching transistor T 3 and the fourth switching transistor T 4 .

The third capacitor Csy 1 is configured to stabilize the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 when the first switching transistor T 1 and the fourth switching transistor T 4 are turned off.

The fourth capacitor Csy 2 is configured to stabilize the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 when the second switching transistor T 2 and the third switching transistor T 3 are turned off.

As shown in FIG. 2 , a connection point G between the third capacitor Csy 1 and the bus is disposed between the first capacitor Cs 1 and the second capacitor Cs 2 , and the third capacitor Csy 1 is connected to the first longitudinal bridge 10 through the connection point H. A connection point I between the fourth capacitor Csy 2 and the bus is disposed between the first capacitor Cs 1 and the second capacitor Cs 2 , and the fourth capacitor Csy 2 is connected to the second longitudinal bridge 20 through the connection point J.

In this embodiment, in the starting phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned on. In this case, the first capacitor Cs 1 and the third capacitor Csy 1 form a parallel equivalent circuit. The first capacitor Cs 1 charges the third capacitor Csy 1 , and voltages of the first capacitor Cs 1 and the third capacitor Csy 1 are equal. Because the first capacitor Cs 1 and the second capacitor Cs 2 form a voltage divider circuit of the direct current power supply, the voltages of the first capacitor Cs 1 and the second capacitor Cs 2 each are equal to ½ of the bus voltage, that is, the ½ bus voltage. In this case, the voltage of the third capacitor Csy 1 is also equal to the ½ bus voltage. In the freewheeling phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned off. If the turn-off speed of the fourth switching transistor T 4 is faster than the turn-off speed of the first switching transistor T 1 , the third capacitor Csy 1 can be further charged by a capacitor with the positive voltage of the bus when the fourth switching transistor T 4 is turned off but the first switching transistor T 1 is not turned off, to avoid fluctuations caused by a voltage increase. If the turn-off speed of the fourth switching transistor T 4 is slower than the turn-off speed of the first switching transistor T 1 , when the first switching transistor T 1 is turned off but the fourth switching transistor T 4 is not turned off, the ½ bus voltage output by the third capacitor Csy 1 can play a stabilizing role, preventing the fluctuation caused by the voltage increase on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 . This effectively prevents resonance caused by the different turn-off speeds of the first switching transistor T 1 and the fourth switching transistor T 4 in the working process of the inverter circuit in the HERIC topology.

In the starting phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned on. In this case, the second capacitor Cs 2 and the fourth capacitor Csy 2 form a parallel equivalent circuit. The second capacitor Cs 2 charges the fourth capacitor Csy 2 , and voltages of the second capacitor Cs 2 and the fourth capacitor Csy 2 are equal. Because the first capacitor Cs 1 and the second capacitor Cs 2 form a voltage divider circuit of the direct current power supply, the voltages of the first capacitor Cs 1 and the second capacitor Cs 2 each are equal to ½ of the bus voltage, that is, the ½ bus voltage. In this case, the voltage of the fourth capacitor Csy 2 is also equal to the ½ bus voltage. In the freewheeling phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned off. If the turn-off speed of the third switching transistor T 3 is faster than the turn-off speed of the second switching transistor T 2 , the fourth capacitor Csy 2 can be further charged by a capacitor with the positive voltage of the bus when the third switching transistor T 3 is turned off but the second switching transistor T 2 is not turned off, to avoid fluctuations caused by a voltage increase. If the turn-off speed of the third switching transistor T 3 is slower than the turn-off speed of the second switching transistor T 2 , the ½ bus voltage output by the fourth capacitor Csy 2 can play a stabilizing role when the second switching transistor T 2 is turned off but the third switching transistor T 3 is not turned off, preventing the fluctuation caused by the voltage increase on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 . This effectively prevents resonance caused by the different turn-off speeds of the second switching transistor T 2 and the third switching transistor T 3 in a working process of the inverter in the HERIC topology.

A difference between the positive half cycle and the negative half cycle of inverter output lies in: In the positive half cycle, the first capacitor Cs 1 is charged by the positive electrode DC+ of the direct current power supply, and charges the third capacitor Csy 1 with a ½ positive bus voltage; whereas in the negative half cycle, the second capacitor Cs 2 is charged by the negative electrode DC− of the direct current power supply, and charges the fourth capacitor Csy 2 with a ½ negative bus voltage.

It should be noted that, in the foregoing first implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected between the first capacitor Cs 1 and the second capacitor Cs 2 on the bus. In this case, the first capacitor Cs 1 and the third capacitor Csy 1 form a parallel circuit, and the second capacitor Cs 2 and the fourth capacitor Csy 2 form a parallel circuit. In this way, when the first switching transistor T 1 and the fourth switching transistor T 4 are turned on, the voltage of the third capacitor Csy 1 is equal to the voltage of the first capacitor Cs 1 , stabilizing the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 in the positive half cycle of inverter output. When the second switching transistor T 2 and the third switching transistor T 3 are turned on, the voltage of the fourth capacitor Csy 2 is equal to the voltage of the second capacitor Cs 2 , stabilizing the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 in the negative half cycle of inverter output. This prevents resonance. Further, when the first switching transistor T 1 , the second switching transistor T 2 , the third switching transistor T 3 , and the fourth switching transistor T 4 are all turned off, the voltage of the first capacitor Cs 1 causes a circuit to sequentially pass through the third capacitor Csy 1 , the first inductor L 1 , the alternating current power grid AC, the second inductor L 2 , the fourth capacitor Csy 2 , and the second capacitor Cs 2 . In this case, the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged with ½ bus voltage. When the first switching transistor T 1 and the fourth switching transistor T 4 are turned on or the second switching transistor T 2 and the third switching transistor T 3 are turned on, a voltage discharged by the third capacitor Csy 1 or the fourth capacitor Csy 2 and a voltage discharged by the first capacitor Cs 1 or the second capacitor Cs 2 are equal and both are the ½ bus voltage. Therefore, a circuit loss is relatively small. In this way, the first implementation in this embodiment of this application not only can effectively prevent resonance caused by different turn-on/turn-off speeds, but also can effectively reduce a circuit loss.

It should be noted that, in an actual physical implementation process of the third capacitor Csy 1 and the fourth capacitor Csy 2 , the third capacitor Csy 1 or the fourth capacitor Csy 2 may be implemented by using one capacitor, or may be implemented by using a plurality of capacitors. This is not limited in this embodiment of this application.

It should be further noted that, modes in which the connection point G between the third capacitor Csy 1 and the bus and the connection point I between the fourth capacitor Csy 2 and the bus are connected to the bus are merely the first implementation provided in this embodiment of this application. Optionally, different working modes may be used to stabilize the voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 based on different locations of the connection point. Specifically, the working modes further include:

•

• 1. Both a connection point between a line on which the third capacitor is located and the bus and a connection point between a line on which the fourth capacitor is located and the bus are disposed between the capacitor group and the direct current power supply. • 2. Neither the connection point between the line on which the third capacitor is located and the bus nor the connection point between the line on which the fourth capacitor is located and the bus is disposed between the first capacitor and the second capacitor. • 3. Only one of the connection point between the line on which the third capacitor is located and the bus and the connection point between the line on which the fourth capacitor is located and the bus is disposed between the first capacitor and the second capacitor.

For ease of understanding, with reference to the accompanying drawings, different connection cases of the third capacitor Csy 1 and the fourth capacitor Csy 2 in the inverter circuit in this embodiment of this application are described in detail below.

•

• (1) Both the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected between the first capacitor Cs 1 on the bus and the positive electrode of the direct current power supply.

As shown in FIG. 3 , in a second implementation, the connection point G between the third capacitor Csy 1 and the bus is disposed between the first capacitor Cs 1 and the positive electrode of the direct current power supply, and the third capacitor Csy 1 is connected to the first longitudinal bridge 10 through the connection point H. The connection point I between the fourth capacitor Csy 2 and the bus is disposed between the first capacitor Cs 1 and the positive electrode of the direct current power supply, and the fourth capacitor Csy 2 is connected to the second longitudinal bridge 20 through the connection point J.

In this embodiment, in the starting phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned on. In this case, a current starts from the first capacitor Cs 1 , and sequentially passes through the first switching transistor T 1 , the first inductor L 1 , the alternating current power grid AC, the second inductor L 2 , the fourth switching transistor T 4 , and the second capacitor Cs 2 . In the freewheeling phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned off. If the turn-off speed of the fourth switching transistor T 4 is different from the turn-off speed of the first switching transistor T 1 , the generated positive voltage of the bus charges the third capacitor Csy 1 , so that the third capacitor Csy 1 can absorb an increased voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 , and the fluctuation caused by the voltage increase is avoided. This effectively prevents resonance caused by the different turn-off speeds of the first switch and the fourth switch in the working process of the inverter circuit in the HERIC topology.

In the starting phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned on. In this case, a current starts from the second capacitor Cs 2 , and sequentially passes through the second switching transistor T 2 , the first inductor L 1 , the alternating current power grid AC, the second inductor L 2 , the third switching transistor T 3 , and the first capacitor Cs 1 . In the freewheeling phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned off. If the turn-off speed of the second switching transistor T 2 is different from the turn-off speed of the third switching transistor T 3 , the generated negative voltage of the bus charges the fourth capacitor Csy 2 , so that the fourth capacitor Csy 2 can absorb a voltage change on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 , and the fluctuation caused by the voltage change is avoided. This effectively prevents resonance caused by the different turn-off speeds of the second switch and the third switch in the working process of the inverter circuit in the HERIC topology.

It should be noted that, in the foregoing second implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected to a positive voltage location of the bus, so that the third capacitor Csy 1 can absorb a voltage fluctuation at a moment at which the first switching transistor T 1 and the fourth switching transistor T 4 are turned off, thereby stabilizing the circuit. Similarly, the fourth capacitor Csy 2 can absorb a voltage fluctuation at a moment at which the second switching transistor T 2 and the third switching transistor T 3 are turned off, thereby stabilizing the circuit. Further, when the first switching transistor T 1 , the second switching transistor T 2 , the third switching transistor T 3 , and the fourth switching transistor T 4 are all turned off, the voltage of the first capacitor Cs 1 causes a circuit to sequentially pass through the third capacitor Csy 1 and the fourth capacitor Csy 2 , and flow through the entire loop. In this case, the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged with one bus voltage. When the first switching transistor T 1 and the fourth switching transistor T 4 are turned on or the second switching transistor T 2 and the third switching transistor T 3 are turned on, a voltage discharged by the third capacitor Csy 1 or the fourth capacitor Csy 2 is greater than a voltage discharged by the first capacitor Cs 1 or the second capacitor Cs 2 (as described above, in the voltage divider circuit including the first capacitor Cs 1 and the second capacitor Cs 2 , the voltage of the first capacitor Cs 1 and the voltage of the second capacitor Cs 2 both are equal to ½ bus voltage). In this way, when the first switching transistor T 1 and the fourth switching transistor T 4 are turned on or the second switching transistor T 2 and the third switching transistor T 3 are turned on, the third capacitor Csy 1 or the fourth capacitor Csy 2 needs to discharge an extra voltage. This process causes an external circuit loss. In this way, the second implementation in this embodiment of this application can effectively prevent the resonance caused by the different turn-on/turn-off speeds, but causes a specific circuit loss. Therefore, the second implementation may be used as a candidate implementation.

•

• (2) Both the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected between the second capacitor Cs 2 on the bus and the negative electrode of the direct current power supply.

As shown in FIG. 4 , in a third implementation, the connection point G between the third capacitor Csy 1 and the bus is disposed between the second capacitor Cs 2 and the negative electrode of the direct current power supply, and the third capacitor Csy 1 is connected to the first longitudinal bridge 10 through the connection point H. The connection point I between the fourth capacitor Csy 2 and the bus is disposed between the second capacitor Cs 2 and the negative electrode of the direct current power supply, and the fourth capacitor Csy 2 is connected to the second longitudinal bridge 20 through the connection point J.

In this embodiment, in the starting phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned on. In this case, a current starts from the first capacitor Cs 1 , and sequentially passes through the first switching transistor T 1 , the first inductor L 1 , the alternating current power grid AC, the second inductor L 2 , the fourth switching transistor T 4 , and the second capacitor Cs 2 . In the freewheeling phase of the positive half cycle of inverter output, the first switching transistor T 1 and the fourth switching transistor T 4 are turned off. If the turn-off speed of the fourth switching transistor T 4 is different from the turn-off speed of the first switching transistor T 1 , the generated positive voltage of the bus charges the third capacitor Csy 1 , so that the third capacitor Csy 1 can absorb an increased voltage on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 , and the fluctuation caused by the voltage increase is avoided. This effectively prevents the resonance caused by the different turn-off speeds of the first switch and the fourth switch in the working process of the inverter circuit in the HERIC topology.

In the starting phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned on. In this case, a current starts from the second capacitor Cs 2 , and sequentially passes through the second switching transistor T 2 , the first inductor L 1 , the alternating current power grid AC, the second inductor L 2 , the third switching transistor T 3 , and the first capacitor Cs 1 . In the freewheeling phase of the negative half cycle of inverter output, the second switching transistor T 2 and the third switching transistor T 3 are turned off. If the turn-off speed of the second switching transistor T 2 is different from the turn-off speed of the third switching transistor T 3 , the generated negative voltage of the bus charges the fourth capacitor Csy 2 , so that the fourth capacitor Csy 2 can absorb a voltage change on the bus, the first longitudinal bridge 10 , and the second longitudinal bridge 20 , and the fluctuation caused by the voltage change is avoided. This effectively prevents resonance caused by the different turn-off speeds of the second switch and the third switch in the working process of the inverter circuit in the HERIC topology.

It should be noted that, in the foregoing third implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected to a negative voltage location of the bus, so that the third capacitor Csy 1 can absorb a voltage fluctuation at a moment at which the first switching transistor T 1 and the fourth switching transistor T 4 are turned off, thereby stabilizing a circuit. Similarly, the fourth capacitor Csy 2 can absorb a voltage fluctuation at a moment at which the second switching transistor T 2 and the third switching transistor T 3 are turned off, thereby stabilizing the circuit. Further, when the first switching transistor T 1 , the second switching transistor T 2 , the third switching transistor T 3 , and the fourth switching transistor T 4 are all turned off, the voltage of the first capacitor Cs 1 causes a circuit to sequentially pass through the third capacitor Csy 1 and the fourth capacitor Csy 2 , and flow through the entire loop. In this case, the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged with the voltage of the one bus. When the first switching transistor T 1 and the fourth switching transistor T 4 are turned on or the second switching transistor T 2 and the third switching transistor T 3 are turned on, the voltage discharged by the third capacitor Csy 1 or the voltage discharged by the fourth capacitor Csy 2 is greater than the voltage discharged by the first capacitor Cs 1 or the second capacitor Cs 2 (as described above, in the voltage divider circuit including the first capacitor Cs 1 and the second capacitor Cs 2 , the voltage of the first capacitor Cs 1 and the voltage of the second capacitor Cs 2 both are equal to ½ bus voltage). In this way, when the first switching transistor T 1 and the fourth switching transistor T 4 are turned on or the second switching transistor T 2 and the third switching transistor T 3 are turned on, the third capacitor Csy 1 or the fourth capacitor Csy 2 needs to discharge an extra voltage. This process causes an external circuit loss. In this way, the third implementation in this embodiment of this application can effectively prevent the resonance caused by the different turn-on/turn-off speeds, but causes a specific circuit loss. The third implementation and the foregoing second implementation of this application are equivalent. A difference lies in: In the second implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected to the positive voltage location of the bus; whereas in the second implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected to the negative voltage location of the bus. The third implementation may be used as an alternative solution of the foregoing second implementation.

The foregoing describes three solutions that are improved based on the inverter circuit in the HERIC topology in the embodiments of this application. In the first implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected between the first capacitor Cs 1 and the second capacitor Cs 2 (that is, a midpoint of the bus); in the second implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected between the first capacitor Cs 1 and the positive electrode of the direct current power supply (that is, a positive electrode of the bus); in the third implementation, the third capacitor Csy 1 and the fourth capacitor Csy 2 are bridge-connected between the second capacitor Cs 2 and the negative electrode of the direct current power supply (that is, a negative electrode of the bus). Optionally, the following implementations may be further included based on a combination of the foregoing implementations.

In a fourth implementation, the third capacitor Csy 1 is bridge-connected to the midpoint of the bus, and the fourth capacitor Csy 2 is bridge-connected to the positive electrode of the bus.

In a fifth implementation, shown in FIG. 16 , the third capacitor Csy 1 is bridge-connected to the midpoint of the bus, and the fourth capacitor Csy 2 is bridge-connected to the negative electrode of the bus.

In a sixth implementation, the fourth capacitor Csy 2 is bridge-connected to the midpoint of the bus, and the third capacitor Csy 1 is bridge-connected to the positive electrode of the bus.

In a seventh implementation, the fourth capacitor Csy 2 is bridge-connected to the midpoint of the bus, and the third capacitor Csy 1 is bridge-connected to the negative electrode of the bus.

In an eighth implementation, shown in FIG. 17 , the third capacitor Csy 1 is bridge-connected to the positive electrode of the bus, and the fourth capacitor Csy 2 is bridge-connected to the negative electrode of the bus.

In a ninth implementation, the third capacitor Csy 1 is bridge-connected to the negative electrode of the bus, and the fourth capacitor Csy 2 is bridge-connected to the positive electrode of the bus.

In the foregoing fourth to ninth implementations, for connection solutions and working principles of bridge-connection modes of the third capacitor Csy 1 and the fourth capacitor Csy 2 , refer to the foregoing first to third implementations. A difference lies only in different combinations of the bridge-connection modes. Details are not described herein again.

It should be noted that, in any one of the foregoing embodiments, an impedance network may be connected in series to the third capacitor Csy 1 and the fourth capacitor Csy 2 , to protect charging stability of the third capacitor Csy 1 and the fourth capacitor Csy 2 . In this way, in a process of charging the third capacitor Csy 1 and the fourth capacitor Csy 2 , the charging stability of the third capacitor Csy 1 and the fourth capacitor Csy 2 is maintained. Specifically, the impedance network includes at least one inductor and/or at least one resistor that are connected in series. For ease of understanding, different cases of the impedance network are specifically described below with reference to the accompanying drawings.

As shown in FIG. 5 , based on the first implementation of this embodiment of this application, the inductor Ls 1 and the inductor Ls 2 are respectively disposed in series with the third capacitor Csy 1 and the fourth capacitor Csy 2 . The inductor Ls 1 is connected in series to the third capacitor Csy 1 , and the inductor Ls 2 is connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, the inductor Ls 1 and the inductor Ls 2 can share a current flowing into the third capacitor Csy 1 and the fourth capacitor Csy 2 , to prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to instantaneous charging by an excessive current. When the charging of the third capacitor Csy 1 and the fourth capacitor Csy 2 is completed, the inductor Ls 1 and the inductor Ls 2 may release the charged current, and slowly charge the third capacitor Csy 1 and the fourth capacitor Csy 2 , so that a large current does not damage the third capacitor Csy 1 and the fourth capacitor Csy 2 , and does not waste an excess current.

Further, as shown in FIG. 6 , based on the first implementation of this embodiment of this application, a resistor Rs 1 and a resistor Rs 2 are respectively disposed in series on the third capacitor Csy 1 and the fourth capacitor Csy 2 . The resistor Rs 1 is connected in series to the third capacitor Csy 1 , and the resistor Rs 2 is connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, if a charged current is excessively large, the resistor Rs 1 and the resistor Rs 2 respectively connected in series to the third capacitor Csy 1 and the fourth capacitor Csy 2 can convert extra electric energy. This protects the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevents the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to charging by a large current.

Further, as shown in FIG. 7 , based on the first implementation of this embodiment of this application, the inductor Ls 1 , the inductor Ls 2 , the resistor Rs 1 , and the resistor Rs 2 are disposed in series with the third capacitor Csy 1 and the fourth capacitor Csy 2 . The inductor Ls 1 and the resistor Rs 1 are connected in series to the third capacitor Csy 1 , and the inductor Ls 2 and the resistor Rs 2 are connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, the inductor Ls 1 and the inductor Ls 2 can share a current flowing into the third capacitor Csy 1 and the fourth capacitor Csy 2 , to prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to instantaneous charging by an excessive current. Further, the resistor Rs 1 and the resistor Rs 2 that are connected in series can convert extra electric energy. This further protects the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevents the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to charging of a large current.

As shown in FIG. 8 , based on the second implementation of this embodiment of this application, the inductor Ls 1 and the inductor Ls 2 are respectively disposed in series on the third capacitor Csy 1 and the fourth capacitor Csy 2 . The inductor Ls 1 is connected in series to the third capacitor Csy 1 , and the inductor Ls 2 is connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, the inductor Ls 1 and the inductor Ls 2 can share a current charged into the third capacitor Csy 1 and the fourth capacitor Csy 2 , to prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to instantaneous charging by an excessive current. When the charging of the third capacitor Csy 1 and the fourth capacitor Csy 2 is completed, the inductor Ls 1 and the inductor Ls 2 may release the charged current, and slowly charge the third capacitor Csy 1 and the fourth capacitor Csy 2 , so that a large current does not damage the third capacitor Csy 1 and the fourth capacitor Csy 2 , and does not waste an excess current.

Further, as shown in FIG. 9 , based on the second implementation of this embodiment of this application, the resistor Rs 1 and the resistor Rs 2 are respectively disposed in series on the third capacitor Csy 1 and the fourth capacitor Csy 2 . The resistor Rs 1 is connected in series to the third capacitor Csy 1 , and the resistor Rs 2 is connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, if a charged current is excessively large, the resistor Rs 1 and the resistor Rs 2 respectively connected in series to the third capacitor Csy 1 and the fourth capacitor Csy 2 can convert extra electric energy. This protects the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevents the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to charging by a large current.

Further, as shown in FIG. 10 , based on the second implementation of this embodiment of this application, the inductor Ls 1 , the inductor Ls 2 , the resistor Rs 1 , and the resistor Rs 2 are disposed in series with the third capacitor Csy 1 and the fourth capacitor Csy 2 . The inductor Ls 1 and the resistor Rs 1 are connected in series to the third capacitor Csy 1 , and the inductor Ls 2 and the resistor Rs 2 are connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, the inductor Ls 1 and the inductor Ls 2 can share a current charged into the third capacitor Csy 1 and the fourth capacitor Csy 2 , to prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to instantaneous charging of an excessive current. Further, the resistor Rs 1 and the resistor Rs 2 that are connected in series can convert extra electric energy. This further protects the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevents the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to charging by a large current.

As shown in FIG. 11 , based on the third implementation of this embodiment of this application, the inductor Ls 1 and the inductor Ls 2 are respectively disposed in series on the third capacitor Csy 1 and the fourth capacitor Csy 2 . The inductor Ls 1 is connected in series to the third capacitor Csy 1 , and the inductor Ls 2 is connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, the inductor Ls 1 and the inductor Ls 2 can share a current charged into the third capacitor Csy 1 and the fourth capacitor Csy 2 , to prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to instantaneous charging by an excessive current. When the charging of the third capacitor Csy 1 and the fourth capacitor Csy 2 is completed, the inductor Ls 1 and the inductor Ls 2 may release the charged current, and slowly charge the third capacitor Csy 1 and the fourth capacitor Csy 2 , so that a large current does not damage the third capacitor Csy 1 and the fourth capacitor Csy 2 , and does not waste an excess current.

Further, as shown in FIG. 12 , based on the third implementation of this embodiment of this application, the resistor Rs 1 and the resistor Rs 2 are respectively disposed in series on the third capacitor Csy 1 and the fourth capacitor Csy 2 . The resistor Rs 1 is connected in series to the third capacitor Csy 1 , and the resistor Rs 2 is connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, if a charged current is excessively large, the resistor Rs 1 and the resistor Rs 2 respectively connected in series to the third capacitor Csy 1 and the fourth capacitor Csy 2 can convert extra electric energy. This protects the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevents the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to charging by a large current.

Further, as shown in FIG. 13 , based on the third implementation of this embodiment of this application, the inductor Ls 1 , the inductor Ls 2 , the resistor Rs 1 , and the resistor Rs 2 are disposed in series with the third capacitor Csy 1 and the fourth capacitor Csy 2 . The inductor Ls 1 and the resistor Rs 1 are connected in series to the third capacitor Csy 1 , and the inductor Ls 2 and the resistor Rs 2 are connected in series to the fourth capacitor Csy 2 .

In this embodiment, in a process in which the third capacitor Csy 1 and the fourth capacitor Csy 2 are charged, the inductor Ls 1 and the inductor Ls 2 can share a current charged into the third capacitor Csy 1 and the fourth capacitor Csy 2 , to prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to instantaneous charging by an excessive current. Further, the resistor Rs 1 and the resistor Rs 2 that are connected in series can convert extra electric energy. This further protects the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevents the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged due to charging by a large current.

Further, based on the foregoing fourth to ninth implementations, an impedance network may be disposed on the third capacitor Csy 1 and the fourth capacitor Csy 2 . For a specific setting manner, refer to the foregoing first to third implementations. A difference lies only in different combinations of the bridge-connection modes. Details are not described herein again.

It should be noted that, when the impedance network is disposed, the impedance network may protect the third capacitor Csy 1 and the fourth capacitor Csy 2 , and prevent the third capacitor Csy 1 and the fourth capacitor Csy 2 from being damaged in a charging process. However, existence of the impedance network also reduces the third capacitor Csy 1 and the fourth capacitor Csy 2 , thereby affecting protection of the third capacitor Csy 1 and the fourth capacitor Csy 2 against resonance in a turn-off process of the switching transistors to some extent. In this way, users can determine, depending on actual situations, whether to add an impedance network and to increase a quantity of capacitors specifically disposed in the impedance network and a quantity of inductors specifically disposed in the impedance network.

As shown in FIG. 14 , an embodiment of this application further provides an inverter. The inverter includes a control unit 1401 and an inverter power unit 1402 . The control unit is configured to control the inverter power unit, and the inverter power unit 1402 includes the inverter circuit according to any one of the foregoing implementations. For understanding, refer to the foregoing description of the inverter circuit. The control unit 1401 may include a control chip and a circuit structure configured to implement a function of the control chip. Operation of the control unit 1401 and the inverter power unit 1402 may include that the control unit 1401 controls turn-on or turn-off of each switching transistor of the inverter circuit in the inverter power unit 1402 .

As shown in FIG. 15 , an embodiment of this application further provides a photovoltaic power system, including a photovoltaic panel 1501 , an inverter 1502 , and an alternating current power grid 1503 . The photovoltaic panel 1501 is connected to the inverter 1502 , and the inverter 1502 is connected to the alternating current power grid 1503 . The photovoltaic panel 1501 is configured to convert light energy into a direct current. The inverter 1502 includes the inverter circuit according to any one of the foregoing embodiments, and is configured to convert the direct current into an alternating current. The alternating current power grid 1503 is configured to transmit the alternating current.

In this embodiment, the inverter converts the direct current generated by the photovoltaic panel through solar energy power generation into alternating current, and connects the alternating current to the alternating current power grid, so that solar energy is utilized. The inverter circuit included in the inverter is the inverter circuit according to any one of the foregoing embodiments. For understanding, refer to the foregoing description of the inverter circuit. The inverter circuit not only can convert the direct current into the alternating current, but also can avoid an EMC problem caused by a resonance phenomenon.

The foregoing describes in detail the inverter circuit, the inverter, and the photovoltaic power system that are provided in the embodiments of this application. The principles and implementations of this application are described herein by using specific examples. The description about the embodiments of this application is merely provided to help understand the method and core ideas of this application. In addition, a person of ordinary skill in the art can make variations and modifications to this application in terms of the specific implementations and application scopes according to the ideas of this application. Therefore, the content of specification shall not be construed as a limitation to this application.