Display Device and Array Substrate

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of PCT international application Ser. No. PCT/JP2019/028861 filed on Jul. 23, 2019 which designates the United States, incorporated herein by reference, and claims the benefit of priority from Japanese Patent Application No. 2018-179815 filed on Sep. 26, 2018, incorporated herein by reference.

BACKGROUND

1. Technical Field

The present disclosure relates to a display device and an array substrate.

2. Description of the Related Art

Widely known are display devices including organic light emitting diodes (OLED) or inorganic light emitting diodes (micro LEDs) serving as display elements. Japanese Patent Application Laid-open Publication No. 2018-41752 (JP-A-2018-41752) describes a semiconductor device used as a pixel circuit for display devices or the like. The pixel circuit described in JP-A-2018-41752 includes a plurality of transistors and a plurality of capacitances in each pixel.

The pixel circuit described in JP-A-2018-41752 has a large number of elements (the transistors and the capacitances) in one pixel and a large number of wires coupled to the elements. As a result, it may possibly be difficult to efficiently dispose the wiring.

SUMMARY

A display device according to an embodiment of the present disclosure includes a substrate, a plurality of pixels provided to the substrate, a light emitting element and a plurality of transistors provided to each of the pixels, signal lines configured to supply a signal to the pixels, a first semiconductor layer and a second semiconductor layer provided in different layers in a direction perpendicular to the substrate and overlap at least partially in planar view, first gate electrodes each of which is provided in a region overlapping a part of the first semiconductor layer, a first insulating film provided between the first gate electrodes and the first semiconductor layer, and a second insulating film provided between the first semiconductor layer and the second semiconductor layer.

An array substrate according to an embodiment of the present disclosure includes a substrate, a plurality of transistors provided to the substrate, a first semiconductor layer and a second semiconductor layer provided in different layers in a direction perpendicular to the substrate and overlap at least partially in planar view, first gate electrodes each of which is provided in a region overlapping a part of the first semiconductor layer, a first insulating film provided between the first gate electrodes and the first semiconductor layer, and a second insulating film provided between the first semiconductor layer and the second semiconductor layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view schematically illustrating a display device according to an embodiment;

FIG. 2 is a plan view of a plurality of pixels;

FIG. 3 is a circuit diagram of a pixel circuit;

FIG. 4 is an enlarged plan view of two pixels of the display device according to the embodiment;

FIG. 5 is a sectional view along line V-V′ of FIG. 4 ;

FIG. 6 is a sectional view along line VI-VI′ of FIG. 4 ;

FIG. 7 is a sectional view of a light emitting element according to the embodiment;

FIG. 8 is a sectional view of the light emitting element according to a first modification of the embodiment; and

FIG. 9 is a sectional view of the display device according to a second modification of the embodiment.

DETAILED DESCRIPTION

Exemplary aspects (embodiments) to embody the present disclosure are described below in greater detail with reference to the accompanying drawings. The contents described in the embodiments are not intended to limit the present disclosure. Components described below include components easily conceivable by those skilled in the art and components substantially identical therewith.

Furthermore, the components described below may be appropriately combined. What is disclosed herein is given by way of example only, and appropriate changes made without departing from the spirit of the present disclosure and easily conceivable by those skilled in the art naturally fall within the scope of the disclosure. To simplify the explanation, the drawings may possibly illustrate the width, the thickness, the shape, and other elements of each unit more schematically than the actual aspect. These elements, however, are given by way of example only and are not intended to limit interpretation of the present disclosure. In the present specification and the figures, components similar to those previously described with reference to previous figures are denoted by like reference numerals, and detailed explanation thereof may be appropriately omitted.

EMBODIMENTS

FIG. 1 is a plan view schematically illustrating a display device according to an embodiment. As illustrated in FIG. 1 , a display device 1 includes an array substrate 2 , pixels Pix, drive circuits 12 , a drive integrated circuit (IC) 210 , and cathode wiring 60 . The array substrate 2 is a drive circuit board for driving the pixels Pix and is also called a backplane or an active matrix substrate. The array substrate 2 includes a substrate 21 , a plurality of transistors, a plurality of capacitances, and various kinds of wiring, for example.

As illustrated in FIG. 1 , the display device 1 has a display region AA and a peripheral region GA. The display region AA is disposed overlapping the pixels Pix and displays an image. The peripheral region GA does not overlap the pixels Pix and is disposed outside the display region AA.

The pixels Pix are arrayed in a first direction Dx and a second direction Dy in the display region AA of the substrate 21 . The first direction Dx and the second direction Dy are parallel to the surface of the substrate 21 . The first direction Dx is orthogonal to the second direction Dy. The first direction Dx may intersect the second direction Dy without being orthogonal thereto. A third direction Dz is orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to the normal direction of the substrate 21 , for example. In the following description, planar view indicates the positional relation when viewed in the third direction Dz.

The drive circuits 12 drive a plurality of gate lines (e.g., a reset control signal line L 5 , an output control signal line L 6 , a pixel control signal line L 7 , and an initialization control signal line L 8 (refer to FIG. 3 )) based on various control signals received from the drive IC 210 . The drive circuits 12 sequentially or simultaneously select a plurality of gate lines and supply gate drive signals to the selected gate lines. As a result, the drive circuits 12 select a plurality of pixels Pix coupled to the gate lines.

The drive IC 210 is a circuit that controls display on the display device 1 . The drive IC 210 is mounted on the peripheral region GA of the substrate 21 as chip on glass (COG). The mounting form of the drive IC 210 is not limited thereto, and the drive IC 210 may be mounted on FPCs or a rigid substrate coupled to the peripheral region GA of the substrate 21 as chip on film (COF).

The cathode wiring 60 is provided in the peripheral region GA of the substrate 21 . The cathode wiring 60 is provided surrounding the pixels Pix in the display region AA and the drive circuits 12 in the peripheral region GA. Cathodes of a plurality of light emitting elements 3 are coupled to the common cathode wiring 60 and supplied with a fixed potential (e.g., a ground potential). More specifically, a cathode terminal 22 t of the light emitting element 3 (illustrated in FIG. 5 ) is coupled to the cathode wiring 60 via a cathode electrode 22 .

FIG. 2 is a plan view of a plurality of pixels. As illustrated in FIG. 2 , one pixel Pix includes a plurality of pixels 49 . The pixel Pix includes a first pixel 49 R, a second pixel 49 G, and a third pixel 49 B, for example. The first pixel 49 R displays a primary color of red as the first color. The second pixel 49 G displays a primary color of green as the second color. The third pixel 49 B displays a primary color of blue as the third color. As illustrated in FIG. 2 , the first pixel 49 R and the third pixel 49 B are disposed side by side in the first direction Dx in one pixel Pix. The second pixel 49 G and the third pixel 49 B are disposed side by side in the second direction Dy. The first color, the second color, and the third color are not limited to red, green, and blue, respectively, and may be any desired colors, such as complementary colors. In the following description, the first pixel 49 R, the second pixel 49 G, and the third pixel 49 B are referred to as pixels 49 when they need not be distinguished from one another.

The pixels 49 each include the light emitting element 3 and an anode electrode 23 . The display device 1 displays an image by outputting different light from light emitting elements 3 R, 3 G, and 3 B in the first pixel 49 R, the second pixel 49 G, and the third pixel 49 B, respectively. The light emitting element 3 is an inorganic light emitting diode (LED) chip having a size of approximately 3 μm to 300 μm in planar view and is called a micro LED. The display device 1 including the micro LEDs in the respective pixels is also called a micro LED display device. The term “micro” of the micro LED is not intended to limit the size of the light emitting element 3 .

The light emitting elements 3 may output different light in four or more colors. The positions of the pixels 49 are not limited to the configuration illustrated in FIG. 2 . The first pixel 49 R, for example, may be disposed side by side with the second pixel 49 G in the first direction Dx. Alternatively, the first pixel 49 R, the second pixel 49 G, and the third pixel 49 B may be repeatedly arrayed in this order in the first direction Dx. The display device 1 is not limited to a micro LED display device and may be a self-luminous display device including organic LEDs (OLEDs) as the display elements or a reflective display device, such as electronic paper.

FIG. 3 is a circuit diagram of a pixel circuit. FIG. 3 illustrates a pixel circuit PICA provided to one pixel 49 . The pixel circuit PICA is provided to each of the pixels 49 . As illustrated in FIG. 3 , the pixel circuit PICA includes the light emitting element 3 , five transistors, and two capacitances. Specifically, the pixel circuit PICA includes a drive transistor DRT (first transistor), an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST (second transistor). The drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are n-type thin-film transistors (TFTs). The pixel circuit PICA includes first capacitance Cs 1 and second capacitance Cs 2 .

The cathode (cathode terminal 22 t ) of the light emitting element 3 is coupled to a cathode power supply line L 10 . The anode (anode terminal 23 t ) of the light emitting element 3 is coupled to an anode power supply line L 1 via the drive transistor DRT and the output transistor BCT. The anode power supply line L 1 is supplied with an anode power supply potential PVDD. The cathode power supply line L 10 is supplied with a cathode power supply potential PVSS via the cathode wiring 60 and the cathode electrode 22 . The anode power supply potential PVDD is higher than the cathode power supply potential PVSS.

The anode power supply line L 1 supplies the anode power supply potential PVDD serving as a drive potential to the pixel 49 . Specifically, the light emitting element 3 ideally emits light by being supplied with a forward current (drive current) by a potential difference (PVDD-PVSS) between the anode power supply potential PVDD and the cathode power supply potential PVSS. In other words, the anode power supply potential PVDD has a potential difference to cause the light emitting element 3 to emit light with respect to the cathode power supply potential PVSS. The anode terminal 23 t of the light emitting element 3 is coupled to the anode electrode 23 . The second capacitance Cs 2 serving as an equivalent circuit is coupled between the anode electrode 23 and the anode power supply line L 1 .

The source electrode of the drive transistor DRT is coupled to the anode terminal 23 t of the light emitting element 3 via the anode electrode 23 , and the drain electrode thereof is coupled to the source electrode of the output transistor BCT. The gate electrode of the drive transistor DRT is coupled to the first capacitance Cs 1 , the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.

The gate electrode of the output transistor BCT is coupled to the output control signal line L 6 . The output control signal line L 6 is supplied with an output control signal BG. The drain electrode of the output transistor BCT is coupled to the anode power supply line L 1 .

The source electrode of the initialization transistor IST is coupled to an initialization power supply line L 4 . The initialization power supply line L 4 is supplied with an initialization potential Vini. The gate electrode of the initialization transistor IST is coupled to the initialization control signal line L 8 . The initialization control signal line L 8 is supplied with an initialization control signal IG. In other words, the gate electrode of the drive transistor DRT is coupled to the initialization power supply line L 4 via the initialization transistor IST.

The source electrode of the pixel selection transistor SST is coupled to a video signal line L 2 . The video signal line L 2 is supplied with a video signal Vsig. The gate electrode of the pixel selection transistor SST is coupled to the pixel control signal line L 7 . The pixel control signal line L 7 is supplied with a pixel control signal SG.

The source electrode of the reset transistor RST is coupled to a reset power supply line L 3 . The reset power supply line L 3 is supplied with a reset power supply potential Vrst. The gate electrode of the reset transistor RST is coupled to the reset control signal line L 5 . The reset control signal line L 5 is supplied with a reset control signal RG. The drain electrode of the reset transistor RST is coupled to the anode electrode 23 (anode terminal 23 t of the light emitting element 3 ) and the source electrode of the drive transistor DRT. A reset operation performed by the reset transistor RST resets the voltage held in the first capacitance Cs 1 and the second capacitance Cs 2 .

The first capacitance Cs 1 serving as an equivalent circuit is provided between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can prevent fluctuations in the gate voltage due to parasitic capacitance and current leakage in the drive transistor DRT by the first capacitance Cs 1 and the second capacitance Cs 2 .

In the following description, the anode power supply line L 1 and the cathode power supply line L 10 may be simply referred to as power supply lines. The video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 may be referred to as signal lines. The reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 may be referred to as gate lines.

The gate electrode of the drive transistor DRT is supplied with an electric potential corresponding to the video signal Vsig (or gradation signal). In other words, the drive transistor DRT supplies an electric current corresponding to the video signal Vsig to the light emitting element 3 based on the anode power supply potential PVDD supplied via the output transistor BCT. As described above, the anode power supply potential PVDD supplied to the anode power supply line L 1 is lowered by the drive transistor DRT and the output transistor BCT. As a result, an electric potential lower than the anode power supply potential PVDD is supplied to the anode terminal 23 t of the light emitting element 3 .

A first electrode of the second capacitance Cs 2 is supplied with the anode power supply potential PVDD via the anode power supply line L 1 , and a second electrode of the second capacitance Cs 2 is supplied with an electric potential lower than the anode power supply potential PVDD. In other words, the first electrode of the second capacitance Cs 2 is supplied with an electric potential higher than that supplied to the second electrode of the second capacitance Cs 2 . The first electrode of the second capacitance Cs 2 is the anode power supply line L 1 illustrated in FIG. 6 , for example. The second electrode of the second capacitance Cs 2 is the anode electrode 23 coupled to the source of the drive transistor DRT and an anode coupling electrode 24 coupled to the anode electrode 23 illustrated in FIG. 5 , for example.

In the display device 1 , the drive circuits 12 (illustrated in FIG. 1 ) select a plurality of pixel rows in order from the first row (e.g., the uppermost pixel row in the display region AA in FIG. 1 ). The drive IC 210 writes the video signals Vsig (video writing potential) to the pixels 49 of the selected pixel row, thereby causing the light emitting elements 3 to emit light. The drive IC 210 supplies the video signals Vsig to the video signal line L 2 , supplies the reset power supply potential Vrst to the reset power supply line L 3 , and supplies the initialization potential Vini to the initialization power supply line L 4 in each horizontal scanning period. The display device 1 repeats these operations in units of an image of one frame.

The following describes a specific configuration example of the transistors and the wires with reference to FIGS. 4 to 6 . FIG. 4 is an enlarged plan view of two pixels of the display device according to the embodiment.

FIG. 4 illustrates two pixels 49 (e.g., the first pixel 49 R and the third pixel 49 B) disposed side by side in the first direction Dx. As illustrated in FIG. 4 , the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 extend in the second direction Dy. The reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 extend in the first direction Dx and intersect the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 in planar view. Coupling wiring L 9 is provided between the two anode power supply lines L 1 disposed side by side in the first direction Dx. The coupling wiring L 9 couples the drive transistor DRT, the pixel selection transistor SST, and the initialization transistor IST.

The display device 1 (array substrate 2 ) according to the present embodiment includes a first metal layer ML 1 and a second metal layer ML 2 provided in different directions in the third direction Dz. The first metal layer ML 1 and the second metal layer ML 2 are provided in the layers different from those of first semiconductor layers 61 and 65 and second semiconductor layers 71 , 75 , and 79 . The first semiconductor layers 61 and 65 and the second semiconductor layers 71 , 75 , and 79 are provided in different layers. In FIG. 4 , the first metal layer ML 1 is represented by the dotted lines, and the second metal layer ML 2 , the first semiconductor layers 61 and 65 , and the second semiconductor layers 71 , 75 , and 79 are hatched to distinguish the first metal layer ML 1 , the second metal layer ML 2 , the first semiconductor layers 61 and 65 , and the second semiconductor layers 71 , 75 , and 79 .

The anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , the initialization power supply line L 4 , and the coupling wiring L 9 are formed in the second metal layer ML 2 . The reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 are formed in the first metal layer ML 1 .

The first metal layer ML 1 and the second metal layer ML 2 are made of titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), indium tin oxide (ITO), aluminum (Al), silver (Ag), Ag alloy, copper (Cu), carbon nanotube, graphite, graphene, or carbon nanobud, for example. The sheet resistance of the anode power supply line L 1 , the video signal line L 2 , the reset power supply line L 3 , the initialization power supply line L 4 , and the coupling wiring L 9 formed in the second metal layer ML 2 is equal to or lower than that of the gate lines formed in the first meatal layer ML 1 . The sheet resistance of the anode power supply line L 1 is equal to or lower than that of the signal lines (the video signal line L 2 , the reset power supply line L 3 , the initialization power supply line L 4 , and the coupling wiring L 9 ). The sheet resistance of the anode power supply line L 1 is 30 mΩ to 120 mΩ, for example. The sheet resistance of the signal lines and the coupling wiring L 9 (second metal layer ML 2 ) is 120 mΩ to 300 mΩ. The sheet resistance of the gate lines (first metal layer ML 1 ) is 300 mΩ to 3000 mΩ. With this configuration, the display device 1 can prevent a drive voltage applied to the anode power supply line L 1 from dropping, thereby reducing deterioration in display quality.

The first metal layer ML 1 and the second metal layer ML 2 are not limited to single layers and may be multilayered films. The second metal layer ML 2 may be a multilayered structure of Ti/Al/Ti or Mo/Al/Mo, for example, or may be a single-layered film made of Al. Ti, Al, and Mo may be alloys.

The first semiconductor layers 61 and 65 and the second semiconductor layers 71 , 75 , and 79 are made of amorphous silicon, microcrystalline oxide semiconductor, amorphous oxide semiconductor, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), or gallium nitride (GaN), for example. Examples of the oxide semiconductor include, but are not limited to, IGZO, zinc oxide (ZnO), ITZO, etc. IGZO is indium gallium zinc oxide, and ITZO is indium tin zinc oxide. The first semiconductor layers 61 and 65 and the second semiconductor layers 71 , 75 , and 79 may be made of the same material, such as polycrystalline silicon.

As illustrated in FIG. 4 , the reset power supply line L 3 and the initialization power supply line L 4 are shared by the two pixels 49 disposed side by side in the first direction Dx. Specifically, the first pixel 49 R illustrated on the left in FIG. 4 is provided not with the initialization power supply line L 4 but with the reset power supply line L 3 extending along the video signal line L 2 . The third pixel 49 B illustrated on the right in FIG. 4 is provided not with the reset power supply line L 3 but with the initialization power supply line L 4 extending along the video signal line L 2 . This configuration requires a smaller number of wires and enables efficiently disposing the wiring compared with the configuration in which the reset power supply line L 3 and the initialization power supply line L 4 are provided to each of the pixels 49 .

The drive transistor DRT (first transistor) includes the first semiconductor layer 61 , a source electrode 62 , and a first gate electrode 64 . The first semiconductor layer 61 , the source electrode 62 , and the first gate electrode 64 partially overlap in planar view and are provided in a region surrounded by the two anode power supply lines L 1 disposed side by side in the first direction Dx, the output control signal line L 6 , and the pixel control signal line L 7 . Part of a region in the first semiconductor layer 61 overlapping the first gate electrode 64 serves as a channel region. The drive transistor DRT has a single-gate structure in which one first gate electrode 64 is provided overlapping the first semiconductor layer 61 .

The first semiconductor layer 61 includes a first partial semiconductor layer 61 a . The first partial semiconductor layer 61 a is provided in the same layer as that of the first semiconductor layer 61 and made of the same semiconductor material as that of the first semiconductor layer 61 . The first partial semiconductor layer 61 a is a part protruding from the first semiconductor layer 61 in the first direction Dx. The width of the first partial semiconductor layer 61 a in the first direction Dx is larger than the width in the first direction Dx of the part of the first semiconductor layer 61 coupled to the first semiconductor layer 65 of the output transistor BCT. The first semiconductor layer 61 is coupled to the source electrode 62 via the first partial semiconductor layer 61 a . The first semiconductor layer 61 and the first partial semiconductor layer 61 a overlap a first insulating film 91 (refer to FIG. 5 ) and the first gate electrode 64 . The first capacitance Cs 1 is formed between the first partial semiconductor layer 61 a and the first gate electrode 64 . The first semiconductor layer 61 and the first partial semiconductor layer 61 a may each have a rectangular shape and be electrically coupled to each other via a coupler.

The output transistor BCT includes the first semiconductor layer 65 . The first semiconductor layer 65 is coupled to the first semiconductor layer 61 and intersects the output control signal line L 6 in planar view. A region in the first semiconductor layer 65 overlapping the output control signal line L 6 serves as a channel region. The part of the output control signal line L 6 overlapping the first semiconductor layer 65 functions as a first gate electrode 66 of the output transistor BCT. One end of the first semiconductor layer 65 is electrically coupled to an anode power supply line coupling part L 1 a . The anode power supply line coupling part L 1 a is a part branched off from the anode power supply line L 1 in the first direction Dx. With this configuration, the drive transistor DRT and the output transistor BCT are supplied with the anode power supply potential PVDD from the anode power supply line L 1 .

In the third pixel 49 B illustrated on the right in FIG. 4 , the initialization transistor IST includes the second semiconductor layer 71 . In the first pixel 49 R illustrated on the left in FIG. 4 , the initialization transistor IST includes a second semiconductor layer 71 A. The second semiconductor layers 71 and 71 A intersect the initialization control signal line L 8 and a branch signal line L 8 a in planar view. A region in the second semiconductor layers 71 and 71 A overlapping the initialization control signal line L 8 and the branch signal line L 8 a serves as a channel region. The branch signal line L 8 a is branched off from the initialization control signal line L 8 and extends in the first direction Dx. The parts of the initialization control signal line L 8 and the branch signal line L 8 a overlapping the second semiconductor layers 71 and 71 A each function as a second gate electrode 74 of the initialization transistor IST. In other words, the initialization transistor IST has a double-gate structure in which two second gate electrodes 74 are provided overlapping the respective second semiconductor layers 71 and 71 A.

In the third pixel 49 B illustrated on the right in FIG. 4 , the second semiconductor layer 71 extends in the second direction Dy. One end of the second semiconductor layer 71 is electrically coupled to the coupling wiring L 9 , and the other end is coupled to an initialization power supply line coupling part L 4 a . The initialization power supply line coupling part L 4 a is a part branched off from the initialization power supply line L 4 in the first direction Dx. In the first pixel 49 R illustrated on the left in FIG. 4 , the second semiconductor layer 71 A includes a part extending in the second direction Dy and a part extending in the first direction Dx. One end of the part of the second semiconductor layer 71 A extending in the second direction Dy is electrically coupled to the coupling wiring L 9 . The part of the second semiconductor layer 71 A extending in the first direction Dx intersects the anode power supply line L 1 and the video signal line L 2 in planar view, extends to the third pixel 49 B, and is electrically coupled to the initialization power supply line coupling part L 4 a . With this configuration, one initialization power supply line L 4 is electrically coupled to the two initialization transistors IST and shared by the two pixels 49 disposed side by side in the first direction Dx.

The pixel selection transistor SST includes the second semiconductor layer 75 . The second semiconductor layer 75 extends in the first direction Dx and intersects two branch signal lines L 7 a in planar view. A region in the second semiconductor layer 75 overlapping the two branch signal lines L 7 a serves as a channel region. The two branch signal lines L 7 a are parts branched off from the pixel control signal line L 7 in the second direction Dy. The parts of the two branch signal lines L 7 a overlapping the second semiconductor layer 75 each function as a second gate electrode 78 of the pixel selection transistor SST. In other words, the pixel selection transistor SST has a double-gate structure in which two second gate electrodes 78 are provided overlapping the second semiconductor layer 75 . One end of the second semiconductor layer 75 is coupled to a video signal line coupling part L 2 a , and the other end is coupled to the coupling wiring L 9 . The video signal line coupling part L 2 a is a part branched off from the video signal line L 2 in the first direction Dx.

The reset transistor RST includes the second semiconductor layer 79 . The second semiconductor layer 79 extends in the second direction Dy and intersects the reset control signal line L 5 and a branch signal line L 5 a in planar view. A region in the second semiconductor layer 79 overlapping the reset control signal line L 5 and the branch signal line L 5 a serves as a channel region. The branch signal line L 5 a is branched off from the reset control signal line L 5 and extends in the first direction Dx. The parts of the reset control signal line L 5 and the branch signal line L 5 a overlapping the second semiconductor layer 79 each function as a gate electrode of the reset transistor RST. In other words, the reset transistor RST has a double-gate structure.

The reset power supply line L 3 is coupled to reset power supply line coupling parts L 3 a and L 3 b and a bridge L 3 c extending in the first direction Dx. The reset power supply line coupling parts L 3 a and L 3 b are formed in the second metal layer ML 2 . The bridge L 3 c is formed in a layer different from that of the reset power supply line coupling parts L 3 a and L 3 b , that is, the first metal layer ML 1 , for example. The reset power supply line coupling part L 3 a is provided to the first pixel 49 R, and the reset power supply line coupling part L 3 b is provided to the third pixel 49 B. The anode power supply line L 1 , the video signal line L 2 , and the initialization power supply line L 4 are provided between the reset power supply line coupling parts L 3 a and L 3 b . The bridge L 3 c intersects the anode power supply line L 1 , the video signal line L 2 , and the initialization power supply line L 4 in planar view and couples the reset power supply line coupling parts L 3 a and L 3 b.

In the first pixel 49 R, one end of the second semiconductor layer 79 is coupled to the reset power supply line coupling part L 3 a . In the third pixel 49 B, one end of the second semiconductor layer 79 is coupled to the reset power supply line coupling part L 3 b . The other ends of the second semiconductor layers 79 are each electrically coupled to the first semiconductor layer 65 via a second partial semiconductor layer 79 a . In other words, the other end of the second semiconductor layer 79 of the reset transistor RST is electrically coupled to the anode terminal 23 t of the light emitting element 3 via the first semiconductor layer 65 and the source electrode 62 . With this configuration, one reset power supply line L 3 is electrically coupled to the two reset transistors RST and shared by the two pixels 49 disposed side by side in the first direction Dx.

The first semiconductor layer 61 of the drive transistor DRT and the second semiconductor layer 79 of the reset transistor RST overlap at least partially in planar view. Specifically, the second semiconductor layer 79 includes a second partial semiconductor layer 79 a . The width of the second partial semiconductor layer 79 a in the first direction Dx is larger than the width in the first direction Dx of the part of the second semiconductor layer 79 overlapping the reset control signal line L 5 . The second partial semiconductor layer 79 a is a part of the second semiconductor layer 79 overlapping the first gate electrode 64 in planar view. In other words, at least part of the second partial semiconductor layer 79 a overlaps the first partial semiconductor layer 61 a . The second partial semiconductor layer 79 a has a region overlapping the first partial semiconductor layer 61 a and a region not overlapping the first partial semiconductor layer 61 a.

With this configuration, the first capacitance Cs 1 (refer to FIG. 3 ) is composed of the capacitance formed between the first semiconductor layer 61 (first partial semiconductor layer 61 a ) and the first gate electrode 64 and the capacitance formed between the second semiconductor layer 79 (second partial semiconductor layer 79 a ) and the first gate electrode 64 . The first partial semiconductor layer 61 a and the second partial semiconductor layer 79 a according to the present embodiment overlap in planar view. This configuration can reduce the area of the part that forms the first capacitance Cs 1 in the first semiconductor layer 61 and the second semiconductor layer 79 in planar view compared with the case where a single semiconductor layer and the first gate electrode 64 form the first capacitance Cs 1 . Consequently, the present embodiment can increase the flexibility in disposing the various kinds of wiring in one pixel 49 , thereby enabling efficiently disposing the wiring. Alternatively, the present embodiment can reduce the area of each pixel 49 in planar view, thereby increasing the resolution of the display device 1 .

The drive transistor DRT and the output transistor BCT that supply the drive current to the light emitting element 3 according to the present embodiment has a single-gate structure. The initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST have a double-gate structure. This configuration can prevent current leakage in the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST.

The following describes a sectional configuration of the display device 1 . FIG. 5 is a sectional view along line V-V′ of FIG. 4 . FIG. 6 is a sectional view along line VI-VI′ of FIG. 4 . FIG. 6 schematically illustrates the cathode wiring 60 and a transistor Tr provided in the peripheral region GA.

As illustrated in FIG. 5 , the light emitting element 3 is provided on the array substrate 2 . The array substrate 2 includes the substrate 21 , various transistors, various kinds of wiring, and various insulating films. The substrate 21 is an insulating substrate and is a glass substrate, a resin substrate, or a resin film, for example.

In the present specification, a direction from the substrate 21 to a flattening film 27 in a direction perpendicular to the surface of the substrate 21 is referred to as an “upper side”. A direction from the flattening film 27 to the substrate 21 is referred to as a “lower side”.

The drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST (not illustrated in FIG. 5 ) are provided on a first surface of the substrate 21 . An undercoat film 90 , the first metal layer ML 1 , the first insulating film 91 , the first semiconductor layers 61 and 65 , a second insulating film 92 , the second semiconductor layers 71 and 75 and the second partial semiconductor layer 79 a (second semiconductor layer 79 ), a third insulating film 93 , the second metal layer ML 2 , and a fourth insulating film 94 are layered in order on the first surface of the substrate 21 . In other words, the first insulating film 91 is provided between the first metal layer ML 1 (first gate electrodes 64 and 66 ) and the first semiconductor layers 61 and 65 in the direction perpendicular to the substrate 21 . The second insulating film 92 is provided between the first semiconductor layers 61 and 65 and the second semiconductor layers 71 , 75 , and 79 . The third insulating film 93 is provided between the second semiconductor layers 71 , 75 , and 79 and the second metal layer ML 2 , that is, the various signal lines and the power supply lines. The fourth insulating film 94 is provided on the various signal lines and the power supply lines.

The anode coupling electrode 24 and a shield electrode 26 are provided on the fourth insulating film 94 . The anode electrode 23 and the light emitting element 3 are provided on the anode coupling electrode 24 and the shield electrode 26 with a fifth insulating film 95 interposed therebetween.

In the display device 1 , the array substrate 2 includes the layers from the substrate 21 to the anode electrode 23 . The array substrate 2 does not include the flattening film 27 , the cathode electrode 22 , or the light emitting element 3 .

The undercoat film 90 , the first insulating film 91 , the second insulating film 92 , the third insulating film 93 , and the fifth insulating film 95 are made of inorganic insulating material, such as a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxynitride film (SiON). The inorganic insulating films are not limited to single layers and may be multilayered films. The undercoat film 90 is not necessarily provided. The fourth insulating film 94 and the flattening film 27 are organic insulating films or inorganic-organic hybrid insulating films (made of material in which an organic group (a methyl group or a phenyl group) is bonded to a main chain of Si—O, for example).

The first gate electrodes 64 and 66 and the second gate electrodes 74 and 78 formed in the first metal layer ML 1 are provided on the substrate 21 with the undercoat film 90 interposed therebetween. The first insulating film 91 is provided on the undercoat film 90 to cover the first gate electrodes 64 and 66 and the second gate electrodes 74 and 78 . The first semiconductor layers 61 and 65 are provided on the first insulating film 91 . The second insulating film 92 is provided on the first insulating film 91 to cover the first semiconductor layers 61 and 65 .

The second semiconductor layers 71 , 75 , and 79 are provided on the second insulating film 92 . The third insulating film 93 is provided on the second insulating film 92 to cover the second semiconductor layers 71 , 75 , and 79 . With this configuration, the distance between the second semiconductor layer 71 and the second gate electrode 74 , the distance between the second semiconductor layer 75 and the second gate electrode 78 , and the distance between the second semiconductor layer 79 and the first gate electrode 64 are larger than the distance between the first semiconductor layer 61 and the first gate electrode 64 and the distance between the first semiconductor layer 65 and the first gate electrode 66 . In other words, capacitance Cox 2 per unit area is larger than capacitance Cox 1 per unit area. The capacitance Cox 1 per unit area is capacitance per unit area formed between the second semiconductor layers 71 , 75 , and 79 and the various gate electrodes (the second gate electrodes 74 and 78 and the first gate electrode 64 ), respectively. The capacitance Cox 2 per unit area is capacitance per unit area formed between the first semiconductor layers 61 and 65 and the first gate electrodes 64 and 66 , respectively. This configuration can prevent current leakage in the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST.

In the example illustrated in FIG. 5 , the transistors have what is called a bottom-gate structure. The transistors may have a top-gate structure in which the gate electrode is provided on the semiconductor layer. Alternatively, the transistors may have a dual-gate structure in which the gate electrodes are provided both on and under the semiconductor layer.

The coupling wiring L 9 , the source electrodes 62 and 72 , and a drain electrode 67 formed in the second metal layer ML 2 are provided on the third insulating film 93 . The source electrode 62 is electrically coupled to the first partial semiconductor layer 61 a (first semiconductor layer 61 ) through a contact hole formed in the second insulating film 92 and the third insulating film 93 . The source electrode 62 is also electrically coupled to the second partial semiconductor layer 79 a (second semiconductor layer 79 ) through a contact hole formed in the third insulating film 93 . As a result, the first semiconductor layer 61 and the second semiconductor layer 79 are electrically coupled.

The drain electrode 67 is electrically coupled to the first semiconductor layer 65 through a contact hole formed in the second insulating film 92 and the third insulating film 93 . The source electrode 72 is electrically coupled to the second semiconductor layer 71 through a contact hole formed in the third insulating film 93 .

One end of the coupling wiring L 9 is electrically coupled to the second semiconductor layer 75 of the pixel selection transistor SST through a contact hole formed in the third insulating film 93 . The part of the coupling wiring L 9 overlapping the second semiconductor layer 75 functions as a drain electrode 77 . The other end of the coupling wiring L 9 is electrically coupled to the second semiconductor layer 71 through a contact hole formed in the third insulating film 93 . The part of the coupling wiring L 9 overlapping the second semiconductor layer 71 functions as a drain electrode 73 . With this configuration, the drain of the pixel selection transistor SST and the drain of the initialization transistor IST are electrically coupled via the coupling wiring L 9 .

The fourth insulating film 94 is provided on the third insulating film 93 to cover the source electrodes 62 and 72 and the drain electrodes 67 , 73 , and 77 . The anode coupling electrode 24 and the shield electrode 26 are provided on the fourth insulating film 94 . The anode coupling electrode 24 is coupled to the source electrode 62 through a contact hole formed in the fourth insulating film 94 . The second capacitance Cs 2 (refer to FIG. 3 ) is formed between the anode coupling electrode 24 and the anode power supply line L 1 and various kinds of wiring coupled to the anode power supply line L 1 . The shield electrode 26 is provided under the anode electrode 23 and the light emitting element 3 .

The fifth insulating film 95 is provided on the fourth insulating film 94 to cover the anode coupling electrode 24 and the shield electrode 26 . The anode electrode 23 is provided on the fifth insulating film 95 . The anode electrode 23 is electrically coupled to the anode coupling electrode 24 through a contact hole formed in the fifth insulating film 95 .

The light emitting element 3 is provided on the anode electrode 23 , and the anode terminal 23 t of the light emitting element 3 is coupled to the anode electrode 23 . As a result, the anode terminal 23 t of the light emitting element 3 is electrically coupled to the source electrode 62 of the drive transistor DRT.

The flattening film 27 is provided on the fifth insulating film 95 to cover at least side surfaces 3 a of the light emitting element 3 . The cathode electrode 22 is provided on the flattening film 27 and coupled to the cathode terminal 22 t of the light emitting element 3 . The cathode electrode 22 is provided from the display region AA to the peripheral region GA and electrically coupled to the light emitting elements 3 of a plurality of pixels 49 .

As illustrated in FIG. 6 , the peripheral region GA of the substrate 21 is provided with the transistors Tr serving as a plurality of transistors included in the drive circuits 12 (refer to FIG. 1 ) and the cathode wiring 60 . The cathode wiring 60 is formed in the second metal layer ML 2 and provided on the third insulating film 93 in the peripheral region GA. The cathode electrode 22 illustrated in FIG. 5 is electrically coupled to the cathode wiring 60 . The cathode power supply line L 10 illustrated in FIG. 3 includes the cathode wiring 60 and the cathode electrode 22 .

The transistor Tr includes a semiconductor layer 81 , a source electrode 82 , a drain electrode 83 , and a gate electrode 84 . Detailed explanation of the transistor Tr is omitted herein because it has the same layer configuration as that of the transistors included in the pixel circuit PICA. The semiconductor layer 81 is provided on the second insulating film 92 , that is, in the same layer as that of the second semiconductor layers 71 , 75 , and 79 . The semiconductor layer 81 may be provided on the first insulating film 91 , that is, in the same layer as that of the first semiconductor layers 61 and 65 .

As illustrated in FIG. 6 , the anode power supply line L 1 , the video signal line L 2 , and the reset power supply line L 3 are provided on the third insulating film 93 . The width of the anode power supply line L 1 is larger than those of the video signal line L 2 and the reset power supply line L 3 . The thickness t 2 of the anode power supply line L 1 (second metal layer ML 2 ) is larger than the thickness t 1 (refer to FIG. 5 ) of the first gate electrode (first metal layer ML 1 ). The thickness t 2 of the anode power supply line L 1 is equal to the thickness of the video signal line L 2 and the reset power supply line L 3 . This configuration can reduce the resistance of the anode power supply line L 1 . The thickness t 2 of the anode power supply line L 1 may be different from the thickness of the video signal line L 2 and the reset power supply line L 3 .

The layer configuration of the wiring can be appropriately modified. The signal lines, such as the anode power supply line L 1 , the video signal line L 2 , and the reset power supply line L 3 , may be provided in different layers, for example.

The relative permittivity of the first insulating film 91 , the second insulating film 92 , and the third insulating film 93 according to the present embodiment is higher than that of the fourth insulating film 94 . The anode power supply line L 1 faces the various gate lines (the reset control signal line L 5 , the output control signal line L 6 , the pixel control signal line L 7 , and the initialization control signal line L 8 (refer to FIG. 4 )) with the first insulating film 91 , the second insulating film 92 , and the third insulating film 93 interposed therebetween. The first insulating film 91 , the second insulating film 92 , and the third insulating film 93 having high relative permittivity increase the capacitance formed between the anode power supply line L 1 and the various gate lines. The capacitance formed in the anode power supply line L 1 is used as a decoupling capacitor. The decoupling capacitor can absorb fluctuations in the anode power supply potential PVDD and enable the drive IC 210 to stably operate. In addition, the decoupling capacitor can prevent electromagnetic noise generated in the display device 1 from leaking outside.

As described above, the display device 1 according to the present embodiment includes the substrate 21 , the pixels 49 , the light emitting elements 3 and the transistors, the signal lines, the first semiconductor layers 61 and 65 and the second semiconductor layers 71 , 75 , and 79 , the first gate electrodes 64 and 66 , the first insulating film 91 , and the second insulating film 92 . The pixels 49 are provided to the substrate 21 . The light emitting element 3 and the transistors (the drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST) are provided to each of the pixels 49 . The signal lines (the video signal line L 2 , the reset power supply line L 3 , and the initialization power supply line L 4 ) supply signals to the pixels 49 . The first semiconductor layer 61 and the second semiconductor layer 79 are provided in different layers in the direction perpendicular to the substrate 21 and overlap at least partially in planar view. The first gate electrode 64 is provided in a region overlapping a part of the first semiconductor layer 61 . The first insulating film 91 is provided between the first gate electrode 64 and the first semiconductor layer 61 . The second insulating film 92 is provided between the first semiconductor layer 61 and the second semiconductor layers 71 and 75 .

In the display device 1 (array substrate 2 ), the first capacitance Cs 1 (refer to FIG. 3 ) is composed of the capacitance formed between the first semiconductor layer 61 and the first gate electrode 64 and the capacitance formed between the second semiconductor layer 79 and the first gate electrode 64 . The first semiconductor layer 61 and the second semiconductor layer 79 according to the present embodiment overlap in planar view. This configuration can reduce the area of the part that forms the first capacitance Cs 1 in the first semiconductor layer 61 and the second semiconductor layer 79 in planar view compared with the case where a single semiconductor layer and the first gate electrode 64 form the first capacitance Cs 1 . Consequently, the present embodiment can increase the flexibility in disposing the various kinds of wiring in one pixel 49 , thereby enabling efficiently disposing the wiring. Alternatively, the present embodiment can reduce the area of each pixel 49 in planar view, thereby increasing the resolution of the display device 1 .

The configuration of the pixel circuit PICA illustrated in FIG. 3 can be appropriately modified. The number of wires and the number of transistors in one pixel 49 may be different from those illustrated in FIG. 3 , for example. The pixel circuit PICA may be a current mirror circuit. Since a current mirror circuit has been described in Japanese Patent Application Laid-open Publication No. 2002-215093, for example, the present embodiment includes the related description in Japanese Patent Application Laid-open Publication No. 2002-215093, and thereby the explanation of the current mirror circuit is omitted herein.

FIG. 7 is a sectional view of the light emitting element according to the embodiment. In the display device 1 according to the present embodiment, the light emitting element 3 has what is called a face-up structure in which the anode terminal 23 t is provided at the lower part and the cathode terminal 22 t is provided at the upper part.

As illustrated in FIG. 7 , the light emitting element 3 includes a plurality of partial light emitting elements 3 s , a protective layer 39 , a p-type electrode 37 , and an n-type electrode 38 . The protective layer 39 covers the partial light emitting elements 3 s . The partial light emitting elements 3 s have a columnar shape and are provided between the p-type electrode 37 and the n-type electrode 38 . The partial light emitting elements 3 s each include an n-type cladding layer 33 , an active layer 34 , and a p-type cladding layer 35 . The n-type electrode 38 is electrically coupled to the n-type cladding layer 33 . The p-type electrode 37 is electrically coupled to the p-type cladding layer 35 . The p-type cladding layer 35 , the active layer 34 , and the n-type cladding layer 33 are layered in order on the p-type electrode 37 . The n-type cladding layer 33 , the active layer 34 , and the p-type cladding layer 35 are light emitting layers and are made of a compound semiconductor, such as gallium nitride (GaN) and aluminum indium phosphorus (AlInP).

The n-type electrode 38 is made of translucent conductive material, such as ITO. The n-type electrode 38 serves as the cathode terminal 22 t of the light emitting element 3 and is coupled to the cathode electrode 22 . The p-type electrode 37 serves as the anode terminal 23 t of the light emitting element 3 and includes a Pt layer 37 a and a thick Au layer 37 b produced by plating. The thick Au layer 37 b is coupled to a placement surface 23 a of the anode electrode 23 .

The protective layer 39 is spin on glass (SOG), for example. The side surfaces of the protective layer 39 correspond to the side surfaces 3 a of the light emitting element 3 . The flattening film 27 is provided surrounding the side surfaces of the protective layer 39 .

First Modification

FIG. 8 is a sectional view of the light emitting element according to a first modification of the embodiment. In the display device 1 , the light emitting element 3 does not necessarily have a face-up structure. Alternatively, the light emitting element 3 may have what is called a face-down structure in which the lower part of the light emitting element 3 is coupled to the anode electrode 23 and the cathode electrode 22 .

As illustrated in FIG. 8 , in a light emitting element 3 A, a buffer layer 32 , the n-type cladding layer 33 , the active layer 34 , the p-type cladding layer 35 , and a p-type electrode 36 are layered in order on a translucent substrate 31 . In the light emitting element 3 A, the translucent substrate 31 is provided at the upper part, and the p-type electrode 36 is provided at the lower part. The surface of the n-type cladding layer 33 facing the cathode electrode 22 has a region exposed from the active layer 34 . This region is provided with an n-type electrode 38 A.

The p-type electrode 36 is made of material having metallic luster that reflects light from the light emitting layers. The p-type electrode 36 is coupled to the anode electrode 23 with a bump 39 A interposed therebetween. The n-type electrode 38 A is coupled to the cathode electrode 22 with a bump 39 B interposed therebetween. An insulating film 97 covers the cathode electrode 22 and the anode electrode 23 . The bumps 39 A and 39 B are coupled to the anode electrode 23 and the cathode electrode 22 , respectively, through openings in the insulating film 97 .

In the light emitting element 3 A, the p-type cladding layer 35 and the n-type cladding layer 33 are not directly bonded, and another layer (active layer 34 ) is provided therebetween. With this configuration, carriers, such as electrons and holes, can be concentrated in the active layer 34 , thereby efficiently recombining the carriers (emitting light). The active layer 34 may have a multi-quantum well structure (MQW structure) in which well layers and barrier layers composed of several atomic layers are cyclically layered for higher efficiency.

Second Modification

FIG. 9 is a sectional view of the display device according to a second modification of the embodiment. A display device 1 A according to the present modification is different from the display device 1 in that the third insulating film 93 has a recess 93 a.

As illustrated in FIG. 9 , the anode power supply line L 1 is provided in the recess 93 a . In other words, the first insulating film 91 , the second insulating film 92 , and the third insulating film 93 have a first part 93 b overlapping the anode power supply line L 1 and a second part 93 c not overlapping the anode power supply line L 1 . The thickness t 3 of the first part 93 b is smaller than the thickness t 4 of the second part 93 c . In the present modification, the thicknesses t 3 and t 4 are the distance between the upper surface of the second insulating film 92 and the upper surface of the third insulating film 93 in the direction perpendicular to the substrate 21 .

This configuration increases the capacitance formed between the anode power supply line L 1 and the various gate lines. In other words, the capacitance used as a decoupling capacitor increases. The decoupling capacitor can absorb fluctuations in the anode power supply potential PVDD and enable the drive IC 210 to stably operate. In addition, the decoupling capacitor can prevent electromagnetic noise generated in the display device 1 from leaking outside.

The recess 93 a is not necessarily formed in the third insulating film 93 and may be formed in the first insulating film 91 or the second insulating film 92 . Also in this case, the thickness t 3 of the first part 93 b corresponding to the total thickness of the first insulating film 91 , the second insulating film 92 , and the third insulating film 93 is smaller than the thickness t 4 of the second part 93 c.

While an exemplary embodiment according to the present disclosure has been described, the embodiment is not intended to limit the disclosure. The contents disclosed in the embodiment are given by way of example only, and various changes may be made without departing from the spirit of the present disclosure. Appropriate changes made without departing from the spirit of the present disclosure naturally fall within the technical scope of the disclosure. At least one of various omissions, substitutions, and changes of the components may be made without departing from the gist of the embodiment above and the modifications thereof.