Semiconductor Devices Having Variously-shaped Source/drain Patterns

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 17/131,977, filed on Dec. 23, 2020, which in turn is a continuation of U.S. application Ser. No. 16/252,919, filed on Jan. 21, 2019, which claims the benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2018-0067354, filed on Jun. 12, 2018, in the Korean Intellectual Property Office, and the entire contents of each above-identified application are hereby incorporated by reference.

TECHNICAL FIELD

The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor devices having variously shaped source/drain patterns.

BACKGROUND

Semiconductor devices are beneficial in the electronic industry, and in other industries for many reasons, such as their small size, their multi-functionality, and/or their low fabrication cost. Semiconductor devices may encompass semiconductor memory devices storing logic data, semiconductor logic devices processing operations of logic data, and hybrid semiconductor devices having both memory and logic elements. The advancing development of the electronic industry and other industries has made semiconductor devices with increasing integration increasingly desirable. For example, semiconductor devices having high reliability, high speed, and/or multi-functionality have been increasingly requested. Semiconductor devices are becoming gradually more complicated and more integrated to meet these requested characteristics.

SUMMARY

The inventive concepts disclosed herein provide semiconductor devices with improved electrical characteristics.

According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a plurality of active patterns on a substrate; a device isolation layer defining the plurality of active patterns; a gate electrode extending across the plurality of active patterns; and a source/drain pattern on the plurality of active patterns. The plurality of active patterns may comprise: a first active pattern; and a second active pattern. The source/drain pattern may comprise: a first part on the first active pattern; a second part on the second active pattern; and a third part extending from the first part and along an upper portion of the first active pattern. The device isolation layer may comprise a first outer segment on a sidewall of the first active pattern and below the source/drain pattern. A lowermost level of a bottom surface of the third part of the source/drain pattern may be lower than an uppermost level of a top surface of the first outer segment.

According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a plurality of active patterns on a substrate; a device isolation layer defining the plurality of active patterns; a gate electrode extending across the active patterns; and a source/drain pattern on the plurality of active patterns. The plurality of active patterns may comprise first, second, and third active patterns. The second active pattern may be between the first and third active patterns. The source/drain pattern may comprise: a first part on the first active pattern; a second part on the second active pattern; and a third part on the third active pattern. The first, second, and third parts of the source/drain pattern may be merged with each other. A first valley having a first depth may be defined between the first and second parts of the source/drain pattern. A second valley having a second depth may be defined between the second and third parts of the source/drain pattern. The second depth may be less than the first depth.

According to some example embodiments of the present inventive concepts, a semiconductor device may comprise: a substrate; first, second, and third active patterns on the substrate; a gate electrode extending across the first, second, and third active patterns; and a source/drain pattern on the first, second, and third active patterns. The source/drain pattern may comprise first, second, and third parts respectively on the first, second, and third active patterns. The first and second parts of the source/drain pattern may be spaced apart from each other. The second and third parts of the source/drain pattern may be merged with each other. A lowermost level of a bottom surface of the second part of the source/drain pattern may be lower than a lowermost level of a bottom surface of the third part of the source/drain pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 A, 2 A, 3 A, and 4 A illustrate plan views showing operations in methods of manufacturing semiconductor devices, according to some of the present inventive concepts.

FIGS. 1 B, 2 B, 3 B, and 4 B illustrate cross-sectional views taken along line A-A′ of FIGS. 1 A, 2 A, 3 A, and 4 A , respectively.

FIGS. 2 C, 3 C, and 4 C illustrate cross-sectional views taken along line B-B′ of FIGS. 2 A, 3 A, and 4 A , respectively.

FIGS. 2 D, 3 D, and 4 D illustrate cross-sectional views taken along line C-C′ of FIGS. 2 A, 3 A, and 4 A , respectively.

FIG. 5 illustrates a cross-sectional view taken along line A-A′ of FIG. 4 A .

FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A illustrate plan views showing operations of methods of manufacturing semiconductor devices, according to some of the present inventive concepts.

FIGS. 6 B, 7 B, 8 B, 9 B, 10 B, and 11 B illustrate cross-sectional views taken along line A-A′ of FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A , respectively.

FIGS. 7 C, 8 C, 9 C, 10 C, and 11 C illustrate cross-sectional views taken along line B-B′ of FIGS. 7 A, 8 A, 9 A, 10 A, and 11 A , respectively.

FIGS. 7 D, 8 D, 9 D, 10 D, and 11 D illustrate cross-sectional views taken along line C-C′ of FIGS. 7 A, 8 A, 9 A, 10 A, and 11 A , respectively.

DETAILED DESCRIPTION

FIGS. 1 A, 2 A, 3 A, and 4 A illustrate plan views showing operations of methods of manufacturing semiconductor devices according to some of the present inventive concepts. FIGS. 1 B, 2 B, 3 B, and 4 B illustrate cross-sectional views taken along line A-A′ of FIGS. 1 A, 2 A, 3 A, and 4 A , respectively. FIGS. 2 C, 3 C, and 4 C illustrate cross-sectional views taken along line B-B′ of FIGS. 2 A, 3 A, and 4 A , respectively. FIGS. 2 D, 3 D, and 4 D illustrate cross-sectional views taken along line C-C′ of FIGS. 2 A, 3 A, and 4 A , respectively.

Referring to FIGS. 1 A and 1 B , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate, or may include a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

A device isolation layer ST may be formed on the substrate 100 . The formation of the device isolation layer ST may include patterning the substrate 100 to form trenches defining first to fourth active patterns AP 1 to AP 4 , forming an insulation layer on an entire surface of the substrate 100 , and recessing the insulation layer. The device isolation layer ST may have a top surface lower than those of the first to fourth active patterns AP 1 to AP 4 .

The device isolation layer ST may define the first to fourth active patterns AP 1 to AP 4 on an upper portion of the substrate 100 . Each of the first to fourth active patterns AP 1 to AP 4 may have a linear or bar shape extending in a second direction D 2 .

The first to fourth active patterns AP 1 to AP 4 may be sequentially arranged along a first direction D 1 . The first to fourth active patterns AP 1 to AP 4 may be spaced apart from each other in the first direction D 1 . In some embodiments, the first to fourth active patterns AP 1 to AP 4 may be equally spaced apart from each other in the first direction D 1 . The first and fourth active patterns AP 1 and AP 4 may be active patterns positioned at outermost positions. For example, the first and fourth active patterns AP 1 and AP 4 may be outermost active patterns. The second and third active patterns AP 2 and AP 3 may be between the first and fourth active patterns AP 1 and AP 4 . For example, the second and third active patterns AP 2 and AP 3 may be inner active patterns. The first active pattern AP 1 may include a first sidewall SW 1 and a second sidewall SW 2 . The first sidewall SW 1 may face the second active pattern AP 2 . The second sidewall SW 2 may stand opposite to the first sidewall SW 1 . The fourth active pattern AP 4 may include a third sidewall SW 3 and a fourth sidewall SW 4 . The third sidewall SW 3 may face the third active pattern AP 3 . The fourth sidewall SW 4 may stand opposite to the third sidewall SW 3 . The second active pattern AP 2 and the third active pattern AP 3 may have sidewalls, which are unlabeled in FIG. 1 B .

The device isolation layer ST may include outer segments ST 1 and intermediate segments ST 2 . The outer segments ST 1 may be formed on the second sidewall SW 2 of the first active pattern AP 1 and on the fourth sidewall SW 4 of the fourth active pattern AP 4 . The intermediate segments ST 2 may be formed between the first and second active patterns AP 1 and AP 2 , between the second and third active patterns AP 2 and AP 3 , and between the third and fourth active patterns AP 3 and AP 4 .

Referring to FIGS. 2 A to 2 D , sacrificial patterns PP may be formed to run across the first to fourth active patterns AP 1 to AP 4 . Each of the sacrificial patterns PP may have a linear or bar shape extending in the first direction D 1 . Each of the sacrificial patterns PP may be perpendicular to the first through fourth active patterns AP 1 to AP 4 , when viewed in a plan view.

The formation of the sacrificial patterns PP may include forming a sacrificial layer on the substrate 100 , forming mask patterns MP on the sacrificial layer, and using the mask patterns MP as an etching mask to etch the sacrificial layer. The sacrificial layer may be formed using polysilicon. The mask patterns MP may be formed using a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. For example, the gate spacers GS may include one or more of SiCN, SiCON, and SiN. For another example, the gate spacers GS may include a multiple layer consisting of two or more of SiCN, SiCON, and SiN.

The formation of the gate spacers GS may include performing a deposition process, such as CVD or ALD, to form a spacer layer on the entire surface of the substrate 100 , and performing an anisotropic etching process on the spacer layer.

The mask patterns MP and the gate spacers GS may be used as an etching mask to etch the first to fourth active patterns AP 1 to AP 4 . The first to fourth active patterns AP 1 to AP 4 may be etched to form recesses RS, as best seen in FIG. 2 D .

The device isolation layer ST may be etched at the same time when the first to fourth active patterns AP 1 to AP 4 are etched. The outer segment ST 1 of the device isolation layer ST may have an etched top surface at a level lower than that of an etched top surface of the intermediate segment ST 2 of the device isolation layer ST. The second sidewall SW 2 of the first active pattern AP 1 and the fourth sidewall SW 4 of the fourth active pattern AP 4 may be partially exposed by the outer segments ST 1 of the device isolation layer ST, as best seen in FIG. 2 B .

Referring to FIGS. 3 A to 3 D , source/drain patterns SD may be formed to fill the recesses RS. The formation of the source/drain patterns SD may include performing a selective epitaxial growth process in which the first to fourth active patterns AP 1 to AP 4 are used as seed layers. After the selective epitaxial growth process, the source/drain patterns SD may be doped with P-type impurities or N-type impurities. The source/drain pattern SD may have a flat top surface.

Each of the source/drain patterns SD may include first to sixth parts SDP 1 to SDP 6 , as best seen in FIG. 3 B . The first part SDP 1 may be formed on the first active pattern AP 1 , the second part SDP 2 may be formed on the second active pattern AP 2 , the third part SDP 3 may be formed on the third active pattern AP 3 , and the fourth part SDP 4 may be formed on the fourth active pattern AP 4 . The first to fourth parts SDP 1 to SDP 4 may be formed on respective upper surfaces of the first to fourth active patterns AP 1 to AP 4 . The first to fourth parts SDP 1 to SDP 4 may be connected to each other. For example, the first to fourth parts SDP 1 to SDP 4 may be merged with each other.

The fifth part SDP 5 may be formed on the second sidewall SW 2 of the first active pattern AP 1 . The fifth part SDP 5 may extend from the first part SDP 1 and along an upper portion of the second sidewall SW 2 . The fifth part SDP 5 may have a bottom surface whose lowermost level is lower than a lowermost level of the top surface of each of the intermediate segments ST 2 between the first to fourth active patterns AP 1 to AP 4 below the source/drain pattern SD. The lowermost level of the bottom surface of the fifth part SDP 5 may be lower than an uppermost level of the top surface of the outer segment ST 1 on the second sidewall SW 2 of the first active pattern AP 1 below the source/drain pattern SD. The fifth part SDP 5 may partially cover the top surface of the outer segment ST 1 on the second sidewall SW 2 of the first active pattern AP 1 . The top surfaces of the first to fourth active patterns AP 1 to AP 4 below the source/drain pattern SD may be located at a first level LV 1 . The lowermost level of the bottom surface of the fifth part SDP 5 may be lower than the first level LV 1 .

The sixth part SDP 6 may be formed on the fourth sidewall SW 4 of the fourth active pattern AP 4 . The sixth part SDP 6 may extend from the fourth part SDP 4 and along an upper portion the fourth sidewall SW 4 . The sixth part SDP 6 may have a bottom surface whose lowermost level is lower than the lowermost level of the top surface of each of the intermediate segments ST 2 between the first to fourth active patterns AP 1 to AP 4 below the source/drain pattern SD. The lowermost level of the bottom surface of the sixth part SDP 6 may be lower than an uppermost level of the top surface of the outer segment ST 1 on the fourth sidewall SW 4 of the fourth active pattern AP 4 below the source/drain pattern SD. The sixth part SDP 6 may partially cover a top surface of the outer segment ST 1 on the fourth sidewall SW 4 of the fourth active pattern AP 4 . The lowermost level of the bottom surface of the sixth part SDP 6 may be lower than the first level LV 1 . In some embodiments, the source/drain pattern SD may differ from that shown, and may include one, or only one, of the fifth and sixth parts SDP 5 and SDP 6 .

Voids VO may be formed between the source/drain pattern SD and the intermediate segments ST 2 of the device isolation layer ST. For example, a void VO may be formed between the third active pattern AP 3 and the fourth active pattern AP 4 , above the intermediate segment ST 2 between the third active pattern AP 3 and the fourth active pattern AP 4 , and below the source/drain pattern SD (and more specifically, below a portion of the third part SDP 3 and below a portion of the fourth part SDP 4 ). The voids VO may be substantially empty spaces. The voids VO may be filled with air.

Referring to FIGS. 4 A to 4 D , a first interlayer dielectric layer 110 may be formed on the substrate 100 . A planarization process may be performed on the first interlayer dielectric layer 110 until top surfaces of the sacrificial patterns PP are exposed. The planarization process may include an etch-back process and/or a chemical mechanical polishing (CMP) process. When the first interlayer dielectric layer 110 is planarized, the mask patterns MP may be removed. The first interlayer dielectric layer 110 may include, for example, a silicon oxide layer or a silicon oxynitride layer.

The planarization process may remove the exposed sacrificial patterns PP. The removal of the sacrificial patterns PP may form empty spaces each of which is provided between a pair of neighboring gate spacers GS. The empty spaces may expose the first to fourth active patterns AP 1 to AP 4 .

A gate dielectric pattern GI and a gate electrode GE may be formed in each of the empty spaces. The formation of the gate dielectric pattern GI and the gate electrode GE may include forming a gate dielectric layer on surfaces in the empty space, partially filling the empty space, and forming a gate electrode layer to completely fill the empty space. The filling of the empty space with the gate electrode layer may form the gate electrode GE. The gate dielectric layer may include a high-k dielectric material. The high-k dielectric material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate electrode layer may include, for example, one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

Gate capping patterns CP may be formed on the gate electrodes GE. The gate capping pattern CP may include a material having an etch selectivity with respect to the first interlayer dielectric layer 110 . The gate capping patterns CP may include, for example, one or more of SiON, SiCN, SiCON, and SiN.

A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110 and the gate capping patterns CP. The second interlayer dielectric layer 120 may include, for example, a silicon oxide layer or a silicon oxynitride layer.

Contacts CT may be formed to penetrate the first and second interlayer dielectric layers 110 and 120 and to come into connection with the source/drain patterns SD. For example, the contacts CT may include metal, such as titanium, tantalum, tungsten, copper, or aluminum.

A third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120 and the contacts CT. The third interlayer dielectric layer 130 may include, for example, a silicon oxide layer or a silicon oxynitride layer.

Via contacts V 1 and wiring lines M 1 may be formed in the third interlayer dielectric layer 130 . The via contact V 1 may electrically connect the wiring line M 1 and the contact CT to each other. Each of the via contact V 1 and the wiring line M 1 may include metal whose resistance is low. The low resistance metal may be or include, for example, copper or tungsten. The wiring line M 1 may be provided on the via contact V 1 . The wiring line M 1 may extend in the second direction D 2 . The wiring lines M 1 may be spaced apart from each other in the first direction D 1 .

A semiconductor device according to some example embodiments of the present inventive concepts will now be described, with reference to FIGS. 4 A to 4 D .

The device isolation layer ST may be provided on the substrate 100 . The device isolation layer ST may define the first to fourth active patterns AP 1 to AP 4 on an upper portion of the substrate 100 . The device isolation layer ST may have a top surface lower than those of the first to fourth active patterns AP 1 to AP 4 .

The first to fourth active patterns AP 1 to AP 4 may be sequentially arranged along the first direction D 1 . Each of the first to fourth active patterns AP 1 to AP 4 may extend in the second direction D 2 . The recesses RS may be correspondingly provided on the first to fourth active patterns AP 1 to AP 4 .

The device isolation layer ST may include the outer segments ST 1 and the intermediate segments ST 2 . The outer segment ST 1 of the device isolation layer ST may have a top surface at a level lower than that of a top surface of the intermediate segment ST 2 of the device isolation layer ST. The top surface of the outer segment ST 1 on the second sidewall SW 2 of the first active pattern AP 1 may become lower with increasing distance from the first active pattern AP 1 . The top surface of the outer segment ST 1 on the fourth sidewall SW 4 of the fourth active pattern AP 4 may become lower with increasing distance from the fourth active pattern AP 4 .

The source/drain patterns SD may be provided on the first to fourth active patterns AP 1 to AP 4 . The source/drain patterns SD may fill the recesses RS. Each of the source/drain patterns SD may include the first to sixth parts SDP 1 to SDP 6 . The first to fourth parts SDP 1 to SDP 4 may be merged with each other. The fifth part SDP 5 may extend from the first part SDP 1 and along the second sidewall SW 2 of the first active pattern AP 1 . The sixth part SDP 6 may extend from the fourth part SDP 4 and along the fourth sidewall SW 4 of the fourth active pattern AP 4 .

The gate electrodes GE may extend in the first direction D 1 , while running across the first to fourth active patterns AP 1 to AP 4 . The gate electrodes GE may be spaced apart from each other in the second direction D 2 . For example, the gate electrode GE may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D 1 along the gate electrode GE. The gate spacers GS may have top surfaces higher than that of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with that of the first interlayer dielectric layer 110 .

The gate dielectric pattern GI may be interposed between each of the gate electrodes GE and each of the first to fourth active patterns AP 1 to AP 4 . The gate dielectric pattern GI may lie between the gate electrode GE and each of the gate spacers GS. The gate dielectric pattern GI may include a high-k dielectric material. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The gate capping pattern CP may be provided on each of the gate electrodes GE. The gate capping pattern CP may extend in the first direction D 1 along the gate electrode GE.

The first interlayer dielectric layer 110 may be provided on an entire surface of the substrate 100 . The first interlayer dielectric layer 110 may cover the device isolation layer ST, the gate electrodes GE, and the source/drain patterns SD. The first interlayer dielectric layer 110 may have a top surface substantially coplanar with those of the gate capping patterns CP. The second interlayer dielectric layer 120 may be provided on the first interlayer dielectric layer 110 .

The contacts CT may extend at least partially into the first and second interlayer dielectric layers 110 and 120 and come into connection with the source/drain patterns SD.

The third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120 and the contacts CT. The via contacts V 1 and the wiring lines M 1 may be provided in the third interlayer dielectric layer 130 .

A semiconductor device according to some example embodiments of the present inventive concepts will now be described, with reference to FIGS. 4 A, 4 C, 4 D, and 5 . FIG. 5 illustrates a cross-sectional view taken along line A-A′ of FIG. 4 A of a semiconductor device according to an example of an embodiment. For brevity of description, components substantially the same as those discussed with reference to FIGS. 4 A to 4 D are allocated the same reference numerals thereto, and repetitive explanations thereof may be omitted in favor of the description provided above.

The device isolation layer ST may be provided on the substrate 100 . The device isolation layer ST may define the first to fourth active patterns AP 1 to AP 4 on an upper portion of the substrate 100 . Each of the outer segments ST 1 of the device isolation layer ST may have a top surface at a level substantially the same as or similar to that of a top surface of each of the intermediate segments ST 2 of the device isolation layer ST. For example, the level of the top surface of each outer segment ST 1 of FIG. 5 may be higher than the top surface of each outer segment ST 1 of FIG. 2 B . The recesses RS may be correspondingly provided on the first to fourth active patterns AP 1 to AP 4 .

The source/drain patterns SD may be provided on the first to fourth active patterns AP 1 to AP 4 . Each of the source/drain patterns SD may include the first to fourth parts SDP 1 to SDP 4 . The first part SDP 1 may be formed on the first active pattern AP 1 , the second part SDP 2 may be formed on the second active pattern AP 2 , the third part SDP 3 may be formed on the third active pattern AP 3 , and the fourth part SDP 4 may be formed on the fourth active pattern AP 4 . The first to fourth parts SDP 1 to SDP 4 may be connected to each other. For example, the first to fourth parts SDP 1 to SDP 4 may be merged with each other. According to the present example embodiment, the source/drain patterns SD may not include the fifth and sixth parts SDP 5 and SDP 6 discussed above with reference to FIGS. 3 A to 3 D .

The first and second parts SDP 1 and SDP 2 may define a first valley VA 1 . For example, the first valley VA 1 may be defined by top surfaces of the first and second parts SDP 1 and SDP 2 . The first valley VA 1 may cause the source/drain pattern SD to have a non-flat top surface that connects an uppermost portion of the first part SDP 1 to an uppermost portion of the second part SDP 2 . The first valley VA 1 may cause the source/drain pattern SD to have a non-flat top surface between an uppermost portion of the first part SDP 1 and an uppermost portion of the second part SDP 2 . The first valley VA 1 may be interposed between the first and second parts SDP 1 and SDP 2 . The first valley VA 1 may have a first depth D 1 . The first depth D 1 may correspond to a height between a bottom VA 1 B of the first valley VA 1 and the uppermost portion of the first part SDP 1 and/or the second part SDP 2 . The bottom VA 1 B of the first valley VA 1 may be located at a level lower than that of the uppermost portion of the first part SDP 1 and that of the uppermost portion of the second part SDP 2 .

The second and third parts SDP 2 and SDP 3 may define a second valley VA 2 . For example, the second valley VA 2 may be defined by top surfaces of the second and third parts SDP 2 and SDP 3 . The second valley VA 2 may cause the source/drain pattern SD to have a non-flat top surface that connects the uppermost portion of the second part SDP 2 to an uppermost portion of the third part SDP 3 . The second valley VA 2 may cause the source/drain pattern SD to have a non-flat top surface between the uppermost portion of the second part SDP 2 and an uppermost portion of the third part SDP 3 . The second valley VA 2 may be interposed between the second and third parts SDP 2 and SDP 3 . The second valley VA 2 may have a second depth D 2 . The second depth D 2 may correspond to a height between a bottom VA 2 B of the second valley VA 2 and the uppermost portion of the second part SDP 2 and/or the third part SDP 3 . The second depth D 2 may be less than the first depth D 1 . The bottom VA 2 B of the second valley VA 2 may be located at a level lower than that of the uppermost portion of the second part SDP 2 and that of the uppermost portion of the third part SDP 3 . The level of the bottom VA 2 B of the second valley VA 2 may be higher than the level of the bottom VA 1 B of the first valley VA 1 .

The source/drain pattern SD may have a flat top surface that connects the uppermost portion of the third part SDP 3 to an uppermost portion of the fourth part SDP 4 . For example, no valley may be formed between the third and fourth parts SDP 3 and SDP 4 .

The gate electrodes GE may be provided to extend in the first direction D 1 , while running across the first to fourth active patterns AP 1 to AP 4 . A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate dielectric pattern GI may be interposed between each of the gate electrodes GE and each of the first to fourth active patterns AP 1 to AP 4 . The gate dielectric pattern GI may lie between the gate electrode GE and each of the gate spacers GS. The gate capping pattern CP may be provided on each of the gate electrodes GE.

The first interlayer dielectric layer 110 may be provided on an entire surface of the substrate 100 . The second interlayer dielectric layer 120 may be provided on the first interlayer dielectric layer 110 .

The contacts CT may extend at least partially into the first and second interlayer dielectric layers 110 and 120 and to come into connection with the source/drain patterns SD.

The third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120 and the contacts CT. The via contacts V 1 and the wiring lines M 1 may be provided in the third interlayer dielectric layer 130 .

FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A illustrate plan views showing a method of manufacturing a semiconductor device according to some example embodiments of the present inventive concepts. FIGS. 6 B, 7 B, 8 B, 9 B, 10 B, and 11 B illustrate cross-sectional views taken along line A-A′ of FIGS. 6 A, 7 A, 8 A, 9 A, 10 A, and 11 A , respectively. FIGS. 7 C, 8 C, 9 C, 10 C , and 11 C illustrate cross-sectional views taken along line B-B′ of FIGS. 7 A, 8 A, 9 A, 10 A, and 11 A , respectively. FIGS. 7 D, 8 D, 9 D, 10 D, and 11 D illustrate cross-sectional views taken along line C-C′ of FIGS. 7 A, 8 A, 9 A, 10 A, and 11 A , respectively.

For brevity of description, components substantially the same as those discussed with reference to FIGS. 1 A to 4 D are allocated the same reference numerals thereto, and a repetitive explanation thereof may be omitted herein in favor of the explanation provided above.

Referring to FIGS. 6 A and 6 B , a substrate 100 may be provided. The substrate 100 may include a first region RG 1 and a second region RG 2 .

A device isolation layer ST may be formed on the substrate 100 . The formation of the device isolation layer ST may include patterning the first and second regions RG 1 and RG 2 to form trenches that define first to fourth active patterns AP 1 to AP 4 on the first region RG 1 and also define fifth to eighth active patterns AP 5 to AP 8 on the second region RG 2 , forming an insulation layer on an entire surface of the substrate 100 , and then recessing the insulation layer. The device isolation layer ST may have a top surface lower than those of the first to eighth active patterns AP 1 to AP 8 .

The device isolation layer ST may define the first to eighth active patterns AP 1 to AP 8 on an upper portion of the substrate 100 . Each of the first to eighth active patterns AP 1 to AP 8 may have a linear or bar shape extending in a second direction D 2 .

The first to eighth active patterns AP 1 to AP 8 may be sequentially arranged along a first direction D 1 . The first to eighth active patterns AP 1 to AP 8 may be spaced apart from each other in the first direction D 1 .

Referring to FIGS. 7 A to 7 D , sacrificial patterns PP may be formed to run across the first to eighth active patterns AP 1 to AP 8 . Each of the sacrificial patterns PP may be perpendicular to the first to eighth active patterns AP 1 to AP 8 , when viewed in a plan view. The formation of the sacrificial patterns PP may include forming a sacrificial layer on the substrate 100 , forming mask patterns MP on the sacrificial layer, and using the mask patterns MP as an etching mask to etch the sacrificial layer.

A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. A pair of insulation spacers IS may be formed on opposite sidewalls of each of the first to eighth active patterns AP 1 to AP 8 . The gate spacers GS and the insulation spacers IS may be formed at the same time. The gate spacers GS and the insulation spacers IS may include the same material. For example, the gate spacers GS and the insulation spacers IS may each include one or more of SiCN, SiCON, and SiN. For another example, the gate spacers GS and the insulation spacers IS may each include a multiple layer consisting of two or more of SiCN, SiCON, and SiN.

The formation of the gate spacers GS and the insulation spacers IS may include performing a deposition process, such as CVD or ALD, to form a spacer layer on the entire surface of the substrate 100 , and performing an anisotropic etching process on the spacer layer.

Referring to FIGS. 8 A to 8 D , the first to fourth active patterns AP 1 to AP 4 on the first region RG 1 of the substrate 100 may be etched to form first recesses RS 1 . The first recesses RS 1 are best seen in FIG. 8 D . The etching of the first to fourth active patterns AP 1 to AP 4 may include coating a first photoresist layer on the entire surface of the substrate 100 , patterning the first photoresist layer by a first photolithography process to form a first photoresist pattern PR 1 , and using the first photoresist pattern PR 1 as an etching mask to etch the first to fourth active patterns AP 1 to AP 4 .

The insulation spacers IS may include first to fourth insulation spacers IS 1 to IS 4 . The first to fourth insulation spacers IS 1 to IS 4 may be formed on opposite sidewalls of the first to fourth active patterns AP 1 to AP 4 , respectively.

When the first to fourth active patterns AP 1 to AP 4 are etched, the first to fourth insulation spacers IS 1 to IS 4 may also be etched. The first to fourth insulation spacers IS 1 to IS 4 may have different etching degrees from each other. In such cases, the first to fourth insulation spacers IS 1 to IS 4 may have different maximum heights from each other. For example, the maximum heights of the first insulation spacers IS 1 on the opposite sidewalls of the first active pattern AP 1 may be greater than the maximum heights of the second insulation spacers IS 2 on the opposite sidewalls of the second active pattern AP 2 . The maximum heights of the third insulation spacers IS 3 on the opposite sidewalls of the third active pattern AP 3 may be greater than the maximum heights of the first insulation spacers IS 1 . The first insulation spacers IS 1 may partially expose the sidewalls of the first active pattern AP 1 . The second insulation spacers IS 2 may partially expose the sidewalls of the second active pattern AP 2 .

A first trench TR 1 may be formed at the same time when the first to fourth active patterns AP 1 to AP 4 are etched. The first trench TR 1 may be formed by etching the device isolation layer ST between the fourth and fifth active patterns AP 4 and AP 5 . For example, a portion of the device isolation layer ST that is adjacent to the fourth active pattern AP 4 may be etched, which may result in the formation of the first trench TR 1 . The first trench TR 1 may extend in the second direction D 2 .

Referring to FIGS. 9 A to 9 D , the fifth to eighth active patterns AP 5 to AP 8 on the second region RG 2 of the substrate 100 may be etched to form second recesses RS 2 . The etching of the fifth to eighth active patterns AP 5 to AP 8 may include coating a second photoresist layer on the entire surface of the substrate 100 , patterning the second photoresist layer by a second photolithography process to form a second photoresist pattern PR 2 , and using the second photoresist pattern PR 2 as an etching mask to etch the fifth to eighth active patterns AP 5 to AP 8 .

The insulation spacers IS may include fifth to eighth insulation spacers IS 5 to IS 8 . The fifth to eighth insulation spacers IS 5 to IS 8 may be formed on opposite sidewalls of the fifth to eighth active patterns AP 5 to AP 8 , respectively.

When the fifth to eighth active patterns AP 5 to AP 8 are etched, the fifth to eighth insulation spacers IS 5 to IS 8 may also be etched. The fifth to eighth insulation spacers IS 5 to IS 8 may have different etching degrees from each other. In such cases, the fifth to eighth insulation spacers IS 5 to IS 8 may have different maximum heights from each other. For example, the maximum heights of the fifth insulation spacers IS 5 on the opposite sidewalls of the fifth active pattern AP 5 may be greater than the maximum heights of the sixth insulation spacers IS 6 on the opposite sidewalls of the sixth active pattern AP 6 . The maximum heights of the seventh insulation spacers IS 7 on the opposite sidewalls of the seventh active pattern AP 7 may be greater than the maximum heights of the fifth insulation spacers IS 5 . The fifth insulation spacers IS 5 may partially expose the sidewalls of the fifth active pattern AP 5 . The sixth insulation spacers IS 6 may partially expose the sidewalls of the sixth active pattern AP 6 .

A second trench TR 2 may be formed at the same time when the fifth to eighth active patterns AP 5 to AP 8 are formed. The second trench TR 2 may be formed by etching the device isolation layer ST between the first trench TR 1 and the fifth active pattern AP 5 . For example, a portion of the device isolation layer ST that is adjacent to the fifth active pattern AP 5 may be etched, which may result in the formation of the second trench TR 2 . The second trench TR 2 may extend in the second direction D 2 .

The first and second trenches TR 1 and TR 2 may define a protrusion PT therebetween, as best seen in FIG. 9 B . The protrusion PT may be a portion of the device isolation layer ST provided between the first and second trenches TR 1 and TR 2 . The protrusion PT may extend in the second direction D 2 .

A first length L 1 may refer to a shortest distance in the first direction D 1 between the fourth active pattern AP 4 and an uppermost portion of the protrusion PT. A second length L 2 may refer to a shortest distance in the first direction D 1 between the fifth active pattern AP 5 and the uppermost portion of the protrusion PT. Stated differently, a first length L 1 may refer to a shortest distance in the first direction D 1 from the uppermost portion of the protrusion PT to the active pattern on the first region RG 1 that is closest to the protrusion PT, and a second length L 2 may refer to a shortest direction in the first direction D 1 from the uppermost portion of the protrusion PT to the active pattern on the second region RG 2 that is closest to the protrusion PT. For example, as shown in FIG. 9 B , the first length L 1 may be less than the second length L 2 . For another example, differently from that shown in FIG. 9 B , the first length L 1 may be the same as or greater than the second length L 2 .

Referring to FIGS. 10 A to 10 D , first source/drain patterns SD 1 may be formed to fill the first recesses RS 1 . The formation of the first source/drain patterns SD 1 may include performing a selective epitaxial growth process in which the first to fourth active patterns AP 1 to AP 4 are used as seed layers. Simultaneously with or after the selective epitaxial growth process to form the first source/drain patterns SD 1 , the first source/drain patterns SD 1 may be doped with P-type impurities.

Second source/drain patterns SD 2 may be formed to fill the second recesses RS 2 . The formation of the second source/drain patterns SD 2 may include performing a selective epitaxial growth process in which the fifth to eighth active patterns AP 5 to AP 8 are used as seed layers. The formation of the second source/drain patterns SD 2 may be formed simultaneously with the formation of the first source/drain patterns SD 1 , but the present disclosure is not limited thereto. Simultaneously with or after the selective epitaxial growth process to form the second source/drain patterns SD 2 , the second source/drain patterns SD 2 may be doped with N-type impurities.

Each of the first source/drain patterns SD 1 may include first to fourth parts SD 1 P 1 to SD 1 P 4 . The first part SD 1 P 1 may be formed on the first active pattern AP 1 , the second part SD 1 P 2 may be formed on the second active pattern AP 2 , the third part SD 1 P 3 may be formed on the third active pattern AP 3 , and the fourth part SD 1 P 4 may be formed on the fourth active pattern AP 4 . The first part SD 1 P 1 may be spaced apart from the second part SD 1 P 2 . The fourth part SD 1 P 4 may be spaced apart from the third part SD 1 P 3 . The second part SD 1 P 2 may be merged with the third part SD 1 P 3 . The second and third parts SD 1 P 2 and SD 1 P 3 may have therebetween a boundary at a location where the second and third parts SD 1 P 2 and SD 2 P 3 are connected to each other while being selectively epitaxially grown. The first to fourth parts SD 1 P 1 to SD 1 P 4 may have their uppermost portions at the same level.

The first part SD may have a first width W 1 corresponding to a maximum width in the first direction D 1 and a first height H 1 corresponding to a maximum height in a third direction D 3 . The second part SD 1 P 2 may have a second width W 2 corresponding to a maximum width in the first direction D 1 and a second height H 2 corresponding to a maximum height in the third direction D 3 . The third part SD 1 P 3 may have a third width W 3 corresponding to a maximum width in the first direction D 1 and a third height H 3 corresponding to a maximum height in the third direction D 3 . The fourth part SD 1 P 4 may have a fourth width W 4 corresponding to a maximum width in the first direction D 1 and a fourth height H 4 corresponding to a maximum height in the third direction D 3 .

The second width W 2 may be greater than the first width W 1 , and the second height H 2 may be greater than the first height H 1 . For example, the second part SD 1 P 2 may have a size greater than that of the first part SD 1 P 1 . The second part SD 1 P 2 may have a bottom surface whose lowermost level is lower than a lowermost level of a bottom surface of the first part SD 1 P 1 . The third width W 3 may be less than the second width W 2 , and the third height H 3 may be less than the second height H 2 . For example, the third part SD 1 P 3 may have a size less than that of the second part SD 1 P 2 . The lowermost level of the bottom surface of the second part SD 1 P 2 may be lower than a lowermost level of a bottom surface of the third part SD 1 P 3 . The fourth width W 4 may be less than the second width W 2 , and the fourth height H 4 may be less than the second height H 2 . For example, the fourth part SD 1 P 4 may have a size less than that of the second part SD 1 P 2 . The lowermost level of the bottom surface of the second part SD 1 P 2 may be lower than a lowermost level of a bottom surface of the fourth part SD 1 P 4 .

Each of the second source/drain patterns SD 2 may include fifth to eighth parts SD 2 P 5 to SD 2 P 8 . The fifth part SD 2 P 5 may be formed on the fifth active pattern AP 5 , the sixth part SD 2 P 6 may be formed on the sixth active pattern AP 6 , the seventh part SD 2 P 7 may be formed on the seventh active pattern AP 7 , and the eighth part SD 2 P 8 may be formed on the eighth active pattern APB. The fifth part SD 2 P 5 may be spaced apart from the sixth part SD 2 P 6 . The eighth part SD 2 P 8 may be spaced apart from the seventh part SD 2 P 7 . The sixth part SD 2 P 6 may be merged with the seventh part SD 2 P 7 . The sixth and seventh parts SD 2 P 6 and SD 2 P 7 may have therebetween a boundary at a location where the sixth and seventh parts SD 2 P 6 and SD 2 P 7 are connected to each other while being selectively epitaxially grown. The fifth to eighth parts SD 2 P 5 to SD 2 P 8 may have their uppermost portions at the same level.

The fifth part SD 2 P 5 may have a fifth width W 5 corresponding to a maximum width in the first direction D 1 and a fifth height H 5 corresponding to a maximum height in the third direction D 3 . The sixth part SD 2 P 6 may have a sixth width W 6 corresponding to a maximum width in the first direction D 1 and a sixth height H 6 corresponding to a maximum height in the third direction D 3 . The seventh part SD 2 P 7 may have a seventh width W 7 corresponding to a maximum width in the first direction D 1 and a seventh height H 7 corresponding to a maximum height in the third direction D 3 . The eighth part SD 2 P 8 may have an eighth width W 8 corresponding to a maximum width in the first direction D 1 and an eighth height H 8 corresponding to a maximum height in the third direction D 3 .

The sixth width W 6 may be greater than the fifth width W 5 , and the sixth height H 6 may be greater than the fifth height H 5 . For example, the sixth part SD 2 P 6 may have a size greater than that of the fifth part SD 2 P 5 . The sixth part SD 2 P 6 may have a bottom surface whose lowermost level is lower than a lowermost level of a bottom surface of the fifth part SD 2 P 5 . The seventh width W 7 may be less than the sixth width W 6 , and the seventh height H 7 may be less than the sixth height H 6 . For example, the seventh part SD 2 P 7 may have a size less than that of the sixth part SD 2 P 6 . The lowermost level of the bottom surface of the sixth part SD 2 P 6 may be lower than a lowermost level of a bottom surface of the seventh part SD 2 P 7 . The eighth width W 8 may be less than the sixth width W 6 , and the eighth height H 8 may be less than the sixth height H 6 . For example, the eighth part SD 2 P 8 may have a size less than that of the sixth part SD 2 P 6 . The lowermost level of the bottom surface of the sixth part SD 2 P 6 may be lower than a lowermost level of a bottom surface of the eighth part SD 2 P 8 .

A void VO may be formed between the second and third parts SD 1 P 2 and SD 1 P 3 of the first source/drain pattern SD 1 . A void VO may also be formed between the sixth and seventh parts SD 2 P 6 and SD 2 P 7 of the second source/drain pattern SD 2 . The voids VO may be substantially empty spaces.

Referring to FIGS. 11 A to 11 D , a first interlayer dielectric layer 110 may be formed on the substrate 100 . A planarization process may be performed on the first interlayer dielectric layer 110 until top surfaces of the sacrificial patterns PP are exposed. When the first interlayer dielectric layer 110 is planarized, the mask patterns MP may be removed.

The planarization process may remove the exposed sacrificial patterns PP. The removal of the sacrificial patterns PP may form empty spaces each of which is provided between a pair of neighboring gate spacers GS. The empty spaces may expose the first to eighth active patterns AP 1 to AP 8 .

A gate dielectric pattern GI and a gate electrode GE may be formed in each of the empty spaces. The formation of the gate dielectric pattern GI and the gate electrode GE may include conformally forming a gate dielectric layer in the empty space and forming a gate electrode layer to completely fill the empty space. The filling of the empty space with the gate electrode layer may form the gate electrode GE. Gate capping patterns CP may be formed on the gate electrodes GE.

A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110 and the gate capping patterns CP. First contacts CT 1 may be formed to penetrate the first and second interlayer dielectric layers 110 and 120 and to come into connection with the first source/drain patterns SD 1 . Second contacts CT 2 may be formed to penetrate the first and second interlayer dielectric layers 110 and 120 and to come into connection with the second source/drain patterns SD 2 .

A third interlayer dielectric layer 130 may be formed on the second interlayer dielectric layer 120 , the first contacts CT 1 , and the second contacts CT 2 .

Via contacts V 1 and wiring lines M 1 may be formed in the third interlayer dielectric layer 130 . The via contact V 1 may electrically connect the wiring line M 1 to the first contact CT 1 or to the second contact CT 2 .

A semiconductor device according to some example embodiments of the present inventive concepts will now be described, with reference to FIGS. 11 A to 11 D .

The device isolation layer ST may be provided on the substrate 100 . The device isolation layer ST may define the first to eighth active patterns AP 1 to AP 8 on an upper portion of the substrate 100 . The first to fourth active patterns AP 1 to AP 4 may be provided on the first region RG 1 of the substrate 100 . The fifth to eighth active patterns AP 5 to AP 8 may be provided on the second region RG 2 of the substrate 100 . The device isolation layer ST may have a top surface lower than those of the first to eighth active patterns AP 1 to AP 8 .

The first to eighth active patterns AP 1 to AP 8 may be sequentially arranged along the first direction D 1 . Each of the first to eighth active patterns AP 1 to AP 8 may extend in the second direction D 2 . The first recesses RS 1 may be correspondingly provided on the first to fourth active patterns AP 1 to AP 4 . The second recesses RS 2 may be correspondingly provided on the fifth to eighth active patterns AP 5 to AP 8 .

The first source/drain patterns SD 1 may be provided on the first to fourth active patterns AP 1 to AP 4 . The first source/drain patterns SD 1 may fill the first recesses RS 1 . Each of the first source/drain patterns SD 1 may include the first to fourth parts SD 1 P 1 to SD 1 P 4 . The second and third parts SD 1 P 2 and SD 1 P 3 may be merged with each other. The first part SD 1 P 1 may be spaced apart from the second part SD 1 P 2 . The second part SD 1 P 2 may be larger than the first part SD 1 P 1 . The third part SD 1 P 3 may be smaller than the second part SD 1 P 2 .

The second source/drain patterns SD 2 may be provided on the fifth to eighth active patterns AP 5 to AP 8 . The second source/drain patterns SD 2 may fill the second recesses RS 2 . Each of the second source/drain patterns SD 2 may include the fifth to eighth parts SD 2 P 5 to SD 2 P 8 . The sixth and seventh parts SD 2 P 6 and SD 2 P 7 may be merged with each other. The fifth part SD 2 P 5 may be spaced apart from the sixth part SD 2 P 6 . The sixth part SD 2 P 6 may be larger than the fifth part SD 2 P 5 . The seventh part SD 2 P 7 may be smaller than the sixth part SD 2 P 6 .

The gate electrodes GE may be provided to extend in the first direction D 1 , while running across the first to eighth active patterns AP 1 to AP 8 . The gate electrodes GE may be spaced apart from each other in the second direction D 2 . For example, the gate electrode GE may include one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D 1 along the gate electrode GE. The gate spacers GS may have top surfaces higher than that of the gate electrode GE. The top surfaces of the gate spacers GS may be coplanar with that of the first interlayer dielectric layer 110 .

The gate dielectric pattern GI may be interposed between each of the gate electrodes GE and each of the first to eighth active patterns AP 1 to AP 8 . The gate dielectric pattern GI may lie between the gate electrode GE and each of the gate spacers GS. The gate dielectric pattern GI may include a high-k dielectric material. For example, the high-k dielectric material may include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The gate capping pattern CP may be provided on each of the gate electrodes GE. The gate capping pattern CP may extend in the first direction D 1 along the gate electrode GE.

The first interlayer dielectric layer 110 may be provided on an entire surface of the substrate 100 . The first interlayer dielectric layer 110 may cover the device isolation layer ST, the gate electrodes GE, and the first and second source/drain patterns SD 1 and SD 2 . The first interlayer dielectric layer 110 may have a top surface substantially coplanar with those of the gate capping patterns CP. The second interlayer dielectric layer 120 may be provided on the first interlayer dielectric layer 110 .

The first contacts CT 1 may be provided to penetrate the first and second interlayer dielectric layers 110 and 120 and to come into connection with the first source/drain patterns SD 1 . The second contacts CT 2 may be provided to penetrate the first and second interlayer dielectric layers 110 and 120 and to come into connection with the second source/drain patterns SD 2 .

The third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120 , the first contacts CT 1 , and the second contacts CT 2 . The via contacts V 1 and the wiring lines M 1 may be provided in the third interlayer dielectric layer 130 .

Although FIGS. 1 A to 5 show four active patterns AP 1 to AP 4 , this number of active patterns is merely an example used herein to discuss the inventive concepts disclosed herein, and in some embodiments there may be less than four active patterns or greater than four active patterns. Likewise, although FIGS. 6 A to 11 D show four active patterns AP 1 to AP 4 on the first region RG 1 , and four active patterns AP 5 to AP 8 on the second region RG 2 , these numbers of active patterns are merely examples used herein to discuss the inventive concepts disclosed herein, and in some embodiments there may be less than four active patterns on each region or greater than four active patterns on each region. In some embodiments, the number of active patterns in each region RG 1 and RG 2 may be different.

A semiconductor device according to some of the present inventive concepts may include variously shaped source/drain patterns, and thus may have improved electrical characteristics.

Although some examples of embodiments of the inventive concepts disclosed herein have been discussed with reference to the accompanying figures, it will be understood that various changes in form and details may be made therein without departing from the scope of the present disclosure. It therefore will be understood that the some example embodiments described above are merely illustrative, and are not limitative in all aspects.