Manufacturing Method of Display Device Having a Lower Portion of a Partition Between First and Second Apertures

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation Application of U.S. application Ser. No. 18/336,048, filed Jun. 16, 2023, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-098019, filed Jun. 17, 2022, the entire contents of each are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a display device and a manufacturing method of a display device.

BACKGROUND

Recently, display devices to which an organic light emitting diode (OLED) is applied as a display element have been put into practical use. This display element comprises a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer which covers the lower electrode, and an upper electrode which covers the organic layer. The organic layer includes functional layers such as a hole transport layer and an electron transport layer in addition to a light emitting layer.

In the process of manufacturing such a display element, a technique which prevents the reduction in reliability has been required.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration example of a display device DSP.

FIG. 2 is a diagram showing an example of the layout of subpixels SP 1 , SP 2 and SP 3 .

FIG. 3 is a schematic cross-sectional view of the display device DSP along the A-B line of FIG. 2 .

FIG. 4 is a diagram showing an example of the configuration of display elements 201 to 203 .

FIG. 5 is a flow diagram for explaining an example of the manufacturing method of the display device DSP.

FIG. 6 is a diagram for explaining the manufacturing method of the display device DSP.

FIG. 7 is a diagram for explaining the manufacturing method of the display device DSP.

FIG. 8 is a diagram for explaining the manufacturing method of the display device DSP.

FIG. 9 is a diagram for explaining the manufacturing method of the display device DSP.

FIG. 10 is a diagram for explaining the manufacturing method of the display device DSP.

FIG. 11 is a diagram for explaining the manufacturing method of the display device DSP.

FIG. 12 is a diagram for explaining the manufacturing method of the display device DSP.

DETAILED DESCRIPTION

Embodiments described herein aim to provide a display device which can prevent the reduction in reliability and a manufacturing method of such a display device.

In general, according to one embodiment, a manufacturing method of a display device comprises preparing a processing substrate by forming a lower electrode above a substrate, forming a rib comprising an aperture overlapping the lower electrode, and forming a partition including a lower portion located on the rib and an upper portion located on the lower portion and protruding from a side surface of the lower portion, forming an organic layer on the lower electrode in the aperture, forming an upper electrode on the organic layer, forming a first transparent layer on the upper electrode, and forming a second transparent layer on the first transparent layer. The first transparent layer and the second transparent layer are formed of organic materials different from each other. A refractive index of the second transparent layer is less than a refractive index of the first transparent layer.

According to another embodiment, a display device comprises a substrate, a lower electrode provided above the substrate, a rib formed of an inorganic insulating material and comprising an aperture overlapping the lower electrode, a partition comprising a lower portion provided on the rib and formed of a conductive material, and an upper portion provided on the lower portion and protruding from a side surface of the lower portion, an organic layer provided on the lower electrode in the aperture, an upper electrode which is provided on the organic layer and is in contact with the lower portion of the partition, a first transparent layer provided on the upper electrode, a second transparent layer provided on the first transparent layer, and a sealing layer which covers the second transparent layer and is in contact with the lower portion of the partition. The first transparent layer and the second transparent layer are formed of organic materials different from each other. A refractive index of the first transparent layer is greater than a refractive index of the second transparent layer.

The embodiments can provide a display device which can prevent the reduction in reliability and a manufacturing method of such a display device.

Embodiments will be described with reference to the accompanying drawings.

The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary.

In the drawings, in order to facilitate understanding, an X-axis, a Y-axis and a Z-axis orthogonal to each other are shown depending on the need. A direction parallel to the X-axis is referred to as a first direction. A direction parallel to the Y-axis is referred to as a second direction. A direction parallel to the Z-axis is referred to as a third direction. When various elements are viewed parallel to the third direction Z, the appearance is defined as a plan view.

The display device of the present embodiment is an organic electroluminescent display device comprising an organic light emitting diode (OLED) as a display element, and could be mounted on a television, a personal computer, a vehicle-mounted device, a tablet, a smartphone, a mobile phone, etc.

FIG. 1 is a diagram showing a configuration example of a display device DSP.

The display device DSP comprises a display area DA which displays an image and a surrounding area SA around the display area DA on an insulating substrate 10 . The substrate 10 may be glass or a resinous film having flexibility.

In the present embodiment, the substrate 10 is rectangular as seen in plan view. It should be noted that the shape of the substrate 10 in plan view is not limited to a rectangular shape and may be another shape such as a square shape, a circular shape or an elliptic shape.

The display area DA comprises a plurality of pixels PX arrayed in matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of subpixels SP. For example, each pixel PX includes subpixel SP 1 which exhibits a first color, subpixel SP 2 which exhibits a second color and subpixel SP 3 which exhibits a third color. The first color, the second color and the third color are different colors. Each pixel PX may include a subpixel SP which exhibits another color such as white in addition to subpixels SP 1 , SP 2 and SP 3 or instead of one of subpixels SP 1 , SP 2 and SP 3 .

Each subpixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1 . The pixel circuit 1 comprises a pixel switch 2 , a drive transistor 3 and a capacitor 4 . The pixel switch 2 and the drive transistor 3 are, for example, switching elements consisting of thin-film transistors.

The gate electrode of the pixel switch 2 is connected to a scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to a signal line SL. The other one is connected to the gate electrode of the drive transistor 3 and the capacitor 4 . In the drive transistor 3 , one of the source electrode and the drain electrode is connected to a power line PL and the capacitor 4 , and the other one is connected to the anode of the display element 20 .

It should be noted that the configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may comprise more thin-film transistors and capacitors.

The display element 20 is an organic light emitting diode (OLED) as a light emitting element, and may be called an organic EL element.

FIG. 2 is a diagram showing an example of the layout of subpixels SP 1 , SP 2 and SP 3 .

In the example of FIG. 2 , subpixels SP 2 and SP 3 are arranged in the second direction Y. Further, each of subpixels SP 2 and SP 3 is adjacent to subpixel SP 1 in the first direction X.

When subpixels SP 1 , SP 2 and SP 3 are provided in line with this layout, in the display area DA, a column in which subpixels SP 2 and SP 3 are alternately provided in the second direction Y and a column in which a plurality of subpixels SP 1 are provided in the second direction Y are formed. These columns are alternately arranged in the first direction X.

It should be noted that the layout of subpixels SP 1 , SP 2 and SP 3 is not limited to the example of FIG. 2 . As another example, subpixels SP 1 , SP 2 and SP 3 in each pixel PX may be arranged in order in the first direction X.

A rib 5 and a partition 6 are provided in the display area DA. The rib 5 comprises apertures AP 1 , AP 2 and AP 3 in subpixels SP 1 , SP 2 and SP 3 , respectively.

The partition 6 overlaps the rib 5 as seen in plan view. The partition 6 comprises a plurality of first partitions 6 x extending in the first direction X and a plurality of second partitions 6 y extending in the second direction Y. The first partitions 6 x are provided between the apertures AP 2 and AP 3 which are adjacent to each other in the second direction Y and between two apertures AP 1 which are adjacent to each other in the second direction Y. Each second partition 6 y is provided between the apertures AP 1 and AP 2 which are adjacent to each other in the first direction X and between the apertures AP 1 and AP 3 which are adjacent to each other in the first direction X.

In the example of FIG. 2 , the first partitions 6 x and the second partitions 6 y are connected to each other. Thus, the partition 6 is formed into a grating shape surrounding the apertures AP 1 , AP 2 and AP 3 as a whole. In other words, the partition 6 comprises apertures in subpixels SP 1 , SP 2 and SP 3 in a manner similar to that of the rib 5 .

Subpixels SP 1 , SP 2 and SP 3 comprise display elements 201 , 202 and 203 , respectively, as the display elements 20 .

Subpixel SP 1 comprises a lower electrode LE 1 , an upper electrode UE 1 and an organic layer OR 1 overlapping the aperture AP 1 . Subpixel SP 2 comprises a lower electrode LE 2 , an upper electrode UE 2 and an organic layer OR 2 overlapping the aperture AP 2 . Subpixel SP 3 comprises a lower electrode LE 3 , an upper electrode UE 3 and an organic layer OR 3 overlapping the aperture AP 3 .

In the example of FIG. 2 , the outer shapes of the lower electrodes LE 1 , LE 2 and LE 3 are shown by dotted lines, and the outer shapes of the organic layers OR 1 , OR 2 and OR 3 and the upper electrodes UE 1 , UE 2 and UE 3 are shown by alternate long and short dash lines. The peripheral portion of each of the lower electrodes LE 1 , LE 2 and LE 3 overlaps the rib 5 . It should be noted that the outer shape of each of the lower electrodes, organic layers and upper electrodes shown in the figure does not necessarily reflect the accurate shape.

The lower electrode LE 1 , the upper electrode UE 1 and the organic layer OR 1 constitute the display element 201 of subpixel SP 1 . The lower electrode LE 2 , the upper electrode UE 2 and the organic layer OR 2 constitute the display element 202 of subpixel SP 2 . The lower electrode LE 3 , the upper electrode UE 3 and the organic layer OR 3 constitute the display element 203 of subpixel SP 3 .

The lower electrodes LE 1 , LE 2 and LE 3 correspond to, for example, the anodes of the display elements. The upper electrodes UE 1 , UE 2 and UE 3 correspond to the cathodes of the display elements or a common electrode.

The lower electrode LE 1 is connected to the pixel circuit 1 (see FIG. 1 ) of subpixel SP 1 through a contact hole CH 1 . The lower electrode LE 2 is connected to the pixel circuit 1 of subpixel SP 2 through a contact hole CH 2 . The lower electrode LE 3 is connected to the pixel circuit 1 of subpixel SP 3 through a contact hole CH 3 .

In the example of FIG. 2 , the area of the aperture AP 1 is greater than that of the aperture AP 2 , and the area of the aperture AP 2 is greater than that of the aperture AP 3 . In other words, the area of the lower electrode LE 1 exposed from the aperture AP 1 is greater than that of the lower electrode LE 2 exposed from the aperture AP 2 . The area of the lower electrode LE 2 exposed from the aperture AP 2 is greater than that of the lower electrode LE 3 exposed from the aperture AP 3 .

For example, the display element 201 of subpixel SP 1 is configured to emit light in a blue wavelength range. The display element 202 of subpixel SP 2 is configured to emit light in a green wavelength range. The display element 203 of subpixel SP 3 is configured to emit light in a red wavelength range.

FIG. 3 is a schematic cross-sectional view of the display device DSP along the A-B line of FIG. 2 .

A circuit layer 11 is provided on the substrate 10 described above. The circuit layer 11 includes various circuits such as the pixel circuit 1 , and various lines such as scanning line GL, signal line SL and power line PL shown in FIG. 1 . The circuit layer 11 is covered with an insulating layer 12 . The insulating layer 12 functions as a planarization film which planarizes the irregularities formed by the circuit layer 11 .

The lower electrodes LE 1 , LE 2 and LE 3 are provided on the insulating layer 12 . The rib 5 is provided on the insulating layer 12 and the lower electrodes LE 1 , LE 2 and LE 3 . The end portions of the lower electrodes LE 1 , LE 2 and LE 3 are covered with the rib 5 . In other words, the end portions of the lower electrodes LE 1 , LE 2 and LE 3 are provided between the insulating layer 12 and the rib 5 . Of the lower electrodes LE 1 , LE 2 and LE 3 , between the lower electrodes which are adjacent to each other, the insulating layer 12 is covered with the rib 5 .

The partition 6 includes a lower portion (stem) 61 provided on the rib 5 and an upper portion (shade) 62 provided on the lower portion 61 . The lower portion 61 of the partition 6 shown on the left side of the figure is located between the aperture AP 1 and the aperture AP 2 . The lower portion 61 of the partition 6 shown on the right side of the figure is located between the aperture AP 2 and the aperture AP 3 . The upper portion 62 has a width greater than that of the lower portion 61 . By this configuration, the both end portions of the upper portion 62 protrude relative to the side surfaces of the lower portion 61 . This shape of the partition 6 may be called an overhang shape. Of the upper portion 62 , a portion which protrudes to the aperture AP 1 relative to the lower portion 61 is referred to as a protrusion 621 . A portion which protrudes to the aperture AP 2 relative to the lower portion 61 is referred to as a protrusion 622 . A portion which protrudes to the aperture AP 3 relative to the lower portion 61 is referred to as a protrusion 623 .

The organic layer OR 1 is in contact with the lower electrode LE 1 through the aperture AP 1 , covers the lower electrode LE 1 and overlaps part of the rib 5 . The upper electrode UE 1 faces the lower electrode LE 1 and is provided on the organic layer OR 1 . Further, the upper electrode UE 1 is in contact with a side surface of the lower portion 61 . The organic layer OR 1 and the upper electrode UE 1 are located on the lower side relative to the upper portion 62 .

The organic layer OR 2 is in contact with the lower electrode LE 2 through the aperture AP 2 , covers the lower electrode LE 2 and overlaps part of the rib 5 . The upper electrode UE 2 faces the lower electrode LE 2 and is provided on the organic layer OR 2 . Further, the upper electrode UE 2 is in contact with a side surface of the lower portion 61 . The organic layer OR 2 and the upper electrode UE 2 are located on the lower side relative to the upper portion 62 .

The organic layer OR 3 is in contact with the lower electrode LE 3 through the aperture AP 3 , covers the lower electrode LE 3 and overlaps part of the rib 5 . The upper electrode UE 3 faces the lower electrode LE 3 and is provided on the organic layer OR 3 . Further, the upper electrode UE 3 is in contact with a side surface of the lower portion 61 . The organic layer OR 3 and the upper electrode UE 3 are located on the lower side relative to the upper portion 62 .

Subpixels SP 1 , SP 2 and SP 3 further include cap layers (optical adjustment layers) CP 1 , CP 2 and CP 3 for adjusting the optical property of the light emitted from the light emitting layers of the organic layers OR 1 , OR 2 and OR 3 .

The cap layer CP 1 is located in the aperture AP 1 , is located on the lower side relative to the upper portion 62 and is provided on the upper electrode UE 1 . The cap layer CP 2 is located in the aperture AP 2 , is located on the lower side relative to the upper portion 62 and is provided on the upper electrode UE 2 . The cap layer CP 3 is located in the aperture AP 3 , is located on the lower side relative to the upper portion 62 and is provided on the upper electrode UE 3 .

Sealing layers SE 1 , SE 2 and SE 3 are provided in subpixels SP 1 , SP 2 and SP 3 , respectively.

The sealing layer SE 1 is in contact with the cap layer CP 1 and the lower and upper portions 61 and 62 of the partition 6 and continuously covers the members of subpixel SP 1 .

The sealing layer SE 2 is in contact with the cap layer CP 2 and the lower and upper portions 61 and 62 of the partition 6 and continuously covers the members of subpixel SP 2 .

The sealing layer SE 3 is in contact with the cap layer CP 3 and the lower and upper portions 61 and 62 of the partition 6 and continuously covers the members of subpixel SP 3 .

The sealing layers SE 1 , SE 2 and SE 3 are covered with a protective layer 13 .

In the example shown in the figure, part of the organic layer OR 1 , part of the upper electrode UE 1 and part of the cap layer CP 1 are located between the partition 6 and the sealing layer SE 1 , are provided on the upper portion 62 and are spaced apart from the portions located on the lower side relative to the upper portion 62 .

Part of the organic layer OR 2 , part of the upper electrode UE 2 and part of the cap layer CP 2 are located between the partition 6 and the sealing layer SE 2 , are provided on the upper portion 62 and are spaced apart from the portions located on the lower side relative to the upper portion 62 .

Part of the organic layer OR 3 , part of the upper electrode UE 3 and part of the cap layer CP 3 are located between the partition 6 and the sealing layer SE 3 , are provided on the upper portion 62 and are spaced apart from the portions located on the lower side relative to the upper portion 62 .

The insulating layer 12 is an organic insulating layer. The rib 5 and the sealing layers SE 1 , SE 2 and SE 3 are inorganic insulating layers.

The rib 5 is formed of silicon nitride (SiNx) as an example of inorganic insulating materials. It should be noted that the rib 5 may be formed as, as another inorganic insulating material, a single-layer body of one of silicon oxide (SiOx), silicon oxynitride (SiON) and aluminum oxide (Al 2 O 3 ). The rib 5 may be formed as a sacked layer body of a combination consisting of at least two of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer and an aluminum oxide layer.

The sealing layers SE 1 , SE 2 and SE 3 are formed of, for example, the same inorganic insulating material.

The sealing layers SE 1 , SE 2 and SE 3 are formed of silicon nitride (SiNx) as an example of inorganic insulating materials. It should be noted that the sealing layers SE 1 , SE 2 and SE 3 may be formed as, as another inorganic insulating material, a single-layer body of one of silicon oxide (SiOx), silicon oxynitride (SiON) and aluminum oxide (Al 2 O 3 ). Each of the sealing layers SE 1 , SE 2 and SE 3 may be formed as a stacked layer body of a combination consisting of at least two of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer and an aluminum oxide layer. Thus, the sealing layers SE 1 , SE 2 and SE 3 may be formed of the same material as the rib 5 .

The lower portion 61 of the partition 6 is formed of a conductive material and is electrically connected to the upper electrodes UE 1 , UE 2 and UE 3 . The upper portion 62 of the partition 6 may be also formed of a conductive material.

The thickness of the rib 5 is sufficiently less than that of each of the partition 6 and the insulating layer 12 . For example, the thickness of the rib 5 is greater than or equal to 200 nm but less than or equal to 400 nm.

The thickness of the lower portion 61 of the partition 6 (the thickness from the upper surface of the rib 5 to the lower surface of the upper portion 62 ) is greater than that of the rib 5 .

The thickness of the sealing layer SE 1 , the thickness of the sealing layer SE 2 and the thickness of the sealing layer SE 3 are substantially equal to each other and are, for example, greater than or equal to 1 μm.

Each of the lower electrodes LE 1 , LE 2 and LE 3 may be formed of a transparent conductive material such as ITO or may comprise a multilayer structure of a metal material such as silver (Ag) and a transparent conductive material. Each of the upper electrodes UE 1 , UE 2 and UE 3 is formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). Each of the upper electrodes UE 1 , UE 2 and UE 3 may be formed of a transparent conductive material such as ITO.

Each of the organic layers OR 1 , OR 2 and OR 3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer and an electron injection layer. The organic layer OR 1 includes a light emitting layer EM 1 . The organic layer OR 2 includes a light emitting layer EM 2 . The light emitting layer EM 2 is formed of a material different from that of the light emitting layer EM 1 . The organic layer OR 3 includes a light emitting layer EM 3 . The light emitting layer EM 3 is formed of a material different from the materials of the light emitting layers EM 1 and EM 2 .

The material of the light emitting layer EM 1 , the material of the light emitting layer EM 2 and the material of the light emitting layer EM 3 are materials which emit light in different wavelength ranges.

For example, the light emitting layer EM 1 is formed of a material which emits light in a blue wavelength range. The light emitting layer EM 2 is formed of a material which emits light in a green wavelength range. The light emitting layer EM 3 is formed of a material which emits light in a red wavelength range.

Each of the cap layers CP 1 , CP 2 and CP 3 is formed of, for example, a multilayer body of transparent thin films. As the thin films, the multilayer body includes a thin film formed of an organic material. These thin films have refractive indices different from each other. The materials of the thin films constituting the multilayer body are different from the materials of the upper electrodes UE 1 , UE 2 and UE 3 and are also different from the materials of the sealing layers SE 1 , SE 2 and SE 3 .

The protective layer 13 is formed of a multilayer body of transparent thin films. For example, as the thin films, the multilayer body includes a thin film formed of an inorganic material and a thin film formed of an organic material.

Common voltage is applied to the partition 6 . This common voltage is applied to each of the upper electrodes UE 1 , UE 2 and UE 3 which are in contact with the side surfaces of the lower portions 61 . Pixel voltage is applied to the lower electrodes LE 1 , LE 2 and LE 3 through the pixel circuits 1 provided in subpixels SP 1 , SP 2 and SP 3 , respectively.

When a potential difference is formed between the lower electrode LE 1 and the upper electrode UE 1 , the light emitting layer EM 1 of the organic layer OR 1 emits light in a blue wavelength range. When a potential difference is formed between the lower electrode LE 2 and the upper electrode UE 2 , the light emitting layer EM 2 of the organic layer OR 2 emits light in a green wavelength range. When a potential difference is formed between the lower electrode LE 3 and the upper electrode UE 3 , the light emitting layer EM 3 of the organic layer OR 3 emits light in a red wavelength range.

FIG. 4 is a diagram showing an example of the configuration of the display elements 201 to 203 . Here, in the example, this specification assumes that each lower electrode corresponds to an anode and each upper electrode corresponds to a cathode.

The display element 201 includes the organic layer OR 1 between the lower electrode LE 1 and the upper electrode UE 1 .

In the organic layer OR 1 , a hole injection layer HIL 1 , a hole transport layer HTL 1 , an electron blocking layer EBL 1 , the light emitting layer EM 1 , a hole blocking layer HBL 1 , an electron transport layer ETL 1 and an electron injection layer EIL 1 are stacked in this order.

The cap layer CP 1 includes a first transparent layer TL 11 and a second transparent layer TL 12 . The first transparent layer TL 11 is provided on the upper electrode UE 1 . The second transparent layer TL 12 is provided on the first transparent layer TL 11 . The sealing layer SE 1 is provided on the second transparent layer TL 12 .

The display element 202 includes the organic layer OR 2 between the lower electrode LE 2 and the upper electrode UE 2 .

In the organic layer OR 2 , a hole injection layer HIL 2 , a hole transport layer HTL 2 , an electron blocking layer EBL 2 , the light emitting layer EM 2 , a hole blocking layer HBL 2 , an electron transport layer ETL 2 and an electron injection layer EIL 2 are stacked in this order.

The cap layer CP 2 includes a first transparent layer TL 21 and a second transparent layer TL 22 . The first transparent layer TL 21 is provided on the upper electrode UE 2 . The second transparent layer TL 22 is provided on the first transparent layer TL 21 . The sealing layer SE 2 is provided on the second transparent layer TL 22 .

The display element 203 includes the organic layer OR 3 between the lower electrode LE 3 and the upper electrode UE 3 .

In the organic layer OR 3 , a hole injection layer HIL 3 , a hole transport layer HTL 3 , an electron blocking layer EBL 3 , the light emitting layer EM 3 , a hole blocking layer HBL 3 , an electron transport layer ETL 3 and an electron injection layer EIL 3 are stacked in this order.

The cap layer CP 3 includes a first transparent layer TL 31 and a second transparent layer TL 32 . The first transparent layer TL 31 is provided on the upper electrode UE 3 . The second transparent layer TL 32 is provided on the first transparent layer TL 31 . The sealing layer SE 3 is provided on the second transparent layer TL 32 .

The first transparent layers TL 11 , TL 21 and TL 31 are transparent organic layers each formed of an organic material, and are high refractive layers having refractive indices greater than those of the upper electrodes UE 1 , UE 2 and UE 3 . For example, the refractive index of each of the first transparent layers TL 11 , TL 21 and TL 31 is greater than or equal to 1.7 but less than or equal to 2.0.

The second transparent layers TL 12 , TL 22 and TL 32 are transparent organic layers each formed of an organic material, and are low refractive layers having refractive indices less than those of the first transparent layers TL 11 , TL 21 and TL 31 . For example, the refractive index of each of the second transparent layers TL 12 , TL 22 and TL 32 is greater than or equal to 1.3 but less than or equal to 1.6.

The refractive indices of the sealing layers SE 1 , SE 2 and SE 3 which are in contact with the second transparent layers TL 12 , TL 22 and TL 32 are greater than those of the second transparent layers TL 12 , TL 22 and TL 32 . For example, the refractive index of each of the sealing layers SE 1 , SE 2 and SE 3 is greater than or equal to 1.7 but less than or equal to 2.0.

As the organic material for forming the second transparent layers TL 12 , TL 22 and TL 32 , fluorine resin in which the main chain consists of carbon and which contains fluorine in a substituent is desirable. For example, each of the second transparent layers TL 12 , TL 22 and TL 32 can be formed of at least one of polytetrafluoroethylene (PTFE), polyvinylidene fluoride (PVDF) and 2-(perfluorohexyl)ethyl acrylate. The refractive index of polytetrafluoroethylene is 1.35. The refractive index of polyvinylidene fluoride is 1.42. The refractive index of 2-(perfluorohexyl)ethyl acrylate is 1.35.

As another material for forming the second transparent layers TL 12 , TL 22 and TL 32 , lithium fluoride can be considered. The refractive index of lithium fluoride is 1.4. It should be noted that lithium fluoride is very hygroscopic.

To the contrary, the organic materials described above such as polytetrafluoroethylene (PTFE), polyvinylidene fluoride (PVDF) and 2-(perfluorohexyl)ethyl acrylate have a less hygroscopic property compared to lithium fluoride and do not exhibit a deliquescent property. Thus, these organic materials can stably maintain the state of a thin film even if they are exposed to air.

The second transparent layers TL 12 , TL 22 and TL 32 to which these organic materials are applied can be formed by a method such as vapor deposition based on resistive heating, vapor deposition based on ion beams or sputtering. The film thickness of each of these second transparent layers TL 12 , TL 22 and TL 32 is, for example, 20 nm to 500 nm.

Each of the cap layers CP 1 , CP 2 and CP 3 described above may be a stacked layer body consisting of three or more layers.

It should be noted that each of the organic layers OR 1 , OR 2 and OR 3 may include, in addition to the functional layers described above, other functional layers such as a carrier generation layer as needed, or at least one of the above functional layers may be omitted.

The above functional layers are individually formed for each of the display elements 201 to 203 . Thus, the thickness of each of the above functional layers may differ depending on the display element.

When this specification focuses attention on the same functional layer, the functional layer of one of the display elements 201 to 203 may be formed of a material different from that of the functional layers of the other two display elements, or all of the functional layers of the display elements 201 to 203 may be formed of materials different from each other.

Further, the layer structure of one of the display elements 201 to 203 may be different from that of the other two display elements, or all of the layer structures of the display elements 201 to 203 may be different from each other. For example, when this specification focuses attention on one of the functional layers, one of the display elements 201 to 203 may not include this functional layer, or only one of the display elements 201 to 203 may include the functional layer. When this specification focuses attention on one of the functional layers, for example, this functional layer may comprise a multilayer structure in one of the display elements 201 to 203 .

The first transparent layers TL 11 , TL 21 and TL 31 are spaced apart from each other and are individually formed. Thus, all of the first transparent layers TL 11 , TL 21 and TL 31 may be formed of the same material, or one of the first transparent layers TL 11 , TL 21 and TL 31 may be formed of a material different from that of the other two transparent layers, or all of the first transparent layers TL 11 , TL 21 and TL 31 may be formed of materials different from each other.

The second transparent layers TL 12 , TL 22 and TL 32 are spaced apart from each other and are individually formed. Thus, all of the second transparent layers TL 12 , TL 22 and TL 32 may be formed of the same material, or one of the second transparent layers TL 12 , TL 22 and TL 32 may be formed of a material different from that of the other two transparent layers, or all of the second transparent layers TL 12 , TL 22 and TL 32 may be formed of materials different from each other.

All of the thicknesses of the first transparent layers TL 11 , TL 21 and TL 31 may be the same as each other, or may be different from each other.

All of the thicknesses of the second transparent layers TL 12 , TL 22 and TL 32 may be the same as each other, or may be different from each other.

For example, all of the thicknesses of the second transparent layers TL 12 , TL 22 and TL 32 are the same as each other. The thickness of the first transparent layer TL 11 in the display element 201 for blue is less than that of the first transparent layer TL 31 in the display element 203 for red.

In the display element 201 , the thickness of the second transparent layer TL 12 is greater than that of the first transparent layer TL 11 . In the display element 203 , the thickness of the first transparent layer TL 31 is less than that of the second transparent layer TL 32 .

All of the layer structures of the cap layers CP 1 to CP 3 may be the same as each other, or the layer structure of one of the cap layers CP 1 to CP 3 may be different from that of the other two cap layers, or all of the layer structures of the cap layers CP 1 to CP 3 may be different from each other.

In the example shown in FIG. 4 , in the display element 201 , the upper electrode UE 1 functions as an etching stopper layer when dry etching is applied to the sealing layer SE 1 . In the display element 202 , the upper electrode UE 2 functions as an etching stopper layer when dry etching is applied to the sealing layer SE 2 . In the display element 203 , the upper electrode UE 3 functions as an etching stopper layer when dry etching is applied to the sealing layer SE 3 .

When dry etching is applied to each of an etching stopper layer and a sealing layer on the same condition, and the etching rate of the etching stopper layer (an upper electrode) is compared with that of the sealing layer, the etching rate of the etching stopper layer is less than that of the sealing layer. In this configuration, when dry etching is performed for a stacked layer body in which the sealing layer is stacked on the etching stopper layer, while the sealing layer is removed, the progress of etching can be stopped in the etching stopper layer.

The upper electrodes UE 1 , UE 2 and UE 3 which function as etching stopper layers are formed of a material different from the materials of the rib 5 and the sealing layers SE 1 , SE 2 and SE 3 . For example, the rib 5 and the sealing layers SE 1 , SE 2 and SE 3 are formed of silicon nitride. The upper electrodes UE 1 , UE 2 and UE 3 are formed of an alloy of magnesium and silver, which is a material having a high resistance to dry etching compared to silicon nitride.

Now, this specification explains an example of the manufacturing method of the display device DSP.

FIG. 5 is a flow diagram for explaining an example of the manufacturing method of the display device DSP.

The manufacturing method shown here roughly includes the process of preparing a processing substrate SUB comprising subpixels SP 1 , SP 2 and SP 3 (step ST 1 ), the process of forming the display element 201 of subpixel SP 1 (step ST 2 ), the process of forming the display element 202 of subpixel SP 2 (step ST 3 ) and the process of forming the display element 203 of subpixel SP 3 (step ST 4 ).

In step ST 1 , first, the processing substrate SUB is prepared by forming the lower electrode LE 1 of subpixel SP 1 , the lower electrode LE 2 of subpixel SP 2 , the lower electrode LE 3 of subpixel SP 3 , the rib 5 and the partition 6 above the substrate 10 . As shown in FIG. 3 , the circuit layer 11 and the insulating layer 12 are also formed between the substrate 10 and the lower electrodes LE 1 , LE 2 and LE 3 .

In step ST 2 , first, a first thin film 31 including the light emitting layer EM 1 is formed over subpixel SP 1 , subpixel SP 2 and subpixel SP 3 (step ST 21 ). The first thin film 31 is a stacked layer body of the organic layer OR 1 , upper electrode UE 1 , cap layer CP 1 and sealing layer SE 1 shown in FIG. 3 . Subsequently, a first resist 41 patterned into a predetermined shape is formed on the first thin film 31 (step ST 22 ). Subsequently, part of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST 23 ). At this time, for example, the first thin film 31 provided in subpixel SP 2 and subpixel SP 3 is removed. Subsequently, the first resist 41 is removed (step ST 24 ). In this way, subpixel SP 1 is formed. Subpixel SP 1 comprises the display element 201 comprising the first thin film 31 having a predetermined shape.

In step ST 3 , first, a second thin film 32 including the light emitting layer EM 2 is formed over subpixel SP 1 , subpixel SP 2 and subpixel SP 3 (step ST 31 ). The second thin film 32 is a stacked layer body of the organic layer OR 2 , upper electrode UE 2 , cap layer CP 2 and sealing layer SE 2 shown in FIG. 3 . Subsequently, a second resist 42 patterned into a predetermined shape is formed on the second thin film 32 (step ST 32 ). Subsequently, part of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST 33 ). At this time, for example, the second thin film 32 provided in subpixel SP 1 and subpixel SP 3 is removed. Subsequently, the second resist 42 is removed (step ST 34 ). In this way, subpixel SP 2 is formed. Subpixel SP 2 comprises the display element 202 comprising the second thin film 32 having a predetermined shape.

In step ST 4 , first, a third thin film 33 including the light emitting layer EM 3 is formed over subpixel SP 1 , subpixel SP 2 and subpixel SP 3 (step ST 41 ). The third thin film 33 is a stacked layer body of the organic layer OR 3 , upper electrode UE 3 , cap layer CP 3 and sealing layer SE 3 shown in FIG. 3 . Subsequently, a third resist 43 patterned into a predetermined shape is formed on the third thin film 33 (step ST 42 ). Subsequently, part of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST 43 ). At this time, for example, the third thin film 33 provided in subpixel SP 1 and subpixel SP 2 is removed. Subsequently, the third resist 43 is removed (step ST 44 ). In this way, subpixel SP 3 is formed. Subpixel SP 3 comprises the display element 203 comprising the third thin film 33 having a predetermined shape.

The detailed illustrations of the second thin film 32 , the second resist 42 , the third thin film 33 and the third resist 43 are omitted.

Now, this specification explains step ST 1 and step ST 2 with reference to FIG. 6 to FIG. 12 . The section shown in each of FIG. FIG. 6 to FIG. 12 corresponds to, for example, the section taken along the A-B line of FIG. 2 .

First, in step ST 1 , as shown in FIG. 6 , the processing substrate SUB is prepared. The process of preparing the processing substrate SUB includes the process of forming the circuit layer 11 on the substrate 10 , the process of forming the insulating layer 12 on the circuit layer 11 , the process of forming the lower electrode LE 1 of subpixel SP 1 , the lower electrode LE 2 of subpixel SP 2 and the lower electrode LE 3 of subpixel SP 3 on the insulating layer 12 , the process of forming the rib 5 comprising the apertures AP 1 , AP 2 and AP 3 overlapping the lower electrodes LE 1 , LE 2 and LE 3 , respectively, and the process of forming the partition 6 including the lower portion 61 provided on the rib 5 and the upper portion 62 provided on the lower portion 61 and protruding from the side surfaces of the lower portion 61 . In each of FIG. 7 to FIG. 12 , the illustrations of the substrate 10 and the circuit layer 11 lower than the insulating layer 12 are omitted.

The rib 5 is formed of, for example, silicon nitride.

Of the partition 6 , at least the lower portion 61 is formed of a conductive material.

Subsequently, in step ST 21 , as shown FIG. 7 , the first thin film 31 is formed over subpixel SP 1 , subpixel SP 2 and subpixel SP 3 . The process of forming the first thin film 31 includes, on the processing substrate SUB, the process of forming the organic layer OR 1 including the light emitting layer EM 1 , the process of forming the upper electrode UE 1 on the organic layer OR 1 , the process of forming the first transparent layer TL 11 of the cap layer CP 1 on the upper electrode UE 1 , the process of forming the second transparent layer TL 12 of the cap layer CP 1 on the first transparent layer TL 11 and the process of forming the sealing layer SE 1 on the second transparent layer TL 12 . Thus, in the example shown in the figure, the first thin film 31 includes the organic layer OR 1 , the upper electrode UE 1 , the cap layer CP 1 and the sealing layer SE 1 .

The organic layer OR 1 is formed on each of the lower electrode LE 1 , the lower electrode LE 2 and the lower electrode LE 3 and is also formed on the partition 6 . Of the organic layer OR 1 , the portion formed on each upper portion 62 is spaced apart from the portion formed on each of the lower electrodes LE 1 , LE 2 and LE 3 . The various functional layers and the light emitting layer EM 1 of the organic layer OR 1 are formed by a vapor deposition method.

The upper electrode UE 1 is formed on the organic layer OR 1 immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 , covers the rib 5 and is in contact with the lower portions 61 of the partition 6 . The upper electrode UE 1 is also formed on the organic layer OR 1 immediately above each upper portion 62 . Of the upper electrode UE 1 , the portion which is formed immediately above each upper portion 62 is spaced apart from the portion which is formed immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 . The upper electrode UE 1 is formed of an alloy of magnesium and silver by a vapor deposition method.

The first transparent layer TL 11 of the cap layer CP 1 is formed on the upper electrode UE 1 immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 , and is also formed on the upper electrode UE 1 immediately above each upper portion 62 . Of the first transparent layer TL 11 , the portion which is formed immediately above each upper portion 62 is spaced apart from the portion which is formed immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 . For example, the first transparent layer TL 11 is formed of an organic material by a vapor deposition method.

The second transparent layer TL 12 of the cap layer CP 1 is formed on the first transparent layer TL 11 immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 , and is also formed on the first transparent layer TL 11 immediately above each upper portion 62 . Of the second transparent layer TL 12 , the portion which is formed immediately above each upper portion 62 is spaced apart from the portion which is formed immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 . For example, the second transparent layer TL 12 is formed of an organic material by a vapor deposition method. The second transparent layer TL 12 is formed of an organic material which is different from the first transparent layer TL 11 . Further, the refractive index of the second transparent layer TL 12 is less than that of the first transparent layer TL 11 .

The sealing layer SE 1 is formed so as to cover the second transparent layer TL 12 and the partition 6 . In other words, the sealing layer SE 1 is formed on the second transparent layer TL 12 immediately above each of the lower electrodes LE 1 , LE 2 and LE 3 , and is also formed on the second transparent layer TL 12 immediately above each upper portion 62 . Moreover, the sealing layer SE 1 is in contact with the lower portion 61 of the partition 6 . In the sealing layer SE 1 , the portion which is formed immediately above each upper portion 62 is continuous with the portion which is formed immediately above each of the lower electrodes. The sealing layer SE 1 is formed of, for example, silicon nitride. The sealing layer SE 1 is formed by, for example, a CVD method.

Subsequently, in step ST 22 , as shown in FIG. 8 , the patterned first resist 41 is formed on the sealing layer SE 1 . The first resist 41 covers the first thin film 31 of subpixel SP 1 , and the first thin film 31 is exposed from the first resist 41 in subpixels SP 2 and SP 3 . Thus, the first resist 41 overlaps the sealing layer SE 1 located immediately above the lower electrode LE 1 . The first resist 41 extends from subpixel SP 1 to the upper side of the partition 6 . On the partition 6 between subpixel SP 1 and subpixel SP 2 , the first resist 41 is provided on the subpixel SP 1 side (the left side of the figure), and the sealing layer SE 1 is exposed from the first resist 41 on the subpixel SP 2 side (the right side of the figure). The sealing layer SE 1 is exposed from the first resist 41 in subpixel SP 2 and subpixel SP 3 .

Subsequently, in step ST 23 , as shown in FIG. 9 to FIG. 11 , etching is applied using the first resist 41 as a mask. By this process, the first thin film 31 exposed from the first resist 41 in subpixels SP 2 and SP 3 is removed, and the first thin film 31 remains in subpixel SP 1 .

The process of removing the first thin film 31 is, for example, as follows.

First, as shown in FIG. 9 , dry etching is performed using the first resist 41 as a mask to remove the sealing layer SE 1 exposed from the first resist 41 . By this process, of the cap layer CP 1 , part of the second transparent layer TL 12 is exposed from the sealing layer SE 1 .

Subsequently, as shown in FIG. 10 , ashing (dry etching for emitting oxygen plasma) is performed using the first resist 41 as a mask to remove the second transparent layer TL 12 exposed from the sealing layer SE 1 .

Subsequently, ashing is performed using the first resist 41 as a mask to remove the first transparent layer TL 11 exposed from the second transparent layer TL 12 . By this process, part of the upper electrode UE 1 is exposed from the cap layer CP 1 .

Subsequently, as shown in FIG. 11 , wet etching is performed using the first resist 41 as a mask to remove the upper electrode UE 1 exposed from the first transparent layer TL 11 .

Subsequently, ashing is performed using the first resist 41 as a mask to remove the organic layer OR 1 exposed from the upper electrode UE 1 .

In this way, the lower electrode LE 2 is exposed in subpixel SP 2 , and the rib 5 surrounding the lower electrode LE 2 is exposed. In subpixel SP 3 , the lower electrode LE 3 is exposed, and the rib 5 surrounding the lower electrode LE 3 is exposed. Of the partition 6 between subpixel SP 1 and subpixel SP 2 , the subpixel SP 2 side is exposed. Further, the partition 6 between subpixel SP 2 and subpixel SP 3 is exposed.

Subsequently, in step ST 24 , as shown in FIG. 12 , the first resist 41 is removed. Thus, the sealing layer SE 1 of subpixel SP 1 is exposed. Through these steps ST 21 to ST 24 , the display element 201 is formed in subpixel SP 1 . The display element 201 consists of the lower electrode LE 1 , the organic layer OR 1 including the light emitting layer EM 1 , the upper electrode UE 1 , the first transparent layer TL 11 and the second transparent layer TL 12 . The display element 201 is covered with the sealing layer SE 1 .

A stacked layer body of the organic layer OR 1 including the light emitting layer EM 1 , the upper electrode UE 1 , the first transparent layer TL 11 , the second transparent layer TL 12 and the sealing layer SE 1 is formed on the partition 6 between subpixel SP 1 and subpixel SP 2 . The stacked layer body located on the partition 6 is spaced apart from the organic layer OR 1 , the upper electrode UE 1 , the first transparent layer TL 11 , the second transparent layer TL 12 and the sealing layer SE 1 constituting the display element 201 . Of the partition 6 , the portion on the subpixel SP 1 side is covered with the sealing layer SE 1 . It should be noted that the stacked layer body on the partition 6 shown in FIG. 12 is completely removed in some cases.

Steps ST 31 to ST 34 shown in FIG. 5 are similar to steps ST 21 to ST 24 described above. Through these steps ST 31 to ST 34 , the display element 202 is formed in subpixel SP 2 shown in FIG. 3 . The display element 202 consists of the lower electrode LE 2 , the organic layer OR 2 including the light emitting layer EM 2 , the upper electrode UE 2 , the first transparent layer TL 21 and the second transparent layer TL 22 . The display element 202 is covered with the sealing layer SE 2 .

Steps ST 41 to ST 44 shown in FIG. 5 are also similar to steps ST 21 to ST 24 described above. Through these steps ST 41 to ST 44 , the display element 203 is formed in subpixel SP 3 shown in FIG. 3 . The display element 203 consists of the lower electrode LE 3 , the organic layer OR 3 including the light emitting layer EM 3 , the upper electrode UE 3 , the first transparent layer TL 31 and the second transparent layer TL 32 . The display element 203 is covered with the sealing layer SE 3 .

In the present embodiment, the display elements 201 to 203 comprise the cap layers CP 1 to CP 3 , respectively, which function as optical adjustment layers. Thus, the light emitted from the light emitting layers EM 1 to EM 3 is reflected on the interface between the first and second transparent layers constituting the cap layers CP 1 to CP 3 , respectively, and is reflected on the upper electrode again. By the microcavity effect using such interference of reflected light, the light extraction efficiency for each display element can be improved.

This optical adjustment layer is formed as a stacked layer body consisting of a low refractive layer and a high refractive layer. In the manufacturing method of the display device described above, the first to third thin films each including the optical adjustment layer are patterned for each subpixel. At this time, as each layer constituting the optical adjustment layer is formed of an organic material, the layers can be easily and continuously removed by an ashing process. In addition, in the ashing process, oxygen plasma is emitted while spreading. Therefore, as shown in FIG. 9 , both the low refractive layer and the high refractive layer can be assuredly removed immediately under the protrusion 622 of the partition 6 and immediately under the protrusion 623 of the partition 6 . Thus, the generation of the residue of the organic materials is prevented, thereby preventing the reduction in reliability.

Further, as the organic material for forming each of the low refractive layer and the high refractive layer, a material having a high transparency and a predetermined refractive index can be applied. Thus, the number of choices for the applicable materials is increased. When the organic material is removed, an ashing process is applied. Further, the low refractive layer and the high refractive layer can be continuously removed. Thus, the process becomes more flexible and the processing time is also shortened compared to wet etching for removing the layers by a predetermined etchant.

As explained above, the present embodiment can provide a display device which can prevent the reduction in reliability and have an improved manufacturing yield, and a manufacturing method thereof.

All of the display devices and manufacturing methods thereof that can be implemented by a person of ordinary skill in the art through arbitrary design changes to the display device and manufacturing method thereof described above as the embodiment of the present invention come within the scope of the present invention as long as they are in keeping with the spirit of the present invention.

Various modification examples which may be conceived by a person of ordinary skill in the art in the scope of the idea of the present invention will also fall within the scope of the invention. For example, even if a person of ordinary skill in the art arbitrarily modifies the above embodiment by adding or deleting a structural element or changing the design of a structural element, or by adding or omitting a step or changing the condition of a step, all of the modifications fall within the scope of the present invention as long as they are in keeping with the spirit of the invention.

Further, other effects which may be obtained from the above embodiment and are self-explanatory from the descriptions of the specification or can be arbitrarily conceived by a person of ordinary skill in the art are considered as the effects of the present invention as a matter of course.