Display Panel Including an Initialization Voltage Line and an Auxiliary Voltage Line and Display Device Including the Same

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/887,760, filed May 29, 2020, which claims priority to and the benefit of Korean Patent Application No. 10-2019-0104580, filed Aug. 26, 2019, the entire content of both of which is incorporated herein by reference.

BACKGROUND

1. Field

Aspects of one or more example embodiments relate to a display panel and a display device including the same.

2. Description of Related Art

Recently, the uses of display devices have become more diversified. As display devices have become thinner and more lightweight, their range of use has gradually expanded.

As display devices are used in various ways, their shapes may be designed in various ways. Also, functions that may be combined or associated with display devices are increasing.

The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art.

SUMMARY

As a way of increasing functions that may be combined or associated with a display device, one or more example embodiments include a display device including a component area in which a camera, a sensor, etc. may be arranged inside a display area.

Additional aspects will be set forth in part in the description which follows and, in part, will be more apparent from the description, or may be learned by practice of the presented example embodiments of the disclosure.

According to one or more example embodiments, a display panel includes: a substrate including a first area and a second area surrounding the first area a plurality of display elements arranged in the second area and including a first display element and a second display element that are apart from each other with the first area therebetween, a first initialization voltage line extending in a first direction and electrically connected to the first display element, a second initialization voltage line extending in the first direction and electrically connected to the second display element, an auxiliary voltage line arranged on a layer different from layers on which the first initialization voltage line and the second initialization voltage line are arranged and electrically connecting the first initialization voltage line and the second initialization voltage line that are apart from each other, and a first insulating layer covering the first initialization voltage line, the second initialization voltage line, and the auxiliary voltage line and arranged below the plurality of display elements.

According to some example embodiments, each of the plurality of display elements may include a pixel electrode, an opposite electrode above the pixel electrode, and an emission layer between the pixel electrode and the opposite electrode, and the auxiliary voltage line may be arranged below the pixel electrode with the first insulating layer therebetween.

According to some example embodiments, the display panel may further include a second insulating layer arranged between the first and second initialization voltage lines and the auxiliary voltage line.

According to some example embodiments, the display panel may further include thin film transistors and a storage capacitor, the thin film transistors and the storage capacitor being electrically connected to the first display element, wherein the first initialization voltage line and the second initialization voltage line may include the same material as that of one of electrodes of the storage capacitor.

According to some example embodiments, the storage capacitor may include a bottom electrode and a top electrode, and the first initialization voltage line and the second initialization voltage line may include the same material as that of the top electrode.

According to some example embodiments, the display panel may further include a contact metal connecting one of the thin film transistors to the first display element, wherein the auxiliary voltage line may include the same material as that of the contact metal.

According to some example embodiments, the display panel may further include a mediation metal layer arranged between the first initialization voltage line and the auxiliary voltage line, and between the second initialization voltage line and the auxiliary voltage line.

According to some example embodiments, the display panel may further include a first scan line extending in the first direction and electrically connected to the first display element, and a second scan line extending in the first direction and electrically connected to the second display element, wherein the first scan line may be apart from the second scan line with the first area therebetween.

According to some example embodiments, the display panel may further include a first emission control line extending in the first direction and electrically connected to the first display element, and a second emission control line extending in the first direction and electrically connected to the second display element, wherein the first emission control line may be apart from the second emission control line with the first area therebetween.

According to some example embodiments, the display panel may further include an initialization power supply line arranged in an outer area of the substrate, wherein the initialization power supply line may be arranged between the substrate and the first insulating layer.

According to some example embodiments, the display panel may further include a first data line extending in a second direction intersecting the first direction and connected to the first display element, and a second data line extending in the second direction and connected to the second display element, wherein the initialization power supply line may include the same material as that of the first data line or the second data line.

According to one or more embodiments, a display device including at least one component area arranged inside a display area, and a non-display area surrounding the display area, includes a plurality of display elements constituting the display area, each of the plurality of display elements including a pixel electrode, an emission layer, and an opposite electrode that are sequentially stacked, a first initialization voltage line electrically connected to a first display element among the plurality of display elements and extending in a first direction in the display area, a second initialization voltage line electrically connected to a second display element among the plurality of display elements, extending in the first direction in the display area, and apart from the first initialization voltage line with the at least one component area therebetween, an auxiliary voltage line electrically connecting the first initialization voltage line to the second initialization voltage line, and a first insulating layer arranged between the auxiliary voltage line and the pixel electrode.

According to some example embodiments, the display device may further include a second insulating layer arranged between the first and second initialization lines and the auxiliary voltage line.

According to some example embodiments, the display device may further include thin film transistors and a storage capacitor, the thin film transistors being electrically connected to the first display element, and the storage capacitor including a bottom electrode and a top electrode, wherein the first initialization voltage line and the second initialization voltage line may include the same material as that of the top electrode of the storage capacitor.

According to some example embodiments, the display device may further include a contact metal connecting one of the thin film transistors to the first display element, wherein the auxiliary voltage line may include the same material as that of the contact metal.

According to some example embodiments, the first initialization voltage line and the second initialization voltage line may be arranged on the same layer.

According to some example embodiments, the display device may further include a mediation metal layer arranged between the first initialization voltage line and the auxiliary voltage line, and between the second initialization voltage line and the auxiliary voltage line.

According to some example embodiments, the display device may further include a first scan line extending in the first direction and electrically connected to the first display element, and a second scan line extending in the first direction and electrically connected to the second display element, wherein the first scan line may be apart from the second scan line with the at least one component area therebetween.

According to some example embodiments, the display device may further include a first emission control line extending in the first direction and electrically connected to the first display element, and a second emission control line extending in the first direction and electrically connected to the second display element, wherein the first emission control line may be apart from the second emission control line with the at least one component area therebetween.

According to some example embodiments, the display device may further include an initialization power supply line arranged in the non-display area.

According to some example embodiments, the initialization power supply line may be arranged below the first insulating layer.

According to some example embodiments, the display device may further include a first data line extending in a second direction intersecting the first direction and connected to the first display element, and a second data line extending in the second direction and connected to the second display element, wherein the initialization power supply line may include the same material as that of the first data line or the second data line.

According to some example embodiments, the at least one component area may include a first component area and a second component area arranged in the first direction.

According to some example embodiments, the first initialization voltage line may be located on one side of the first component area, and the second initialization voltage line may be located on one side of the second component area, and the first component area and the second component area may be located between the first initialization voltage line and the second initialization voltage line that are apart from each other.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features, and characteristics of certain example embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a perspective view of a display device according to some example embodiments;

FIGS. 2 A to 2 D are cross-sectional views of a display device according to some example embodiments;

FIGS. 3 A to 3 C are cross-sectional views of a display device according to some example embodiments;

FIG. 4 A is a plan view of a display panel according to some example embodiments;

FIG. 4 B is a plan view of a display panel according to some example embodiments;

FIG. 5 is an equivalent circuit diagram of one of pixels of a display panel according to some example embodiments;

FIGS. 6 A and 6 B are plan views of one of pixels of a display panel according to some example embodiments;

FIGS. 7 A and 7 B are cross-sectional views of the pixel taken along the lines Aa-Aa′ and Ba-Ba′ of FIGS. 6 A and 6 B ;

FIGS. 8 A and 8 B are plan views of wiring lines around a component area according to some example embodiments;

FIGS. 9 A and 9 B are cross-sectional views of the wiring lines taken along the line IX-IX′ of FIGS. 8 A and 8 B ;

FIG. 10 is a plan view of a display panel according to some example embodiments;

FIG. 11 is a plan view of wiring lines around a plurality of component areas according to some example embodiments;

FIG. 12 is a plan view of wiring lines around a second non-display area according to some example embodiments; and

FIGS. 13 A and 13 B are cross-sectional views of a display device according to some example embodiments.

DETAILED DESCRIPTION

Reference will now be made in more detail to aspects of some embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

Hereinafter, aspects of some example embodiment of the present invention are described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same or corresponding elements, and repeated description thereof is omitted.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These elements are only used to distinguish one element from another.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

It will be understood that when a layer, region, or element is referred to as being “formed on,” another layer, region, or element, it can be directly or indirectly formed on the other layer, region, or element. That is, for example, intervening layers, regions, or elements may be present.

Sizes of elements in the drawings may be exaggerated for convenience of explanation. In other words, because sizes and thicknesses of elements in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

In the present specification, “A and/or B” means A or B, or A and B. In the present specification, “at least one of A and B” means A or B, or A and B.

It will be understood that when a layer, region, or element is referred to as being “connected” to another layer, region, or element, it may be “directly connected” to the other layer, region, or element and/or may be “indirectly connected” to the other layer, region, or element with other layer, region, or element interposed therebetween. For example, it will be understood that when a layer, region, or element is referred to as being “electrically connected” to another layer, region, or element, it may be “directly electrically connected” to the other layer, region, or element and/or may be “indirectly electrically connected” to other layer, region, or element with other layer, region, or element interposed therebetween.

In the following examples, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

FIG. 1 is a perspective view of a display device 1 according to some example embodiments.

Referring to FIG. 1 , the display device 1 may include a display area DA that emits light and a non-display area NDA that does not emit light. The display device 1 may display an image by using light emitted from a plurality of pixels arranged in the display area DA.

The display device 1 may include a component area OA, for example, located within, or at least partially within the display area DA. That is, the component area OA may be at least partially surrounded by the display area DA. For example, as shown in FIG. 1 , according to some example embodiments, the component area OA may be entirely surrounded by the display area DA.

The non-display area NDA may include a first non-display area NDA 1 and a second non-display area NDA 2 , the first non-display area NDA 1 surrounding the component area OA, and the second non-display area NDA 2 surrounding the outside of the display area DA. For example, the first non-display area NDA 1 may entirely surround the component area OA, the display area DA may entirely surround the first non-display area NDA 1 , and the second non-display area NDA 2 may entirely surround the display area DA.

Thus, according to some example embodiments, the display device 1 may include a component area OA located within, or surrounded by, a first non-display area NDA 1 , and the first non-display area NDA 1 and the component area OA may both be located within the display area DA. Embodiments of the present invention, however, are not limited to the component area OA being located entirely within the display area DA. For example, according to some example embodiments, the component area OA may extend outside a border or edge of the display area. Additionally, according to some example embodiments, the first non-display area NDA 1 or the second non-display area NDA 2 may be omitted, or the first non-display area NDA 1 and the second non-display area NDA 2 may be connected to or merged with each other.

As described below with reference to FIG. 2 A , the component area OA may be a location in which a component is arranged. The component area OA may be a transmission area through which light and/or sound output from a component to the outside or progressing from the outside toward the component may pass. According to some example embodiments, in the case where light passes through the component area OA, a light transmittance may be 50% or more, or, according to some example embodiments, 70% or more, 75% or more, 80% or more, or 85% or more, or 90% or more.

Hereinafter, although the display device 1 is described in the context of an organic light-emitting display device as an example, a display device according to embodiments of the present disclosure is not limited thereto. According to some example embodiments, the display device 1 may be various ones, for example, an inorganic light-emitting display and a quantum dot light-emitting display. For example, an emission layer of a display element provided to the display device 1 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

Though it is shown in FIG. 1 that the component area OA is arranged on one side (an upper right side) of the display area DA, the embodiments according to the present disclosure are not limited thereto. For example, a shape of the display area DA may be a circle, an ellipse, or a polygon such as a triangle, or a pentagon, or any other suitable shape according to the design of the display device 1 (and/or the location of the component area OA). A location of the component area OA may be variously changed. For example, the component area OA may be arranged in an upper central portion of a plane (e.g., an x-y plane) of the display area DA.

FIGS. 2 A to 2 D are cross-sectional views of the display device 1 according to embodiments. For example, FIGS. 2 A to 2 D may correspond to a cross-section taken along the line II-II′ of FIG. 1 .

Referring to FIG. 2 A , the display device 1 may include a display panel 10 and a component 20 , the display panel 10 including a display element, and the component 20 corresponding to the component area OA.

The display panel 10 may include a substrate 100 , an encapsulation substrate 300 , and a display layer 200 therebetween, the encapsulation substrate 300 serving as an encapsulation member facing the substrate 100 . A sealing material 350 (sealant) covering lateral sides of the display layer 200 may be arranged between the substrate 100 and the encapsulation substrate 300 . Though it is shown in FIG. 2 A that the sealing material 350 is arranged on two opposite sides of the component area OA, the component area OA may be entirely surrounded by the sealing material 350 when viewed in a direction perpendicular to a main surface of the substrate 100 (e.g., when viewed from a plan view or a direction normal to the planar surface of the display panel 10 ).

The substrate 100 may include glass or a polymer resin. The polymer resin may include any suitable polymer resin material, for example, polyethersulfone (PES), polyarylate, polyetherimide (PEI), polyacrylate, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), cellulose tri acetate (TAC), and cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multi-layered structure including a layer including the above polymer resin and an inorganic layer. The encapsulation substrate 300 may include any suitable encapsulation substrate material, for example, glass or the polymer resin.

The display layer 200 may include a circuit layer, an organic light-emitting diode OLED, and an insulating layer therebetween, the circuit layer including a thin film transistor TFT, and the organic light-emitting diode OLED serving as a display element connected to the thin film transistor TFT. The thin film transistor TFT and the organic light-emitting diode OLED connected thereto may be arranged in the display area DA. Some of wiring lines WL of the display layer 200 may be located in the first non-display area NDA 1 . The wiring lines WL may provide a signal or voltage (e.g., a set or predetermined signal or voltage) to pixels apart from each other with the component area OA therebetween. Though it is shown in FIG. 2 A that the wiring lines WL do not overlap the sealing material 350 in the first non-display area NDA 1 , a portion of the sealing material 350 may overlap the wiring lines WL according to some example embodiments.

The display panel 10 may include a through hole 10 H corresponding to the component area OA. For example, the substrate 100 and the encapsulation substrate 300 may respectively include through holes 100 H and 300 H each corresponding to the component area OA. The display layer 200 may include a through hole corresponding to the component area OA.

According to some example embodiments, elements such as an input sensing member, a reflection prevention member, and a transparent window may be further arranged on the display panel 10 , the input sensing member sensing a touch input, and the reflection prevention member including a polarizer and a retarder, or a color filter and a black matrix.

The component 20 may be located in the component area OA. The component 20 may be an electronic element that uses light or sound. For example, an electronic element may be a sensor such as an infrared sensor that emits and/or receives light, a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure a distance or recognize a fingerprint, a small lamp that outputs light, or a speaker that outputs sound. An electronic element that uses light may use light in various wavelength bands such as visible light, infrared light, and ultraviolet light. As shown in FIG. 2 A , in the case where the display panel 10 includes a through hole 10 H corresponding to the component area OA, light or sound output from or received by the electronic element may be more effectively utilized.

Unlike the display panel 10 including the through hole 10 H corresponding to the component area OA, some of elements of the display panel 10 may not include a through hole. For example, as shown in FIG. 2 B , the encapsulation substrate 300 includes the through hole 300 H corresponding to the component area OA, but the substrate 100 may not include a through hole.

Alternatively, as shown in FIGS. 2 C and 2 D , both the substrate 100 and the encapsulation substrate 300 may not include the through holes corresponding to the component area OA. In FIG. 2 C , the sealing material 350 may be arranged in the first non-display area NDA 1 to surround the component area OA.

Unlike FIG. 2 C , the sealing material 350 may not be provided around the component area OA in FIG. 2 D . An outer sealing material 360 may be located in the second non-display area NDA 2 and may seal the display layer 200 from external air by bonding the substrate 100 to the encapsulation substrate 300 . According to some example embodiments, the display device 1 of FIGS. 2 A to 2 C may also include the outer sealing material 360 that surrounds the display area DA.

An insulating layer IL of FIG. 2 D may have an opening IL-OP corresponding to the component area OA. According to some example embodiments, in the component area OA, any element may not be arranged between the substrate 100 and the encapsulation substrate 300 . According to some example embodiments, a portion of an inorganic insulating layer(s) such as a buffer layer may remain in the component area OA of the substrate 100 .

Though it is shown in FIGS. 2 A to 2 D that the component 20 is located below the display panel 10 , that is, located on one side of the substrate 100 , the component 20 may be at least partially inserted and located inside the through hole 10 H so as to overlap lateral sides of the display panel 10 that define the through hole 10 H in FIG. 2 A .

The component 20 may include another member besides the electronic element. According to some example embodiments, in the case where the display device 1 is used as a smartwatch or an instrument panel for an automobile, the component 20 may be a member such as clock hands or a needle indicating information (e.g., set or predetermined information) (e.g. the velocity of a vehicle, etc.). Alternatively, the component 20 may include an element such as an accessory that increases aesthetic sense of the display panel 10 .

FIGS. 3 A to 3 C are cross-sectional views of the display device 1 according to other embodiments and may correspond to cross-sections of the display device 1 taken along the line II-II′ of FIG. 1 .

Referring to FIG. 3 A , like the display device 1 described with reference to FIG. 2 A , the display device 1 may include the display panel 10 and the component 20 . Also, according to some example embodiments, the display device 1 may further include an input sensing member sensing a touch input, a reflection prevention member, a window, etc. arranged on the display panel 10 .

Unlike the display panel 10 including the encapsulation substrate 300 as an encapsulation member and the sealing material 350 described above with reference to FIG. 2 A , the display panel 10 according to the present embodiment may include a thin-film encapsulation layer 300 ′ as an encapsulation member. In the case where the display panel 10 includes the thin-film encapsulation layer 300 ′ as an encapsulation member, the flexibility of the display panel 10 may be improved even more. Hereinafter, for convenience of description, a difference is mainly described.

The thin-film encapsulation layer 300 ′ may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, as shown in FIG. 3 A , the thin-film encapsulation layer 300 ′ may include a first inorganic encapsulation layer 310 , a second inorganic encapsulation layer 330 , and an organic encapsulation layer 320 therebetween.

The first and second inorganic encapsulation layers 310 and 330 may include a suitable inorganic encapsulation layer material, for example, at least one inorganic insulating material selected from the group consisting of aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 ), silicon oxide (SiO 2 ), silicon nitride (SiN x ), and silicon oxynitride (SiON). The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include an acryl-based resin, an epoxy-based resin, polyimide, and polyethylene.

The display panel 10 may include the through hole 10 H corresponding to the component area OA. For example, the substrate 100 , the display layer 200 , and the thin-film encapsulation layer 300 ′ may respectively include through holes 100 H, 200 H, and 300 H each corresponding to the component area OA. The thin-film encapsulation layer 300 ′, for example, the first inorganic encapsulation layer 310 , the second inorganic encapsulation layer 330 , and the organic encapsulation layer 320 each may include holes corresponding to the component area OA. A size of the hole of the organic encapsulation layer 320 may be greater than sizes of the holes of the first and second inorganic encapsulation layers 310 and 330 , and thus the first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 around the component area OA.

Unlike FIG. 3 A , some elements of the display panel 10 may not include a through hole. As shown in FIG. 3 B , the display layer 200 and the thin-film encapsulation layer 300 ′ may respectively include the through holes 200 H and 300 H corresponding to the component area OA, but the substrate 100 may not include a through hole.

According to some example embodiments, as shown in FIG. 3 C , all of the substrate 100 , the display layer 200 , and the thin-film encapsulation layer 300 ′ may not include through holes corresponding to the component area OA.

Even though the substrate 100 does not include the through hole 100 H as shown in FIGS. 3 B and 3 C , portions of the display layer 200 that correspond to the component area OA may be at least partially removed and thus a light transmittance for the electronic element, which is the component 20 , may be secured.

In the case where the thin-film encapsulation layer 300 ′ does not include the through hole, the at least one inorganic encapsulation layer and the at least one organic encapsulation layer each may cover a portion of the substrate 100 in the component area OA. For example, the display layer 200 arranged between the substrate 100 and the thin-film encapsulation layer 300 ′ may not cover a portion of the substrate 100 that corresponds to the component area OA. The portion of the substrate 100 that corresponds to the component area OA may be covered by the thin-film encapsulation layer 300 ′.

Though it is shown in FIGS. 3 A to 3 C that all of the insulating layer IL corresponding to the component area OA is removed, some layers of the insulating layer IL, which is a multi-layer, corresponding to the component area OA may be removed in the display panel 10 according to some example embodiments.

Though it is shown in FIGS. 3 A to 3 C that the component 20 is located below the display panel 10 , that is, located on one side of the substrate 100 , the component 20 may be at least partially inserted and located inside the through hole 10 H so as to overlap lateral sides of the display panel 10 that define the through hole 10 H in FIG. 3 A .

FIGS. 4 A and 4 B are plan views of the display panel 10 according to some example embodiments, and FIG. 5 is an equivalent circuit diagram of one of pixels of the display panel 10 according to some example embodiments.

Referring to FIG. 4 A , the display panel 10 may include a plurality of pixels P arranged in the display area DA. Each pixel P may include a display element such as an organic light-emitting diode. Each pixel P may emit, for example, red, green, blue, or white light through an organic light-emitting diode. In the present specification, a pixel P may be a sub-pixel that emits red, green, blue, or white light as described above.

As shown in FIG. 5 , a pixel P may include a pixel circuit PC and an organic light-emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor. The plurality of thin film transistors and the storage capacitor may be connected to signal lines SL, SL−1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

The plurality of thin film transistors may include a driving thin film transistor T 1 , a switching thin film transistor T 2 , a compensation thin film transistor T 3 , a first initialization thin film transistor T 4 , an operation control thin film transistor T 5 , an emission control thin film transistor T 6 , and a second initialization thin film transistor T 7 .

The signal lines include the scan line SL, a previous scan line SL−1, the emission control line EL, and the data line DL, the scan line SL transferring a scan signal Sn, the previous scan line SL−1 transferring a previous scan signal Sn−1 to the first initialization thin film transistor T 4 and the second initialization thin film transistor T 7 , the emission control line EL transferring an emission control signal En to the operation control thin film transistor T 5 and the emission control thin film transistor T 6 , and the data line DL intersecting with the scan line SL and transferring a data signal Dm.

The driving voltage line PL transfers a driving voltage ELVDD (also referred to as first power) to the driving thin film transistor T 1 . The initialization voltage line VL transfers an initialization voltage Vint initializing the driving thin film transistor T 1 and a pixel electrode of the organic light-emitting diode OLED.

A driving gate electrode G 1 of the driving thin film transistor T 1 is connected to a first storage capacitor plate Cst 1 of the storage capacitor Cst, a driving source electrode S 1 of the driving thin film transistor T 1 is connected to the driving voltage line PL through the operation control thin film transistor T 5 , and a driving drain electrode D 1 of the driving thin film transistor T 1 is electrically connected to the pixel electrode of an organic light-emitting diode OLED through the emission control thin film transistor T 6 . The driving thin film transistor T 1 receives a data signal Dm depending on a switching operation of the switching thin film transistor T 2 and supplies a driving current I OLED to the organic light-emitting diode OLED.

A switching gate electrode G 2 of the switching thin film transistor T 2 is connected to the scan line SL, a switching source electrode S 2 of the switching thin film transistor T 2 is connected to the data line DL, and a switching drain electrode D 2 of the switching thin film transistor T 2 is connected to the driving source electrode S 1 of the driving thin film transistor T 1 and simultaneously connected to the driving voltage line PL through the operation control thin film transistor T 5 . The switching thin film transistor T 2 is turned on in response to a scan signal Sn transferred through the scan line SL and performs a switching operation of transferring a data signal Dm transferred through the data line DL to the driving source electrode S 1 of the driving thin film transistor T 1 .

A compensation gate electrode G 3 of the compensation thin film transistor T 3 is connected to the scan line SL, a compensation source electrode S 3 of the compensation thin film transistor T 3 is connected to the driving drain electrode D 1 of the driving thin film transistor T 1 and simultaneously connected to the pixel electrode of the organic light-emitting diode OLED through the emission control thin film transistor T 6 . A compensation drain electrode D 3 of the compensation thin film transistor T 3 is connected to the first storage capacitor plate Cst 1 of the storage capacitor Cst, a first initialization drain electrode D 4 of the first initialization thin film transistor T 4 , and the driving gate electrode G 1 of the driving thin film transistor T 1 . The compensation thin film transistor T 3 is turned on in response to a scan signal Sn transferred through the scan line SL and may compensate for the driving thin film transistor T 1 by electrically connecting the driving gate electrode G 1 to the driving drain electrode D 1 of the driving thin film transistor T 1 .

A first initialization gate electrode G 4 of the first initialization thin film transistor T 4 is connected to the previous scan line SL−1, a first initialization source electrode S 4 of the first initialization thin film transistor T 4 is connected to a second initialization drain electrode D 7 of the second initialization thin film transistor T 7 and the initialization voltage line VL. A first initialization drain electrode D 4 of the first initialization thin film transistor T 4 is connected to the first storage capacitor plate Cst 1 of the storage capacitor Cst, the compensation drain electrode D 3 of the compensation thin film transistor T 3 , and the driving gate electrode G 1 of the driving thin film transistor T 1 . The first initialization thin film transistor T 4 is turned on in response to a previous scan signal Sn−1 transferred through the previous scan line SL−1 and transfers an initialization voltage Vint to the driving gate electrode G 1 of the driving thin film transistor T 1 , thereby initializing a voltage of the driving gate electrode G 1 of the driving thin film transistor T 1 .

An operation control gate electrode G 5 of the operation control thin film transistor T 5 is connected to the emission control line EL, an operation control source electrode S 5 of the operation control thin film transistor T 5 is connected to the driving voltage line PL. An operation control drain electrode D 5 of the operation control thin film transistor T 5 is connected to the driving source electrode S 1 of the driving thin film transistor T 1 and the switching drain electrode D 2 of the switching thin film transistor T 2 .

An emission control gate electrode G 6 of the emission control thin film transistor T 6 is connected to the emission control line EL, an emission control source electrode S 6 of the emission control thin film transistor T 6 is connected to the driving drain electrode D 1 of the driving thin film transistor T 1 and the compensation source electrode S 3 of the compensation thin film transistor T 3 . An emission control drain electrode D 6 of the emission control thin film transistor T 6 is connected to the second initialization source electrode S 7 of the second initialization thin film transistor T 7 and the pixel electrode of the organic light-emitting diode OLED.

The operation control thin film transistor T 5 and the emission control thin film transistor T 6 are simultaneously turned on in response to an emission control signal En transferred through the emission control line EL to allow the driving voltage ELVDD to be transferred to the organic light-emitting diode OLED and thus the driving current I OLED to flow through the organic light-emitting diode OLED.

A second initialization gate electrode G 7 of the second initialization thin film transistor T 7 is connected to the previous scan line SL−1, the second initialization source electrode S 7 of the second initialization thin film transistor T 7 is connected to the emission control drain electrode D 6 of the emission control thin film transistor T 6 and the pixel electrode of the organic light-emitting diode OLED. The second initialization drain electrode D 7 of the second initialization thin film transistor T 7 is connected to the first initialization source electrode S 4 of the first initialization thin film transistor T 4 and the initialization voltage line VL. The second initialization thin film transistor T 7 is turned on in response to a previous scan signal Sn−1 transferred through the previous scan line SL−1 and may initialize the pixel electrode of the organic light-emitting diode OLED.

Though FIG. 5 shows the case where the first initialization thin film transistor T 4 and the second initialization thin film transistor T 7 are connected to the previous scan line SL−1, the embodiment is not limited thereto. For example, according to some example embodiments, the first initialization thin film transistor T 4 may be connected to the previous scan line SL−1 and driven in response to a previous scan signal Sn−1, and the second initialization thin film transistor T 7 may be connected to a separate signal line (for example, the next scan line) and driven in response to a signal transferred through the separate signal line.

A second storage capacitor plate Cst 2 of the storage capacitor Cst is connected to the driving voltage line PL, and an opposite electrode of the organic light-emitting diode OLED is connected to a common voltage ELVSS (also referred to as second power). Therefore, the organic light-emitting diode OLED may receive the driving current I OLED from the driving thin film transistor T 1 and emit light to thereby display an image.

Though it is shown in FIG. 5 that the compensation thin film transistor T 3 and the first initialization thin film transistor T 4 each have a dual gate electrode, the compensation thin film transistor T 3 and the first initialization thin film transistor T 4 each may have one gate electrode.

Referring to FIG. 4 A again, each pixel P may be electrically connected to driving circuits arranged in the non-display area, for example, the second non-display area NDA 2 . A first scan driving circuit 110 , a second scan driving circuit 120 , a terminal 140 , a data driving circuit 150 , a first power supply line 160 , a second power supply line 170 , a first initialization power supply line 181 , and a second initialization power supply line 182 may be arranged in the second non-display area NDA 2 .

The first scan driving circuit 110 may supply a scan signal to each pixel P through a scan line SL. The first scan driving circuit 110 may provide an emission control signal to each pixel P through an emission control line EL. The second scan driving circuit 120 may be parallel to the first scan driving circuit 110 with the display area DA therebetween. Some of the pixels P arranged in the display area DA may be electrically connected to the first scan driving circuit 110 . The other pixels P that are not connected to the first scan driving circuit 110 may be electrically connected to the second scan driving circuit 120 . According to some example embodiments, one of the first scan driving circuit 110 and the second scan driving circuit 120 may be omitted.

The terminal 140 may be arranged on one side of the substrate 100 . The terminal 140 may be exposed and electrically connected to a printed circuit board PCB by not being covered by an insulating layer. A terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10 . The printed circuit board PCB transfers a signal of a controller or power to the display panel 10 . The printed circuit board PCB may transfer a control signal generated by the controller to the first scan driving circuit 110 and the second scan driving circuit 120 .

The data driving circuit 150 may be electrically connected to the data line DL. A data signal of the data driving circuit 150 may be provided to each pixel P through a connection line 151 connected to the terminal 140 , and the data line DL connected to the connection line 151 . Though it is shown in FIGS. 4 A and 4 B that the data driving circuit 150 is arranged on the printed circuit board PCB, the data driving circuit 150 may be arranged on the substrate 100 according to some example embodiments. For example, the data driving circuit 150 may be arranged between the terminal 140 and the first power supply line 160 .

The first power supply line 160 may include a first sub-line 162 and a second sub-line 163 each being parallel to each other with the display area DA therebetween and extending in an x-direction. The driving voltage line PL extending so as to cross the display area DA may be connected to the first sub-line 162 and the second sub-line 163 . The second power supply line 170 may have a loop shape having one open side and partially surround the display area DA. The first power supply line 160 may provide the first power ELVDD (see FIG. 5 ) to each pixel P, and the second power supply line 170 may provide the second power ELVSS (see FIG. 5 ) to each pixel P as described above.

The first and second initialization power supply lines 181 and 182 may be arranged in the second non-display area NDA 2 . The first and second initialization power supply lines 181 and 182 respectively have shapes at least surrounding the left and the right of the display area DA and may extend in a y-direction. For example, the first and second initialization power supply lines 181 and 182 may be apart from each other with the display area DA therebetween. The first and second initialization power supply lines 181 and 182 may extend in the y-direction and a portion of the first and second initialization power supply lines 181 and 182 may have a shape bent toward the display area DA along an edge corner of the display area DA. The first and second initialization power supply lines 181 and 182 may provide an initialization voltage to each pixel P through the initialization voltage line VL.

The component area OA may be located inside the display area DA. The plurality of pixels P may be arranged around the component area OA. The plurality of pixels P may surround the component area OA.

As shown in FIG. 4 A , the component area OA may be arranged in an upper right portion of the display area DA. According to some example embodiments, as shown in FIG. 4 B , the component area OA may be arranged in an upper central portion of the display area DA. For example, in the case where the component area OA is arranged in a central portion of the display area DA, a difference in an emission characteristic between pixels P on the left of the component area OA and pixels P on the right of the component area OA may be reduced. According to some example embodiments, the component area OA may be arranged in various locations inside the display area DA such as an upper left portion, a lower right portion, a lower left portion, and a central portion inside the display area DA. Though it is shown in FIGS. 4 A and 4 B that one component area OA is provided, the component area OA may be provided as a plurality of component areas inside the display area OA according to some example embodiments.

Detouring lines may be arranged in the first non-display area NDA 1 , the detouring lines applying a signal or power (e.g., a set or predetermined signal or power) to pixels P apart from each other around the component area OA. A relevant structure is described below with reference to FIG. 8 .

The display panel described with reference to FIGS. 4 A and 4 B may be a figure of the substrate 100 . For example, the substrate 100 may include a first area, a second area, a third area, and a fourth area, the first area corresponding to the component area OA, the second area corresponding to the display area DA, the third area corresponding to the first non-display area NDA 1 , and the fourth area corresponding to the second non-display area NDA 2 . A plurality of pixels P are arranged in the second area of the substrate 100 to constitute the display area DA of the display panel that may display an image. The fourth area of the substrate 100 is an outer area of the substrate 100 that surrounds the second area. The first scan driving circuit 110 , the second scan driving circuit 120 , the terminal 140 , the data driving circuit 150 , the first power supply line 160 , the second power supply line 170 , the first initialization power supply line 181 , and the second initialization power supply line 182 may be arranged in the fourth area.

FIGS. 6 A and 6 B are plan views of one of pixels of a display panel according to some example embodiments, and FIGS. 7 A and 7 B are cross-sectional views of the pixel taken along the lines Aa-Aa′ and Ba-Ba′ of FIGS. 6 A and 6 B .

Referring to FIGS. 6 A and 7 A , the driving thin film transistor T 1 , the switching thin film transistor T 2 , the compensation thin film transistor T 3 , the first initialization thin film transistor T 4 , the operation control thin film transistor T 5 , the emission control thin film transistor T 6 , and the second initialization thin film transistor T 7 may be arranged along a semiconductor layer 1130 .

Some regions of the semiconductor layer 1130 may correspond to semiconductor layers of the driving thin film transistor T 1 , the switching thin film transistor T 2 , the compensation thin film transistor T 3 , the first initialization thin film transistor T 4 , the operation control thin film transistor T 5 , the emission control thin film transistor T 6 , and the second initialization thin film transistor T 7 . In other words, the semiconductor layers of the driving thin film transistor T 1 , the switching thin film transistor T 2 , the compensation thin film transistor T 3 , the first initialization thin film transistor T 4 , the operation control thin film transistor T 5 , the emission control thin film transistor T 6 , and the second initialization thin film transistor T 7 may be connected to each other and may have a shape bent in various directions.

The semiconductor layer 1130 is located over the substrate 100 . It is shown in FIG. 7 A that a portion of the semiconductor layer 1130 , for example, a driving semiconductor layer 1130 a , a compensation semiconductor layer 1130 c , and an emission control semiconductor layer 1130 f are located over the substrate 100 .

A buffer layer IL 1 may be formed under the semiconductor layer 1130 , the buffer layer IL 1 including an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride.

The semiconductor layer 1130 may include a channel region, a source region, and a drain region, the source region and the drain region being on two opposite sides of the channel region. The source region and the drain region may be respectively a source electrode and a drain electrode of a thin film transistor. Hereinafter, for convenience of description, a source region and a drain region are respectively referred to as a source electrode and a drain electrode.

The driving thin film transistor T 1 includes the driving gate electrode G 1 , the driving source electrode S 1 , and the driving drain electrode D 1 , the driving gate electrode G 1 overlapping a driving channel region, and the driving source electrode S 1 and the driving drain electrode D 1 being on two opposite sides of the driving channel region. The driving channel region overlapped with the driving gate electrode G 1 may form a long channel length in a narrow space by having a structure bent in various shapes. For example, in the case where a length of the driving channel region is formed long, a driving range of a gate voltage widens and gradation of light emitted from an organic light-emitting diode OLED may be more elaborately controlled, and a display quality may be improved.

The switching thin film transistor T 2 includes the switching gate electrode G 2 , the switching source electrode S 2 , and the switching drain electrode D 2 , the switching gate electrode G 2 overlapping a switching channel region, and the switching source electrode S 2 and the switching drain electrode D 2 being on two opposite sides of the switching channel region. The switching drain electrode D 2 may be connected to the driving source electrode S 1 .

The compensation thin film transistor T 3 is a dual thin film transistor and may include the compensation gate electrodes G 3 , the compensation source electrode S 3 , and the compensation drain electrode D 3 , the compensation gate electrodes G 3 overlapping two compensation channel regions, and the compensation source electrode S 3 and the compensation drain electrode D 3 being on two opposite sides of the compensation channel region. The compensation thin film transistor T 3 may be connected to the driving gate electrode G 1 of the driving thin film transistor T 1 through a node connection line 1174 described below.

The first initialization thin film transistor T 4 is a dual thin film transistor and may include the first initialization gate electrodes G 4 , the first initialization source electrode S 4 , and the first initialization drain electrode D 4 , the first initialization gate electrodes G 4 overlapping two first initialization channel regions, and the first initialization source electrode S 4 and the first initialization drain electrode D 4 being on two opposite sides of the first initialization channel region.

The operation control thin film transistor T 5 may include the operation control gate electrode G 5 , the operation control source electrode S 5 , and the operation control drain electrode D 5 , the operation control gate electrode G 5 overlapping an operation control channel region, and the operation control source electrode S 5 and the operation control drain electrode D 5 being on two opposite sides of the operation control channel region. The operation control drain electrode D 5 may be connected to the driving source electrode S 1 .

The emission control thin film transistor T 6 may include the emission control gate electrode G 6 , the emission control source electrode S 6 , and the emission control drain electrode D 6 , the emission control gate electrode G 6 overlapping an emission control channel region, and the emission control source electrode S 6 and the emission control drain electrode D 6 being on two opposite sides of the emission control channel region. The emission control source electrode S 6 may be connected to the driving drain electrode D 1 .

The second initialization thin film transistor T 7 may include the second initialization gate electrode G 7 , the second initialization source electrode S 7 , and the second initialization drain electrode D 7 , the second initialization gate electrode G 7 overlapping a second initialization channel region, and the second initialization source electrode S 7 and the second initialization drain electrode D 7 being on two opposite sides of the second initialization channel region.

The above-described thin film transistors may be connected to the signal lines SL, SL−1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

A gate insulating layer IL 2 (see FIG. 7 A ) may be arranged on the semiconductor layer 1130 . The scan line SL, the previous scan line SL−1, the emission control line EL, and the driving gate electrode G 1 may be arranged on the gate insulating layer IL 2 .

The gate insulating layer IL 2 may include an inorganic material such as silicon oxide, silicon nitride, and silicon oxynitride. The scan line SL, the previous scan line SL−1, the emission control line EL, and the driving gate electrode G 1 may include a metal such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and an alloy thereof.

The scan line SL may extend in the x-direction. Some regions of the scan line SL may respectively correspond to the switching and compensation gate electrodes G 2 and G 3 . For example, regions of the scan line SL that overlap the switching and compensation thin film transistors T 2 and T 3 may be the switching and compensation gate electrodes G 2 and G 3 , respectively.

The previous scan line SL−1 may extend in the x-direction and some regions of the previous scan line SL−1 may respectively correspond to the first and second initialization gate electrodes G 4 and G 7 . For example, regions of the previous scan line SL−1 that overlap the channel regions of the first and second initialization thin film transistors T 4 and T 7 may be the first and second initialization gate electrodes G 4 and G 7 , respectively.

The emission control line EL may extend in the x-direction. Some regions of the emission control line EL may respectively correspond to the operation control and emission control gate electrodes G 5 and G 6 . For example, regions of the emission control line EL that overlap the channel regions of the operation control and emission control thin film transistors T 6 and T 7 may be the operation control and emission control gate electrodes G 5 and G 6 , respectively.

The driving gate electrode G 1 is an island type electrode and may be connected to the compensation thin film transistor T 3 through the node connection line 1174 .

An electrode voltage line HL and the initialization voltage line VL may be arranged over the scan line SL, the previous scan line SL−1, the emission control line EL, and the driving gate electrode G 1 with a first interlayer insulating layer IL 3 (see FIG. 7 A ) including an inorganic material therebetween.

As shown in FIG. 6 A , the electrode voltage line HL may extend in the x-direction so as to intersect the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G 1 and constitute the storage capacitor Cst in cooperation with the driving gate electrode G 1 . For example, the driving gate electrode G 1 may serve as the first storage capacitor plate Cst 1 (or a bottom electrode) of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as the second storage capacitor plate Cst 2 (or a top electrode) of the storage capacitor Cst.

The second storage capacitor plate Cst 2 , which is a portion of the electrode voltage line HL, is electrically connected to the driving voltage line PL. It is shown in FIG. 6 A that the electrode voltage line HL is connected to the driving voltage line PL arranged on the electrode voltage line HL through a contact hole 1158 . The electrode voltage line HL may have the same voltage level (a constant voltage, e.g. +5V) as that of the driving voltage line PL. The electrode voltage line HL is a kind of a driving voltage line in a transverse direction (x-direction).

Because the driving voltage line PL extends in the y-direction and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the x-direction intersecting the y-direction, a plurality of driving voltage lines PL and electrode voltage lines HL may constitute a mesh structure in the display area DA.

The initialization voltage line VL may extend in the x-direction. The initialization voltage line VL may be connected to the first and second initialization thin film transistors T 4 and T 7 through an initialization connection line 1173 . The initialization voltage line VL may be arranged on the first interlayer insulating layer IL 3 . For example, the initialization voltage line VL may be arranged on the same layer (e.g. the first interlayer insulating layer IL 3 ) as a layer on which the electrode voltage line HL and/or the second storage capacitor plate Cst 2 , which is the top electrode of the storage capacitor Cst, is arranged and may include the same material as that of the second storage capacitor plate Cst 2 .

The electrode voltage line HL and the initialization voltage line VL may include metal such as Mo, Al, Cu, and Ti, and an alloy thereof.

The data line DL, the driving voltage line PL, the initialization connection line 1173 , the node connection line 1174 , and a first connection metal 1175 may be arranged over the second storage capacitor plate Cst 2 and the electrode voltage line HL with a second interlayer insulating layer IL 4 (see FIG. 7 A ) including an inorganic material therebetween. Because the data line DL, the driving voltage line PL, the initialization connection line 1173 , the node connection line 1174 , and the first connection metal 1175 are formed during the same process, they may include the same material. The data line DL, the driving voltage line PL, the initialization connection line 1173 , the node connection line 1174 , and the first connection metal 1175 may include a single layer or a multi-layer including at least one of Al, Cu, Ti, etc. According to some example embodiments, the driving voltage line PL and the data line DL may have a multi-layered structure of Ti/Al/Ti.

The data line DL may extend in the y-direction and be connected to the switching source electrode S 2 of the switching thin film transistor T 2 through a contact hole 1154 . A portion of the data line DL may be the switching source electrode S 2 (that is, an electrode layer).

The driving voltage line PL may extend in the y-direction and be connected to the electrode voltage line HL through the contact hole 1158 as described above. Also, the driving voltage line PL may be connected to the operation control thin film transistor T 5 through a contact hole 1155 . The driving voltage line PL may be connected to the operation control drain electrode D 5 through the contact hole 1155 .

One end of the initialization connection line 1173 may be connected to the first and second initialization thin film transistors T 4 and T 7 through a contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to the initialization voltage line VL through a contact hole 1151 .

One end of the node connection line 1174 may be connected to the compensation drain electrode D 3 through a contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G 1 through a contact hole 1157 .

A first planarization insulating layer IL 5 may be located on the data line DL, the driving voltage line PL, the initialization connection line 1173 , the node connection line 1174 , and the first connection metal 1175 . The first planarization insulating layer IL 5 may include an organic insulating material including a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), polymer derivatives having a phenol-based group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, and a blend thereof.

As shown in FIGS. 6 B and 7 B , a second connection metal 1176 may be further arranged on the first planarization insulating layer IL 5 . The second connection metal 1176 may be arranged on the first planarization insulating layer IL 5 , and the second connection metal 1176 may be covered by a second planarization insulating layer IL 6 . The second planarization insulating layer IL 6 may include a suitable organic insulating material such as an acryl, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). The second connection metal 1176 may include a single layer or a multi-layer including at least one of Al, Cu, Ti, etc. The second connection metal 1176 , the driving voltage line PL, and the data line DL may include a multi-layered structure of Ti/Al/Ti.

The first connection metal 1175 may be connected to the drain region of the emission control thin film transistor T 6 through a contact hole 1153 . The first connection metal 1175 may be the drain electrode D 6 of the emission control thin film transistor T 6 . The second connection metal 1176 may be connected to the first connection metal 1175 through a contact hole formed in the first planarization insulating layer IL 5 , and the pixel electrode 210 may be electrically connected to the second connection metal 1176 through a contact hole CH defined in the second planarization insulating layer IL 6 . As shown in FIGS. 6 A and 7 A , in the case where the second connection metal 1176 and the second planarization insulating layer IL 6 are omitted, the pixel electrode 210 may be electrically connected to the first connection metal 1175 through a contact hole CH defined in the first planarization insulating layer IL 5 .

The pixel electrode 210 may include a reflective layer including, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), or a compound thereof. According to some example embodiments, the pixel electrode 210 may further include a layer including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) on/under the reflective layer.

A pixel-defining layer PDL may be arranged on the pixel electrode 210 , the pixel-defining layer PDL covering edges of the pixel electrode 210 . The pixel-defining layer PDL may include an opening exposing a portion of the pixel electrode 210 . An intermediate layer 220 may overlap the opening.

The intermediate layer 220 includes an emission layer 222 on the portion of the pixel electrode 210 that is exposed through the opening of the pixel-defining layer PDL. The emission layer 222 may include a polymer organic material or a low molecular weight organic material emitting light of a color (e.g., a set or predetermined color). According to some example embodiments, as shown in FIG. 7 A , the intermediate layer 220 may include a first functional layer 221 under the emission layer 222 and/or a second functional layer 223 on the emission layer 222 .

The first functional layer 221 may include a single layer or a multi-layer. For example, in the case where the first functional layer 221 includes a polymer material, the first functional layer 221 may be a hole transport layer (HTL), which has a single-layered structure. The first functional layer 221 may include poly-(3, 4)-ethylene-dihydroxy thiophene (PEDOT) or polyaniline (PANI). In the case where the first functional layer 221 includes a low molecular weight material, the first functional layer 221 may include a hole injection layer (HIL) and a hole transport layer (HTL).

The second functional layer 223 may be omitted. For example, in the case where the first functional layer 221 and the emission layer 222 include a polymer material, the second functional layer 223 may be formed to make a characteristic of the organic light-emitting diode OLED excellent. The second functional layer 223 may include a single layer or a multi-layer. The second functional layer 223 may include an electron transport layer (ETL) and/or an electron injection layer (EIL).

An opposite electrode 230 faces the pixel electrode 210 with the intermediate layer 220 therebetween. The opposite electrode 230 may include a conductive material having a low work function. For example, the opposite electrode 230 may include a (semi) transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the opposite electrode 230 may further include a layer including ITO, IZO, ZnO, or In 2 O 3 on/under the (semi) transparent layer including the above material.

According to some example embodiments, the display layer 200 arranged on the substrate 100 may be covered by the encapsulation member described above with reference to FIGS. 3 A to 3 C .

FIGS. 8 A and 8 B are plan views of wiring lines around the component area OA according to embodiments. FIGS. 9 A and 9 B are cross-sectional views of the wiring lines taken along the line IX-IX′ of FIGS. 8 A and 8 B . FIGS. 8 A and 8 B show, for convenience of description, eight data lines DL 0 , DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , DL 6 , and DL 7 , eight driving voltage lines PL 0 , PL 1 , PL 2 , PL 3 , PL 4 , PL 5 , PL 6 , and PL 7 , eight scan lines SL 0 , SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , SL 6 , and SL 7 , eight emission control lines EL 0 , EL 1 , EL 2 , EL 3 , EL 4 , EL 5 , EL 6 , and EL 7 , and eight initialization voltage lines VL 0 , VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , VL 6 , and VL 7 around the component area OA.

Referring to FIG. 8 A , the data lines DL 0 , DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , DL 6 , and DL 7 and the driving voltage lines PL 0 , PL 1 , PL 2 , PL 3 , PL 4 , PL 5 , PL 6 , and PL 7 may extend in the y-direction.

Some driving voltage lines PL 0 and PL 7 among the driving voltage lines PL 0 , PL 1 , PL 2 , PL 3 , PL 4 , PL 5 , PL 6 , and PL 7 may continuously extend so as to pass across the display area DA, but other driving voltage lines PL 1 , PL 2 , PL 3 , PL 4 , PL 5 , and PL 6 around the component area OA may be disconnected or separated around the component area OA. Driving voltage lines, which are located above the component area OA, of the driving voltage lines PL 1 , PL 2 , PL 3 , PL 4 , PL 5 , and PL 6 that are disconnected may be connected to the second sub-line 163 described above with reference to FIGS. 4 A and 4 B , and driving voltage lines, which are located below the component area OA, of the driving voltage lines PL 1 , PL 2 , PL 3 , PL 4 , PL 5 , and PL 6 that are disconnected may be connected to the first sub-line 162 .

Some data lines DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , and DL 6 among the data lines DL 0 , DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , DL 6 , and DL 7 may detour an edge of the component area OA around the component area OA. For example, each of the first to sixth data lines DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , and DL 6 connecting pixels P arranged below and above the component area OA in FIG. 8 A may include a portion extending in the y-direction in the display area DA, and a portion detouring the edge of the component area OA in the first non-display area NDA 1 .

Though it is shown in FIG. 8 A that a detouring portion of each of the data lines DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , and DL 6 is a curve of an arc, the detouring portion may have a stepwise configuration.

In FIG. 8 A , pixels P located above and below the component area OA may be electrically connected to one of the data lines DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , and DL 6 that detour the component area OA and may receive a data signal from the data lines DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , and DL 6 . For example, the first to third data lines DL 1 , DL 2 , and DL 3 among the data lines DL 1 , DL 2 , DL 3 , DL 4 , DL 5 , and DL 6 may be bent along a left edge of the component area OA, and the fourth to sixth data lines DL 4 , DL 5 , and DL 6 may be bent along a right edge of the component area OA. Though it is shown in FIG. 8 A , for convenience of description, that three detouring data lines DL 1 , DL 2 , and DL 3 (DL 4 , DL 5 , and DL 6 ) are arranged on the left and the right around the component area OA, the number of data lines detouring the component area OA may be three or more.

The scan lines SL 0 , SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , SL 6 , and SL 7 and the emission control lines EL 0 , EL 1 , EL 2 , EL 3 , EL 4 , EL 5 , EL 6 , and EL 7 may extend in the x-direction intersecting the y-direction. Some of the scan lines SL 0 , SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , SL 6 , and SL 7 , and the emission control lines EL 0 , EL 1 , EL 2 , EL 3 , EL 4 , EL 5 , EL 6 , and EL 7 , for example, the first to sixth scan lines SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , and SL 6 and the first to sixth emission control lines EL 1 , EL 2 , EL 3 , EL 4 , EL 5 , and EL 6 may be disconnected around the component area OA. As described above with reference to FIGS. 4 A and 4 B , because the first scan driving circuit 110 and the second scan driving circuit 120 are arranged on two opposite sides of the display area DA, some of the disconnected scan lines SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , and SL 6 and the disconnected emission control lines EL 1 , EL 2 , EL 3 , EL 4 , EL 5 , and EL 6 arranged on the left of the component area OA in the plan view of FIG. 8 A may be connected to the first scan driving circuit 110 . In the plan view of FIG. 8 A , some of the disconnected scan lines SL 1 , SL 2 , SL 3 , SL 4 , SL 5 , and SL 6 and the disconnected emission control lines EL 1 , EL 2 , EL 3 , EL 4 , EL 5 , and EL 6 arranged on the right of the component area OA may be connected to the second scan driving circuit 120 .

The initialization voltage lines VL 0 , VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , VL 6 , and VL 7 may extend in the x-direction. Some initialization voltage lines VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , and VL 6 around the component area OA may be disconnected around the component area OA. In the plan view of FIG. 8 A , a first initialization voltage line VL-A located on the left of the component area OA may be apart from a second initialization voltage line VL-B located on the right of the component area OA with the component area OA therebetween.

The first initialization voltage line VL-A and the second initialization voltage line VL-B that are apart from each other may be respectively connected to the first initialization power supply line 181 and the second initialization power supply line 182 described above with reference to FIGS. 4 A and 4 B . For example, in the case where the first initialization voltage line VL-A and the second initialization voltage line VL-B are apart from each other around the component area OA, a difference between an initialization voltage applied to pixels P arranged around the component area OA and an initialization voltage applied to other pixels P may occur. In this case, quality of an image displayed by the pixels P may be deteriorated.

In contrast, according to some example embodiments, because the first initialization voltage line VL-A and the second initialization voltage line VL-B are connected to an auxiliary voltage line VL-R, the above issue may be prevented or minimized.

The auxiliary voltage line VL-R may have a ring shape extending along a circumferential direction of the component area OA. According to some example embodiments, as shown in FIG. 8 A , the auxiliary voltage line VL-R may have a linear structure neighboring a boundary between the third area and the second area and arranged in the second area. According to some example embodiments, as shown in FIG. 8 B , the auxiliary voltage line VL-R may have a plate-type structure covering approximately the entire third area of the substrate 100 . The auxiliary voltage line VL-R may be arranged on a layer different from a layer on which the initialization voltage lines VL 0 , VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , VL 6 , and VL 7 are arranged and may electrically connect the initialization voltage lines that are apart from each other around the component area OA through first and second contact holes CNT 1 and CNT 2 .

For example, the first initialization voltage line VL-A may be connected to the auxiliary voltage line VL-R through the first contact hole CNT 1 , and the second initialization voltage line VL-B may be connected to the auxiliary voltage line VL-R through the second contact hole CNT 2 . As described with reference to FIG. 6 A , the initialization voltage lines VL 0 , VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , VL 6 , and VL 7 are arranged on the first interlayer insulating layer IL 3 . It is shown in FIGS. 9 A and 9 B that the first initialization voltage line VL-A and the second initialization voltage line VL-B that are apart from each other around the component area OA are arranged on the first interlayer insulating layer IL 3 .

The auxiliary voltage line VL-R may be arranged over the first initialization voltage line VL-A and the second initialization voltage line VL-B with one or more insulating layers therebetween. For example, as shown in FIG. 9 A , the auxiliary voltage line VL-R may be arranged on the second interlayer insulating layer IL 4 and may be covered by the first planarization insulating layer IL 5 and the second planarization insulating layer IL 6 arranged below the pixel electrode 210 (see FIG. 7 B ). A portion of the auxiliary voltage line VL-R may be connected to the first initialization voltage line VL-A through a first contact hole CNT 1 of the second interlayer insulating layer IL 4 . Similarly, another portion of the auxiliary voltage line VL-R may be connected to the second initialization voltage line VL-B through a second contact hole CNT 2 of the second interlayer insulating layer IL 4 .

According to some example embodiments, as shown in FIG. 9 B , the auxiliary voltage line VL-R may be arranged on the first planarization insulating layer IL 5 and covered by the second planarization insulating layer IL 6 arranged below the pixel electrode 210 (see FIG. 7 B ). A portion of the auxiliary voltage line VL-R may be connected to a mediation metal layer 1177 through a contact hole of the first planarization insulating layer IL 5 , and the mediation metal layer 1177 may be connected to the first initialization voltage line VL-A through a first contact hole CNT 1 of the second interlayer insulating layer IL 4 . Similarly, another portion of the auxiliary voltage line VL-R may be connected to the mediation metal layer 1177 through a contact hole of the first planarization insulating layer IL 5 , and the mediation metal layer 1177 may be connected to the second initialization voltage line VL-B through a second contact hole CNT 2 of the second interlayer insulating layer IL 4 .

Because the initialization voltage lines VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , and VL 6 that are disconnected are connected as one body by the auxiliary voltage line VL-R, initialization voltage lines and the auxiliary voltage line VL-R each may have the same voltage level. Therefore, the occurrence of a voltage deviation originated from disconnection of the initialization voltage line may be minimized.

FIG. 10 is a plan view of a display panel according to some example embodiments.

The display panel may include a plurality of component areas OA 1 and OA 2 . According to some example embodiments, it is shown in FIG. 10 that the display panel includes two component areas OA 1 and OA 2 .

The pixels P may be apart from each other around the plurality of component areas OA 1 and OA 2 . Pixels P may not be arranged in a region between the plurality of component areas OA 1 and OA 2 . For example, as shown in FIG. 10 , the first non-display area NDA 1 may surround the plurality of component areas OA 1 and OA 2 . Because description of other elements of the display panel shown in FIG. 10 are the same as that made with reference to FIGS. 4 A and 4 B , description thereof is omitted.

FIG. 11 is a plan view of wiring lines around a plurality of component areas according to some example embodiments.

Referring to FIG. 11 , each of the initialization voltage lines VL 1 , VL 2 , VL 3 , VL 4 , VL 5 , and VL 6 may include a portion disconnected around the plurality of component areas OA 1 and OA 2 . According to some example embodiments, FIG. 11 shows the first initialization voltage line VL-A on the left of the first component area OA 1 , the second initialization voltage line VL-B on the right of the second component area OA 2 , and a third initialization voltage line VL-C between the first component area OA 1 and the second component area OA 2 . The first initialization voltage line VL-A, the second initialization voltage line VL-B, and the third initialization voltage line VL-C may be apart from one another.

The first initialization voltage line VL-A may be connected to the third initialization voltage line VL-C through a first auxiliary voltage line VL-R 1 . The third initialization voltage line VL-C may be connected to the second initialization voltage line VL-B through a second auxiliary voltage line VL-R 2 .

Each of the first auxiliary voltage line VL-R 1 and the second auxiliary voltage line VL-R 2 may be arranged on a layer different from layers on which the first initialization voltage line VL-A, the second initialization voltage line VL-B, and the third initialization voltage line VL-C are arranged. For example, the first auxiliary voltage line VL-R 1 may be connected to the first initialization voltage line VL-A through the first contact hole CNT 1 and connected to the third initialization voltage line VL-C through the second contact hole CNT 2 . Likewise, the second auxiliary voltage line VL-R 2 may be connected to the third initialization voltage line VL-C through a first contact hole CNT 1 ′ and connected to the second initialization voltage line VL-B through a second contact hole CNT 2 ′.

Cross-sections corresponding to the connection between the first auxiliary voltage line VL-R 1 and the first initialization voltage line VL-A and the connection between the first auxiliary voltage line VL-R 1 and the third initialization voltage line VL-C may have the same structure as that described above with reference to FIGS. 9 A and 9 B . Likewise, cross-sections corresponding to the connection between the second auxiliary voltage line VL-R 2 and the third initialization voltage line VL-C and the connection between the second auxiliary voltage line VL-R 2 and the second initialization voltage line VL-B may have the same structure as that described above with reference to FIGS. 9 A and 9 B .

FIG. 12 is a plan view of wiring lines around the second non-display area NDA 2 according to some example embodiments and may correspond to a region XII of FIG. 10 , and FIGS. 13 A and 13 B are cross-sectional views of a display device according to embodiments and may correspond to cross-sections taken along the line XIII-XIII′ of FIG. 12 .

Referring to FIG. 12 , the first initialization power supply line 181 may be connected to the plurality of initialization voltage lines VL 1 , VL 2 , VL 3 , and VL 4 passing across the display area DA. The first initialization power supply line 181 may include a portion extending in the y-direction and a portion extending in a direction that is oblique with respect to the y-direction. FIG. 12 mainly shows a portion of the first initialization power supply line 181 extending in the oblique direction.

As shown in FIG. 10 , a corner of the display area DA may have a rounded structure. When the corner is enlarged, pixels P may be arranged in a stepwise configuration as shown in FIG. 12 . To provide the initialization voltage to the pixels P arranged in the stepwise configuration while efficiently utilizing the space of the second non-display area NDA 2 , a portion of the first initialization power supply line 181 may extend in the oblique direction, for example, a direction between the x-direction and the y-direction as shown in FIG. 12 .

The first initialization power supply line 181 may include a plurality of connection lines VL-L extending from one side of the first initialization power supply line 181 . Each connection line VL-L may be electrically connected to a corresponding initialization voltage line among the plurality of initialization voltage lines VL 1 , VL 2 , VL 3 , and VL 4 .

The first initialization power supply line 181 may be arranged on a layer different from layers on which the initialization voltage lines VL 1 , VL 2 , VL 3 , and VL 4 are arranged and may be electrically connected to the initialization voltage lines VL 1 , VL 2 , VL 3 , and VL 4 through a third contact hole CNT 3 .

According to some example embodiments, as shown in FIG. 13 A , the first initialization power supply line 181 may be arranged on the second interlayer insulating layer IL 4 . The initialization voltage lines may be arranged on the first interlayer insulating layer IL 3 . It is shown in FIG. 13 A that the second initialization voltage line VL 2 among the plurality of initialization voltage lines VL 1 , VL 2 , VL 3 , and VL 4 is arranged on the first interlayer insulating layer IL 3 . The connection line VL-L extending from the first initialization power supply line 181 may be connected to the second initialization voltage line VL 2 through a contact hole formed in the second interlayer insulating layer IL 4 , the contact hole formed in the second interlayer insulating layer IL 4 corresponding to the third contact hole CNT 3 described with reference to FIG. 12 .

The first initialization power supply line 181 arranged on the second interlayer insulating layer IL 4 may include the same material as that of the data line and/or the driving voltage line described above with reference to FIGS. 6 A and 7 A . Also, the first initialization power supply line 181 may include the same material as those of the node connection line 1174 and the first connection metal 1175 .

According to some example embodiments, as shown in FIG. 13 B , the first initialization power supply line 181 may be arranged on the first planarization insulating layer IL 5 . The connection line VL-L extending from the first initialization power supply line 181 may be connected to a metal layer ML through a contact hole formed in the first planarization insulating layer IL 5 , and the metal layer ML may be connected to the initialization voltage line, for example, the second initialization voltage line VL 2 through a contact hole formed in the second interlayer insulating layer IL 4 . The contact hole formed in the first planarization insulating layer IL 5 and the contact hole formed in the second interlayer insulating layer IL 4 may correspond to the third contact hole CNT 3 described with reference to FIG. 12 .

The first initialization power supply line 181 arranged on the first planarization insulating layer IL 5 may include the same material as that of the second connection metal 1176 described above with reference to FIGS. 6 B and 7 B .

For example, though FIGS. 12 to 13 B mainly describe the first initialization power supply line 181 , the structure described with reference to FIGS. 12 to 13 B is equally applicable to the second initialization power supply line 182 (see FIG. 10 ), and equally applicable to the first and second initialization power supply lines described with reference to FIGS. 4 A and 4 B .

According to some example embodiments, as described above, a display panel having an improved reliability and a reduced non-display area, and a display device including the display panel may be provided.

The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present invention described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present invention.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.