High-speed Buffer Amplifier

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to an amplifier, and more particularly to a high-speed buffer amplifier.

2. Description of Related Art

A liquid-crystal display (LCD) is a type of flat-panel display that presents visual information by modulating liquid crystals (LC) in an LC panel. The LC panel of the LCD is commonly driven by drivers such as a gate driver (or scan driver) and a source driver (or data driver), which are coordinated by a timing controller.

A rail-to-rail class-AB amplifier is usually adapted to the drivers of the LCD as disclosed in “A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEE Journal of Solid-State Circuits, Volume 29, Issue 12, December 1994, the entire contents of which are hereby incorporated by reference. Low settling time is one of key parameters for guaranteeing the performance of the drivers of the LCD, particularly a large-size or high-resolution LCD. The settling time is defined as the time elapsed from the application of an ideal instantaneous step input to the time at which the amplifier output has entered and remained within a specified error band.

A need has arisen to propose a novel scheme capable of improving settling time of a buffer amplifier adaptable to the LCD.

SUMMARY OF THE INVENTION

In view of the foregoing, it is an object of the embodiment of the present invention to provide a high-speed buffer amplifier with improved settling time.

According to one embodiment, a high-speed buffer amplifier includes an input stage, a middle stage and an output stage. The input stage includes a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs. The middle stage includes a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source. The output stage is coupled to the middle stage to generate an output voltage. The middle stage includes a shunt circuit electrically connected between the first current source and the second current source, and configured to bypass the floating current source.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram illustrating a high-speed buffer amplifier according to one embodiment of the present invention; and

FIG. 2 shows a circuit diagram illustrating the high-speed buffer amplifier of FIG. 1 according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a block diagram illustrating a high-speed buffer amplifier 100 according to one embodiment of the present invention, and FIG. 2 shows a circuit diagram illustrating the high-speed buffer amplifier 100 of FIG. 1 according to the embodiment of the present invention.

In the embodiment, the high-speed buffer amplifier (“amplifier” hereinafter) 100 may include an input stage 11 , a middle stage 12 and an output stage 13 .

The input stage 11 of the embodiment may include a first channel 111 coupled to receive differential inputs Vip and Vin, and composed of first-type transistors (e.g., P-type metal-oxide-semiconductor (PMOS) transistors) M 1 -M 4 . Specifically, the transistors M 1 -M 2 are connected in series (with the transistor M 1 coupled to power VDD) to form a first bias branch with bias voltages Vb 3 -Vb 4 , and the transistors M 3 -M 4 are connected in parallel with sources connected together to form a first source-coupled differential pair, which is connected to (the transistor M 2 of) the first bias branch.

The input stage 11 of the embodiment may include a second channel 112 coupled to receive the differential inputs Vip and Vin, and composed of second-type transistors (e.g., N-type MOS transistors or NMOS transistors) M 5 -M 8 . Specifically, the transistors M 5 -M 6 are connected in series (with the transistor M 5 coupled to ground) to form a second bias branch with bias voltages Vb 5 -Vb 6 , and the transistors M 7 -M 8 are connected in parallel with sources connected together to form a second source-coupled differential pair, which is connected to (the transistor M 6 of) the second bias branch.

The middle stage 12 of the embodiment may include a first current source 121 coupled to receive outputs of the second channel 112 , and electrically connected to the power VDD. The first current source 121 may include first-type transistors M 9 -M 12 . Specifically, the transistors M 9 and M 11 are connected in series (with the transistor M 9 coupled to the power VDD), at a first intermediate node n 9 , to form a first current branch, and the transistors M 10 and M 12 are connected in series (with the transistor M 10 coupled to the power VDD), at a second intermediate node n 10 , to form a second current branch. Gates of corresponding transistors of the first and the second current branches are coupled together. For example, gates of the transistors M 9 -M 10 adjacent to the power VDD are coupled at a first coupling node n 11 , which is further connected to a drain of the transistor M 11 . It is noted that the first intermediate node n 9 and the second intermediate node n 10 are connected to drains of the second source-coupled differential pair M 7 -M 8 , respectively. The gates of the transistors M 11 -M 12 are coupled to a first bias voltage Vb 1 .

The middle stage 12 of the embodiment may include a second current source 122 coupled to receive outputs of the first channel 111 , and electrically connected to the ground. The second current source 122 may include second-type transistors M 17 -M 20 . Specifically, the transistors M 17 and M 19 are connected in series (with the transistor M 19 coupled to the ground), at a third intermediate node n 5 , to form a third current branch, and the transistors M 18 and M 20 are connected in series (with the transistor M 20 coupled to the ground), at a fourth intermediate node n 6 , to form a fourth current branch. Gates of corresponding transistors of the third and the fourth current branches are coupled together. For example, gates of the transistors M 19 -M 20 adjacent to ground are coupled at a second coupling node n 7 , which is further connected to a drain of the transistor M 17 . It is noted that the third intermediate node n 5 and the fourth intermediate node n 6 are connected to drains of the first source-coupled differential pair M 3 -M 4 , respectively. The gates of the transistors M 17 -M 18 are coupled to a second bias voltage Vb 2 .

The middle stage 12 of the embodiment may include a floating current source 123 (composed of first-type transistors M 15 -M 16 and second-type transistors M 13 -M 14 ) electrically connected between the first current source 121 and the second current source 122 . Specifically, the transistors M 13 and M 15 are connected in parallel to form a first floating branch, which is connected between the first current branch M 9 /M 11 (at a first connected node n 13 ) of the first current source 121 and the third current branch M 17 /M 19 (at a second connected node n 14 ) of the second current source 122 . The transistors M 14 and M 16 are connected in parallel to form a second floating branch, which is connected between the second current branch M 10 /M 12 (at a third connect node n 12 ) of the first current source 121 and the fourth current branch M 18 /M 20 (at a fourth connect node n 8 ) of the second current source 122 . The gates of the transistors M 13 -M 16 are respectively coupled to corresponding bias voltages Vb 7 -Vb 10 . As usual, the gates of the transistors M 13 -M 14 /M 15 -M 16 with the same type are coupled to the same bias voltage.

It is noted that the third connect node n 12 and the fourth connect node n 8 are used as a first output node and a second output node of the middle stage 12 , respectively.

According to one aspect of the embodiment, the middle stage 12 may include a shunt circuit 124 electrically connected between the first current source 121 and the second current source 122 , and configured to bypass the floating current source 123 . The shunt circuit 124 may include a (first-type) first shunt transistor M 12 x and a (second-type) second shunt transistor M 18 x . Specifically, a source and a drain of the first shunt transistor M 12 x are connected to the second intermediate node n 10 and the fourth connect node n 8 respectively, and the gate connected to the first bias voltage Vb 1 ; and a source and a drain of the second shunt transistor M 18 x are connected to the fourth intermediate node n 6 and the third connect node n 12 respectively, and the gate connected to the second bias voltage Vb 2 . Furthermore, the shunt circuit 124 may include a (first-type) third shunt transistor M 11 x and a (second-type) fourth shunt transistor M 17 x . Specifically, a source and a drain of the third shunt transistor M 11 x are connected to the first intermediate node n 9 and the second connect node n 14 respectively, and the gate connected to the first bias voltage Vb 1 ; and a source and a drain of the fourth shunt transistor M 17 x are connected to the third intermediate node n 5 and the first connect node n 13 respectively, and the gate connected to the second bias voltage Vb 2 .

Alternatively speaking, the first shunt transistor M 12 x is connected with the transistor M 12 in parallel but bypassing the second floating branch M 14 /M 16 ; and the second shunt transistor M 18 x is connected with the transistor M 18 in parallel but bypassing the second floating branch M 14 /M 16 . Furthermore, the third shunt transistor M 11 x is connected with the transistor M 11 in parallel but bypassing the first floating branch M 13 /M 15 ; and the fourth shunt transistor M 17 x is connected with the transistor M 17 in parallel but bypassing the first floating branch M 13 /M 15 .

As the drain of the first shunt transistor M 12 x is connected to the fourth connect node n 8 , instead of connecting to the third connect node n 12 as for the transistor M 12 , signals may pass around the transistors M 12 and M 16 to promptly affect the fourth connect node n 8 (i.e., the second output node of the middle stage 12 ), thereby accelerating response of the amplifier 100 . Similarly, as the drain of the second shunt transistor M 18 x is connected to the third connect node n 12 , instead of connecting to the fourth connect node n 8 as for the transistor M 18 , signals may pass around the transistors M 18 and M 14 to promptly affect the third connect node n 12 (i.e., the first output node of the middle stage 12 ), thereby accelerating response of the amplifier 100 .

The output stage 13 of the embodiment is coupled to the first output node and the second output node of the middle stage 12 , and configured to generate an output voltage at the output node Vout (of the output stage 13 ). The output stage 13 may include a first output branch composed of a (first-type) first output transistor MpL 1 and a (second-type) second output transistor MnL 1 connected in series between the power VDD and the ground. Gates of the first output transistor MpL 1 and the second output transistor MnL 1 are coupled to the first output node and the second output node of the middle stage 12 , respectively.

The output stage 13 of the embodiment may include a second output branch composed of a (first-type) third output transistor MpL 2 and a (second-type) fourth output transistor MnL 2 connected in series (at the output node Vout of the output stage 13 ) between the power VDD and the ground. Gates of the third output transistor MpL 2 and the fourth output transistor MnL 2 are coupled to the first output node and the second output node of the middle stage 12 , respectively.

In operation, when a differential input voltage between Vip and Vin increases, the voltage at the second intermediate node n 10 accordingly decreases. Consequently, the voltage at the third connect node n 12 decreases, and the output voltage at the fourth connect node n 8 then decreases. As a result, the voltage at the output node Vout thus increases. It is noted that, owing to the first shunt transistor M 12 x , some signals may reach the fourth connect node n 8 and then promptly affect the output node Vout by passing around the transistors M 12 and M 16 .

On the other hand, when a differential input voltage between Vip and Vin decreases, the voltage at the fourth intermediate node n 6 accordingly decreases. Consequently, the voltage at the fourth connect node n 8 decreases, and the voltage at the third connect node n 12 then decreases. As a result, the output voltage at the output node Vout thus decreases. It is noted that, owing to the second shunt transistor M 18 x , some signals may reach the third connect node n 12 and then promptly affect the output node Vout by passing around the transistors M 18 and M 14 .

Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.