Semiconductor Device and Method for Fabricating the Same

This application is based on and claims priority under 35 U.S.C. § 119 from Korean Patent Application No. 10-2019-0086088 filed on Jul. 17, 2019 in the Korean Intellectual Property Office, the contents of which in its entirety are herein incorporated by reference.

BACKGROUND OF THE DISCLOSURE

1. Field

The disclosure relates to a semiconductor device and a method for fabricating the same. More particularly, the disclosure relates to a semiconductor device having a gate cut implemented therein, and a method for fabricating the same.

2. Description of the Related Art

Recently, in order to enhance integrated circuit device density, a multi-gate transistor has been suggested as one of the scaling technologies, in which a silicon body in a fin-like shape or a nanowire-like shape is formed on a substrate, with gates then being formed on the surface of the silicon body.

Such a multi-gate transistor allows easy scaling, as it uses a three-dimensional channel. Also, current control capability can be enhanced without requiring increased gate length of the multi-gate transistor. Moreover, it is possible to effectively inhibit the short channel effect (SCE), where the electric potential of a channel region is affected by a drain voltage.

SUMMARY

The disclosure provides a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented, and method for manufacturing the same.

According to an aspect of the disclosure, there is provided a semiconductor device comprising: a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode provided on the first to fourth active patterns and extending in the second direction; a first cut region that extends in the first direction between the first active pattern and the second active pattern to cut the first gate electrode; and a second cut region that extends in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

According to another aspect of the disclosure, there is provided a semiconductor device comprising: a first active pattern, a second active pattern, and a third active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode provided on the first to third active patterns and extending in the second direction; a second gate electrode extended in the second direction adjacent to the first gate electrode on the first to third active patterns; a first cut region that extends in the first direction between the first active pattern and the second active pattern to cut the first gate electrode; and a second cut region that extends in the first direction between the second active pattern and the third active pattern to cut the second gate electrode, and not to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

According to an aspect of the disclosure, there is provided a semiconductor device, comprising: a substrate comprising an NFET region and a PFET region; a first active pattern provided on the NFET region and extending in a first direction; a second active pattern provided on the PFET region and extending in the first direction; a first gate electrode provided on the first and second active patterns and extending in a second direction intersecting the first direction; a first cut region provided on a first side surface of the first active pattern opposite to the second active pattern and extending in the first direction to cut the first gate electrode; and a second cut region provided on a second side surface of the second active pattern opposite to the first active pattern and extending in the first direction to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

According to another aspect of the disclosure, there is provided a semiconductor device comprising: a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns, a second gate electrode extended in the second direction adjacent to the first gate electrode on the first to fourth active patterns, and a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode, and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, a third cut region extended in the first direction between the second active pattern and the third active pattern to cut the second gate electrode, and not to cut the first gate electrode, wherein a distance between the second active pattern and the third cut region is different from a distance between the third active pattern and the third cut region.

The technical objectives that are intended to be addressed by the disclosure are not limited to that mentioned above, and other technical objectives that are not mentioned above can be clearly understood to those skilled in the art based on the description provided below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout view provided to explain a semiconductor device according to an exemplary embodiment.

FIG. 2 is a cross-sectional view taken on line A-A of FIG. 1 .

FIG. 3 is a cross sectional view taken on line B-B of FIG. 1 .

FIG. 4 is a cross-sectional view taken on line C-C of FIG. 1 .

FIGS. 5 A and 5 B are graphs provided to explain changes in a threshold voltage and a drain current according to a position of a cut region.

FIG. 6 is a layout view provided to explain a semiconductor device according to another exemplary embodiment.

FIGS. 7 A and 7 B are graphs provided to explain changes in a threshold voltage and a drain current according to a position of a cut region.

FIGS. 8 and 9 are layout views provided to explain a semiconductor device according to another exemplary embodiment.

FIGS. 10 A to 10 C are views provided to explain a semiconductor device according to another exemplary embodiment.

FIGS. 11 A to 11 C are views provided to explain a semiconductor device according to another exemplary embodiment.

FIGS. 12 A to 12 B are views provided to explain a semiconductor device according to another exemplary embodiment.

FIG. 13 is a layout view provided to explain a semiconductor device according to some exemplary embodiments.

FIGS. 14 A and 14 B provided to explain changes in a threshold voltage and a drain current according to a length of a cut region.

FIGS. 15 and 16 are layout views provided to explain a semiconductor device according to some exemplary embodiments.

FIGS. 17 A to 17 B are views provided to explain a semiconductor device according to another exemplary embodiment.

FIGS. 18 A to 18 B are views provided to explain a semiconductor device according to another exemplary embodiment.

FIGS. 19 A to 19 B are views provided to explain a semiconductor device according to another exemplary embodiment.

DETAILED DESCRIPTION

Hereinbelow, semiconductor devices according to some exemplary embodiments of the disclosure will be described with reference to FIGS. 1 to 19 B .

Although the drawings may illustrate that a semiconductor device formed on a substrate is a fin-type transistor (FinFET) according to an exemplary embodiment, the disclosure is not limited hereto. For example, in the semiconductor device according to some exemplary embodiments, a semiconductor element formed on the substrate may include a buried channel array transistor (BCAT), a recess channel array transistor (RCAT), a tunneling transistor (tunneling FET), a transistor including a nanowire, a transistor including a nanosheet, or a vertical transistor (vertical FET).

FIG. 1 is a layout view provided to explain a semiconductor device according to an exemplary embodiment. FIG. 2 is a cross-sectional view taken on line A-A of FIG. 1 . FIG. 3 is a cross sectional view taken on line B-B of FIG. 1 . FIG. 4 is a cross-sectional view taken on line C-C of FIG. 1 . For convenience of explanation, a gate contact GC, which is illustrated in FIG. 1 , is not illustrated in FIGS. 2 to 4 .

Referring to FIGS. 1 to 4 , the semiconductor device according to an exemplary embodiment includes a substrate 100 , first to fourth active patterns F 1 -F 4 , a field insulating film 110 , first to sixth gate electrodes G 1 -G 6 , first to fourth cut regions CT 1 -CT 4 , a gate spacer 140 , gate dielectric films 124 , 244 , a source region 150 S and a drain region 150 D, and an interlayer insulating film 160 .

The substrate 100 may be, for example, a bulk silicon or a silicon-on-insulator (SOI). For example, the substrate 100 may be a silicon substrate, or may include other material such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 100 may be a base substrate having an epitaxial layer formed thereon. In the following description, it is assumed that the substrate 100 is a silicon substrate by way of an example.

The substrate 100 may include a first region I and a second region II. The first region I and the second region II may be regions spaced apart from each other, or regions adjacent to each other. Transistors of different conductive types may be formed on the first region I and the second region II, or transistors of the same conductive type may be formed thereon.

The first to fourth active patterns F 1 -F 4 may protrude from an upper surface of the substrate 100 and be extended longitudinally. For example, each of the first to fourth active patterns F 1 -F 4 may have a short side and a long side. It is illustrated in FIG. 1 that the long sides of the first to fourth active patterns F 1 -F 4 are extended in a first direction X. That is, each of the first to fourth active patterns F 1 -F 4 may be extended longitudinally in the first direction X.

The first to fourth active patterns F 1 -F 4 may be spaced apart from one another and may be extended in parallel. For example, the first to fourth active patterns F 1 -F 4 may be arranged in sequence along a second direction Y that intersects the first direction X. As shown in FIG. 1 , the first to fourth active patterns F 1 -F 4 may be spaced apart from one another by an equal distance, but the disclosure is not limited hereto.

In some exemplary embodiments, the first and second active patterns F 1 , F 2 may be arranged on the first region I of the substrate 100 , and the third and fourth active patterns F 3 , F 4 may be arranged on the second region II of the substrate 100 . For example, the first region I of the substrate 100 and the second region II of the substrate 100 may be arranged along the second direction Y.

In some exemplary embodiments, transistors of different conductive types may be formed on the first region I and the second region II. Hereinbelow, it will be explained herein that the first region I is an NFET region and the second region II is an PFET region. However, this is merely an example, and the first region I may be a PFET region and the second region II may be an NFET region. When the first region I is the NFET region, the first and second active patterns F 1 , F 2 may include a p-type impurity. When the second region II is the PFET region, the third and fourth active patterns F 3 , F 4 may include an n-type impurity.

The first to fourth active patterns F 1 -F 4 may be a part of the substrate 100 , and may include an epitaxial layer grown from the substrate 100 . The first to fourth active patterns F 1 -F 4 may include, for example, an elemental semiconductor material such as silicon or germanium. Further, the first to fourth active patterns F 1 -F 4 may include a compound semiconductor such as IV-IV group compound semiconductor or III-V group compound semiconductor, for example.

The field insulating film 110 may be formed on the substrate 100 . In some exemplary embodiments, the field insulating film 110 may surround a part of side surfaces of the first to fourth active patterns F 1 -F 4 . For example, as shown in FIGS. 3 and 4 , the first to fourth active patterns F 1 -F 4 may further protrude upwardly above the field insulating film 110 . For example, an upper surface of the first to fourth active patterns may be above an upper surface of the field insulating film.

The field insulating film 110 may include, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or a combination thereof, but the disclosure is not limited hereto.

The first to sixth gate electrodes G 1 -G 6 may be formed on the first to fourth active patterns F 1 -F 4 . The first to sixth gate electrodes G 1 -G 6 may be extended in a direction that intersects the first to fourth active patterns F 1 -F 4 . For example, each of the first to sixth gate electrodes G 1 -G 6 may be extended longitudinally in the second direction Y. In some exemplary embodiments, the first to sixth gate electrodes G 1 -G 6 may be extended across the first region I and the second region II.

The first to sixth gate electrodes G 1 -G 6 may be spaced apart from one another and may be extended in parallel. For example, the first to sixth gate electrodes G 1 -G 6 may be arranged in sequence along the first direction X. As shown in FIG. 1 , the first to sixth gate electrodes G 1 -G 6 may be spaced apart from one another by an equal distance, but the disclosure is not limited hereto.

In some exemplary embodiments, each of the first to sixth gate electrodes G 1 -G 6 may be formed with a plurality of conductive materials stacked on one another. For example, as shown in FIGS. 2 to 4 , each of the first to sixth gate electrodes G 1 -G 6 may include a work function adjustment film 132 to adjust a work function, and a filling conductive film 134 filling a space formed by the work function adjustment film 132 .

The work function adjustment film 132 may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC, and a combination thereof, but the present inventive concept is not limited hereto. The filling conductive film 134 may include, for example, W or Al, but the disclosure is not limited hereto.

For example, the first to sixth gate electrodes G 1 -G 6 may be formed by a replacement process, but the disclosure is not limited hereto.

The first to fourth cut regions CT 1 -CT 4 may cut the first to sixth gate electrodes G 1 -G 6 . That is, according to an exemplary embodiment, the first to fourth cut regions CT 1 -CT 4 may physically separate at least one of the first to sixth gate electrodes G 1 -G 6 . For example, as shown in FIG. 1 , the first to fourth cut regions CT 1 -CT 4 may be extended in the first direction X to cut at least part of the first to sixth gate electrodes G 1 -G 6 .

The first to fourth cut regions CT 1 -CT 4 may have insulting patterns formed therein. For example, the first to fourth cut regions CT 1 -CT 4 may include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), or a combination thereof, but the disclosure is not limited hereto. Accordingly, the first to fourth cut regions CT 1 -CT 4 may electrically disconnect or separate the first to sixth gate electrodes G 1 -G 6 .

Although FIG. 1 only illustrates insulating patterns integrally formed in the first to fourth cut regions CT 1 -CT 4 , the disclosure is not limited hereto. The insulating patterns may be discontinuously formed in the first to fourth cut regions CT 1 -CT 4 as long as they can cut the first to sixth gate electrodes G 1 -G 6 .

In some exemplary embodiments, the first to fourth cut regions CT 1 -CT 4 may be formed on the same level. Herein, the term, “same level,” refers to being formed by the same fabricating process. For example, the first to fourth cut regions CT 1 -CT 4 may include the same material.

The first cut region CT 1 may be formed on the first region I of the substrate 100 . The first cut region CT 1 may be formed on a side surface of the second active pattern F 2 opposite to the third active pattern F 3 . For example, the first cut region CT 1 may be interposed between the first active pattern F 1 and the second active pattern F 2 .

In some exemplary embodiments, the first cut region CT 1 may be extended in the first direction X to cut the first to sixth gate electrodes G 1 -G 6 . For example, the second gate electrode G 2 may include a first portion G 2 - 1 and a second portion G 2 - 2 which are electrically disconnected by the first cut region CT 1 . In addition, for example, the third gate electrode G 3 may include a first portion G 3 - 1 and a second portion G 3 - 2 which are electrically disconnected by the first cut region CT 1 .

In some exemplary embodiments, a distance D 11 between the first active pattern F 1 and the first cut region CT 1 may be the same as a distance D 12 between the second active pattern F 2 and the first cut region CT 1 . In the detailed description, the term “same” refers to not only being exactly the same but also includes a minute difference or variations that may be caused by a margin or the like in a process.

The second cut region CT 2 may be formed on the second region II of the substrate 100 . The second cut region CT 2 may be formed on a side surface of the third active pattern F 3 opposite to the second active pattern F 2 . For example, the second cut region CT 2 may be interposed between the third active pattern F 3 and the fourth active pattern F 4 .

In some exemplary embodiments, the second cut region CT 2 may be extended in the first direction X to cut the first to sixth gate electrodes G 1 -G 6 . For example, the second gate electrode G 2 may include a third portion G 2 - 3 and a fourth portion G 2 - 4 which are electrically disconnected by the second cut region CT 2 . In addition, for example, the third gate electrode G 3 may include the second portion G 3 - 2 and a third portion G 3 - 3 which are electrically disconnected by the second cut region CT 2 .

In some exemplary embodiments, a distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be the same as a distance D 22 between the fourth active pattern F 4 and the second cut region CT 2 . In addition, in some exemplary embodiments, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be the same as the distance D 12 between the second active pattern F 2 and the first cut region CT 1 .

In some exemplary embodiments, a width W 2 of the second cut region CT 2 may be the same as a width W 1 of the first cut region CT 1 . Herein, the term “width” refers to a width in the second direction Y. According to an exemplary embodiment, the width W 2 of the second cut region CT 2 and the width W 1 of the first cut region CT 1 are measured at the same corresponding position at the second cut region CT 2 and the first cut region CT 1 . For instance, according to an embodiment, the width W 2 may be a width measured at the lower most portion of the second cut region CT 2 and the width W 1 may be a width measured at the lower most portion of the first cut region CT 1 . According to another embodiment, the width W 2 may be a width measured at the upper most portion of the second cut region CT 2 and the width W 1 may be a width measured at the upper most portion of the first cut region CT 1 . According to yet another embodiment, the width W 2 may be a width measured at the center portion of the second cut region CT 2 and the width W 1 may be a width measured at the center portion of the first cut region CT 1 .

The third and fourth cut regions CT 3 , CT 4 may be formed on a side surface of the second active pattern F 2 facing the third active pattern F 3 . In addition, the third and fourth cut regions CT 3 , CT 4 may be formed on a side surface of the third active pattern F 3 facing the second active pattern F 2 . For example, the third and fourth cut regions CT 3 , CT 4 may be interposed between the second active pattern F 2 and the third active pattern F 3 .

In some exemplary embodiments, the third and fourth cut regions CT 3 , CT 4 may be extended in the first direction X to cut the first, second, fifth, and sixth gate electrodes G 1 , G 2 , G 5 , G 6 . For example, the third cut region CT 3 may be extended in the first direction X to cut the first and second gate electrodes G 1 , G 2 , and the fourth cut region CT 4 may be extended in the first direction X to cut the fifth and sixth gate electrodes G 5 , G 6 . For example, the second gate electrode G 2 may include the second portion G 2 - 2 and the third portion G 2 - 3 which are electrically disconnected by the third cut region CT 3 .

However, in some exemplary embodiments, the third and fourth cut regions CT 3 , CT 4 may not cut the third and fourth gate electrodes G 3 , G 4 . For example, the second portion G 3 - 2 of the third gate electrode G 3 may not be cut by the third cut region CT 3 . Accordingly, the second portion G 3 - 2 of the third gate electrode G 3 may be shared by the second and third active patterns F 2 , F 3 .

In some exemplary embodiments, the third and fourth gate electrodes G 3 , G 4 may be active gate electrodes. For example, the second portion G 3 - 2 of the third gate electrode G 3 may be connected with a gate contact GC applying a gate voltage. Accordingly, the second portion G 3 - 2 of the third gate electrode G 3 may function as a gate of a transistor including the second active pattern F 2 and a transistor including the third active pattern F 3 .

In some exemplary embodiments, the first, second, fifth, and sixth gate electrodes G 1 , G 2 , G 5 , G 6 may be dummy gate electrodes. For example, the second portion G 2 - 2 and the third portion G 2 - 3 of the second gate electrode G 2 may not be connected with the gate contact GC applying the gate voltage. Accordingly, the second portion G 2 - 2 of the second gate electrode G 2 may not function as the gate of the transistor including the second active pattern F 2 . Likewise, the third portion G 2 - 3 of the second gate electrode G 2 may not function as the gate of the transistor including the third active pattern F 3 .

In some exemplary embodiments, a distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be different from a distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 . For example, as shown in FIGS. 1 and 4 , the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be shorter than the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 . In this case, operation performance of the transistor including the second active pattern F 2 , which is the NFET region, can be enhanced. This will be described in detail in the explanation of FIGS. 5 A and 5 B .

In some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be different from the distance D 12 between the second active pattern F 2 and the first cut region CT 1 . For example, as shown in FIGS. 1 and 4 , the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be shorter than the distance D 12 between the second active pattern F 2 and the first cut region CT 1 .

In some exemplary embodiments, the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 may be different from the distance D 21 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 . For example, as shown in FIGS. 1 and 4 , the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 may be longer than the distance D 21 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

In some exemplary embodiments, a width W 3 of the third cut region CT 3 may be the same as the width W 1 of the first cut region CT 1 and the width W 2 of the second cut region CT 2 .

The gate spacer 140 may be formed on both side surfaces of each of the first to sixth gate electrodes G 1 -G 6 . For example, as shown in FIG. 2 , the gate spacer 140 may be extended along both side surfaces of the third gate electrode G 3 . In addition, the gate spacer 140 may be extended longitudinally in the second direction Y.

The gate spacer 140 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), or a combination thereof, but the disclosure is not limited hereto.

According to an exemplary embodiment, the gate dielectric film 124 , 224 may be interposed between each of the first to fourth active patterns F 1 -F 4 and each of the first to sixth gate electrodes G 1 -G 6 . For example, as shown in FIGS. 2 and 3 , the first gate dielectric film 124 may be interposed between the first to fourth active patterns F 1 -F 4 and the third gate electrode G 3 . Alternatively, for example, as shown in FIG. 4 , the second gate dielectric film 224 may be interposed between the first to fourth active patterns F 1 -F 4 and the second gate electrode G 2 .

In some exemplary embodiments, the gate dielectric film 124 , 224 may be further extended along a side surface of the gate spacer 140 . For example, as shown in FIG. 2 , a part of the gate dielectric film 124 , 224 may be interposed between the third gate electrode G 3 and the gate spacer 140 . Such a gate dielectric film 124 , 224 may be formed by a replacement process, for example, but the disclosure is not limited hereto.

In some exemplary embodiments, as shown in FIGS. 3 and 4 , the gate dielectric film 124 , 224 may be extended along a top surface of the field insulating film 110 and profiles of the first to fourth active patterns F 1 -F 4 exposed by the field insulating film 110 .

However, in some exemplary embodiments, the gate dielectric film 124 , 224 may not be extended alongside surfaces of the first to fourth cut regions CT 1 -CT 4 . This is attributable to forming the first to fourth cut regions CT 1 -CT 4 after the gate dielectric film 124 , 224 is formed. However, this is merely an example and the disclosure is not limited hereto.

The gate dielectric film 124 , 224 may include, for example, at least one of silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), or a high-k dielectric material having a higher dielectric constant than silicon oxide (SiO 2 ), but the disclosure is not limited hereto.

The semiconductor device according to some exemplary embodiments may further include an interface film 122 , 222 . The interface film 122 , 222 may be interposed between each of the first to fourth active patterns F 1 -F 4 and each of the gate dielectric film 124 , 224 . For example, as shown in FIGS. 2 and 3 , the first interface film 122 may be interposed between the first to fourth active patterns F 1 -F 4 and the third gate electrode G 3 . Alternatively, for example, as shown in FIG. 4 , the second interface film 222 may be interposed between the first to fourth active patterns F 1 -F 4 and the second gate electrode G 2 .

In some exemplary embodiments, as shown in FIGS. 3 and 4 , the interface film 122 , 222 may be extended along the profiles of the first to fourth active patterns F 1 -F 4 exposed by the field insulating film 110 .

The interface film 122 , 222 may include, for example, silicon oxide, but the disclosure is not limited hereto. In some exemplary embodiments, the interface film 122 , 222 may include oxide of the first to fourth active patterns F 1 -F 4 .

The source region 150 S and the drain region 150 D may be formed within each of the first to fourth active patterns F 1 -F 4 . In addition, the source region 150 S and the drain region 150 D may be disposed on both sides of each of the first to sixth gate electrodes G 1 -G 6 . The side of the gate electrode having the source region and the side of the gate electrode having the drain region is not limited to the illustration in FIG. 2 , and thus the sides may be vice versa. The source region 150 S and the drain region 150 D may be insulated from each of the first to sixth gate electrodes G 1 -G 6 by the gate spacer 140 .

In some exemplary embodiments, the source region 150 S and the drain region 150 D may be formed by an epitaxial growth method. For example, as shown in FIG. 2 , the source region 150 S and the drain region 150 D may be formed by the epitaxial growth method to fill a trench 150 t within the second active pattern F 2 .

In some exemplary embodiments, the source region 150 S and the drain region 150 D may be an elevated source/drain. For example, as shown in FIG. 2 , an uppermost portion of source region 150 S and the drain region 150 D may further protrude upwardly than a top surface of the second active pattern F 2 .

Although source region 150 S and the drain region 150 D is illustrated as a single film, the disclosure is not limited hereto. For example, the source region 150 S and the drain region 150 D may be formed as a multi-film including impurities of different concentrations.

When a transistor including the source region 150 S and the drain region 150 D is an NFET, the source region 150 S and the drain region 150 D may include an n-type impurity or an impurity to prevent spread of the n-type impurity. For example, the source region 150 S and the drain region 150 D may include at least one of P, Sb, As or a combination thereof.

In some exemplary embodiments, when the transistor including the source region 150 S and the drain region 150 D is the NFET, the source region 150 S and the drain region 150 D may include a tensile stress material. For example, when the second active pattern F 2 is silicon (Si), the source region 150 S and the drain region 150 D may include silicon carbide (SiC).

Alternatively, when the transistor including the source region 150 S and the drain region 150 D is a PFET, the source region 150 S and the drain region 150 D may include a p-type impurity or an impurity to prevent spread of the p-type impurity. For example, the source region 150 S and the drain region 150 D may include at least one of B, C, In, Ga and Al or a combination thereof.

In some exemplary embodiments, when the transistor including the source region 150 S and the drain region 150 D is the PFET, the source region 150 S and the drain region 150 D may include a compression stress material. For example, when the second active pattern F 2 is silicon (Si), the source region 150 S and the drain region 150 D may include silicon germanium (SiGe).

The interlayer insulating film 160 may be formed on the substrate 100 and the field insulating film 110 . In addition, the interlayer insulating film 160 may be formed to fill a surrounding space. For example, the interlayer insulating film 160 may cover a side surface of the gate spacer 140 and a top surface of the source region 150 S and the drain region 150 D.

The interlayer insulating film 160 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric material with a lower dielectric constant than silicon oxide, but the disclosure is not limited hereto.

FIGS. 5 A and 5 B are graphs provided to explain changes in a threshold voltage and a drain current according to a position of a cut region.

Specifically, FIG. 5 A is an exemplary graph provided to explain changes in a threshold voltage V T of an NFET and a PFET according to a distance between a cut region of an adjacent gate electrode and an active pattern. In addition, FIG. 5 B is an exemplary graph provided to explain changes in a drain current I D of the NFET and the PFET according to the distance between the cut region of the adjacent gate electrode and the active pattern.

For convenience of explanation, it is assumed that an exemplary semiconductor device of FIGS. 5 A and 5 B includes the second active pattern F 2 , the third active pattern F 3 , the second gate electrode G 2 , the third gate electrode G 3 , and the third cut region CT 3 of FIG. 1 . For reference, a point P of FIGS. 5 A and 5 B refers to a case in which the third cut region CT 3 is not included.

Referring to FIG. 5 A , in the case of the NFET, it can be seen that, as the distance between the cut region of the adjacent gate electrode and the active pattern decreases, a change ΔV T of the threshold voltage decreases. For example, as the distance D 31 between the third cut region CT 3 , which cuts the second gate electrode G 2 , and the second active pattern F 2 decreases, the threshold voltage V T of the transistor including the third gate electrode G 3 and the second active pattern F 2 may decrease.

However, in the case of the PFET, it can be seen that, as the distance between the cut region of the adjacent gate electrode and the active pattern decreases, the change ΔV T of the threshold voltage increases. For example, as the distance D 32 between the third cut region CT 3 , which cuts the second gate electrode G 2 , and the third active pattern F 3 decreases, the threshold voltage V T of the transistor including the third gate electrode G 3 and the third active pattern F 3 may increase.

Likewise, referring to FIG. 5 B , in the case of the NFET, it can be seen that, as the distance between the cut region of the adjacent gate electrode and the active pattern decreases, a change ΔI D of the drain current increases. For example, as the distance D 31 between the third cut region CT 3 , which cuts the second gate electrode G 2 , and the second active pattern F 2 decreases, the drain current I D of the transistor including the third gate electrode G 3 and the second active pattern F 2 may increase.

However, in the case of the PFET, it can be seen that, as the distance between the cut region of the adjacent gate electrode and the active pattern decreases, the change ΔI D of the drain current decreases. For example, as the distance D 32 between the third cut region CT 3 , which cuts the second gate electrode G 2 , and the third active pattern F 3 decreases, the drain current I D of the transistor including the third gate electrode G 3 and the third active pattern F 3 may decrease.

As described above, in some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third cut region CT 3 may be relatively short, and the distance D 32 between the third active pattern F 3 and the third cut region CT 3 may be relatively long. Accordingly, when the second active pattern F 2 is the NFET region, the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may increase. In addition, when the third active pattern F 3 is the PFET region, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device having enhanced operation performance may be provided.

FIG. 6 is a layout view provided to explain a semiconductor device according to according to another embodiment. For convenience of explanation, elements or operations overlapping with those already described above with reference to FIGS. 1 to 5 will not be described or described as briefly as possible for the sake of brevity.

Referring to FIG. 6 , in the semiconductor device according to some exemplary embodiments, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be different from the distance D 12 between the second active pattern F 2 and the first cut region CT 1 .

In addition, as shown in the drawing, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be shorter than the distance D 12 between the second active pattern F 2 and the first cut region CT 1 . In this case, operation performance of the transistor including the third active pattern F 3 , which is the PFET region, can be enhanced. This will be described in detail in the explanation of FIGS. 7 A and 7 B .

In some exemplary embodiments, the first, second, fifth, and sixth gate electrodes G 1 , G 2 , G 5 , G 6 between the first cut region CT 1 and the second cut region CT 2 may not be cut. For example, the semiconductor device of FIG. 6 may not include the third and fourth cut regions CT 3 , CT 4 of FIG. 1 . For example, the second gate electrode G 2 may include a second portion G 2 - 2 and a third portion G 2 - 3 which are electrically disconnected by the second cut region CT 2 .

In some exemplary embodiments, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be shorter than the distance D 22 between the fourth active pattern F 4 and the second cut region CT 2 . In addition, in some exemplary embodiments, the distance D 12 between the second active pattern F 2 and the first cut region CT 1 may be longer than the distance D 11 between the first active pattern F 1 and the first cut region CT 1 .

FIGS. 7 A and 7 B are graphs provided to explain changes in a threshold voltage and a drain current according to a position of a cut region.

Specifically, FIG. 7 A is an exemplary graph provided to explain changes in a threshold voltage V T of an NFET and the PFET according to a distance between a cut region of a gate electrode and an active pattern. In addition, FIG. 7 B is an exemplary graph provided to explain changes in a drain current I D of the NFET and the PFET according to the distance between the cut region of the gate electrode and the active pattern.

For convenience of explanation, it is assumed that an exemplary semiconductor device of FIGS. 7 A and 7 B include the second active pattern F 2 , the third active pattern F 3 , and the third gate electrode G 3 of FIG. 6 . For reference, a point P of FIGS. 7 A and 7 B refers to a case in which the first cut region CT 1 or the second cut region CT 2 is not included.

Referring to FIG. 7 A , in the case of the NFET, it can be seen that, as the distance between the cut region of the gate electrode and the active pattern decreases, a change ΔV T of the threshold voltage increases. For example, as the distance D 12 between the first cut region CT 1 , which cuts the third gate electrode G 3 , and the second active pattern F 2 decreases, the threshold voltage V T of the transistor including the third gate electrode G 3 and the second active pattern F 2 may increase.

However, in the case of the PFET, it can be seen that, as the distance between the cut region of the gate electrode and the active pattern decreases, the change ΔV T of the threshold voltage decreases. For example, as the distance D 21 between the second cut region CT 2 , which cuts the third gate electrode G 3 , and the third active pattern F 3 decreases, the threshold voltage V T of the transistor including the third gate electrode G 3 and the third active pattern F 3 may decrease.

Likewise, referring to FIG. 7 B , in the case of the NFET, it can be seen that, as the distance between the cut region of the gate electrode and the active pattern decreases, a change ΔI D of the drain current decreases. For example, as the distance D 12 between the first cut region CT 1 , which cuts the third gate electrode G 3 , and the second active pattern F 2 decreases, the drain current I D of the transistor including the third gate electrode G 3 and the second active pattern F 2 may decrease.

However, in the case of the PFET, it can be seen that, as the distance between the cut region of the gate electrode and the active pattern decreases, the change ΔI D of the drain current increases. For example, as the distance D 21 between the second cut region CT 2 , which cuts the third gate electrode G 3 , and the third active pattern F 3 decreases, the drain current I D of the transistor including the third gate electrode G 3 and the third active pattern F 3 may increase.

As described above, in some exemplary embodiments, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be relatively short, and the distance D 12 between the second active pattern F 2 and the first cut region CT 1 may be relatively long. Accordingly, when the third active pattern F 3 is the PFET region, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may increase. In addition, when the second active pattern F 2 is the NFET region, the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device having enhanced operation performance may be provided.

FIGS. 8 and 9 are layout views provided to explain a semiconductor device according to some exemplary embodiments. For convenience of explanation, elements or operations overlapping with those already described above with reference to FIGS. 1 to 7 will not be described or described as briefly as possible for the sake of brevity.

Referring to FIG. 8 , the semiconductor device according to another exemplary embodiment further includes the third and fourth cut regions CT 3 , CT 4 .

In this case, operation performance of the transistor including the second active pattern F 2 , which is the NFET region, can be enhanced. For example, as described in the explanation of FIG. 5 B , when the third cut region CT 3 is positioned, the drain current I D of the transistor including the third gate electrode G 3 and the second active pattern F 2 may increase. Accordingly, the semiconductor device having further enhanced operation performance of the NFET may be provided.

In some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be the same as the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

Referring to FIG. 9 , in the semiconductor device according to some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be different from the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

For example, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be shorter than the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

In this case, as described above in the explanation of FIG. 5 B , the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may increase. In addition, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device with further improved operation performance can be provided.

FIGS. 10 A to 10 C , FIGS. 11 A to 11 C , FIGS. 12 A to 12 B are views provided to explain a semiconductor device according to some exemplary embodiments. For reference, FIGS. 10 B and 10 C are cross-sectional views taken on D-D of FIG. 10 A . FIGS. 11 B and 11 C are cross-sectional views taken on E-E of FIG. 11 A , and FIG. 12 B is a cross-sectional view take on F-F of FIG. 12 A .

Referring to FIGS. 10 A and 10 B , in the semiconductor device according to some exemplary embodiments, the width W 2 of the second cut region CT 2 may be different from the width W 1 of the first cut region CT 1 .

For example, the width W 2 of the second cut region CT 2 may be larger than the width W 1 of the first cut region CT 1 . Herein, the term “width” refers to a width in the second direction Y.

As the width W 1 of the first cut region CT 1 is relatively smaller, the distance D 12 between the second active pattern F 2 and the first cut region CT 1 may relatively increase. In addition, as the width W 2 of the second cut region CT 2 is relatively larger, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may relatively decrease.

In this case, as described above in the explanation of FIG. 7 B , the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may increase. In addition, the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device having enhanced operation performance can be provided.

In some exemplary embodiments, the distance D 11 between the first active pattern F 1 and the first cut region CT 1 may be the same as the distance D 12 between the second active pattern F 2 and the first cut region CT 1 . In addition, in some exemplary embodiments, the distance D 21 between the third active pattern F 3 and the second cut region CT 2 may be the same as the distance D 22 between the fourth active pattern F 4 and the second cut region CT 2 .

In some exemplary embodiments, the first cut region CT 1 and the second cut region CT 2 may have the same depth. For example, as shown in FIG. 10 B , a height H 1 of the bottom surface of the first cut region CT 1 from the top surface of the substrate 100 may be the same as a height H 2 of the bottom surface of the second cut region CT 2 .

Referring to FIGS. 10 A and 10 C , in the semiconductor device according to some exemplary embodiments, the first cut region CT 1 and the second cut region CT 2 may have depths different from each other.

For example, as shown in FIG. 10 C , the height H 1 of the bottom surface of the first cut region CT 1 from the top surface of the substrate 100 may be different from the height H 2 of the bottom surface of the second cut region CT 2 . For example, the height H 1 of the bottom surface of the first cut region CT 1 may be lower than the height H 2 of the bottom surface of the second cut region CT 2 .

This is attributable to characteristics of an etching process for forming the first cut region CT 1 and the second cut region CT 2 . For example, in an etching process for forming the first cut region CT 1 and the second cut region CT 2 , a by-product such as polymer may be generated and may hinder inflow of an etchant, thereby reducing an etching speed. Many by-products may be generated as a width of a cut region where such products are generated is wider. Accordingly, in some exemplary embodiments, a depth of the second cut region CT 2 having a larger width than the first cut region CT 1 may be shallower than a depth of the first cut region CT 1 .

Referring to FIGS. 11 A and 11 B , the semiconductor device according to some exemplary embodiments further includes the third and fourth cut regions CT 3 , CT 4 .

In this case, operation performance of the transistor including the second active pattern F 2 , which is the NFET region, can be enhanced. For example, as described above in the explanation of FIG. 5 D , when the third cut region CT 3 is positioned, the drain current I D of the transistor including the third gate electrode G 3 and the second active pattern F 2 may increase. Accordingly, the semiconductor device with further enhanced operation performance of the NFET may be provided.

According to some exemplary embodiments, the first cut region CT 1 , the second cut region CT 2 , and the third cut region CT 3 may have the same depth. For example, as shown in FIG. 11 B , a height H 3 of the bottom surface of the third cut region CT 3 from the top surface of the substrate 100 may be the same as the height H 1 of the bottom surface of the first cut region CT 1 and the height H 2 of the bottom surface of the second cut region CT 2 .

Referring to FIGS. 11 A and 11 C , in the semiconductor device according to some exemplary embodiments, the first cut region CT 1 , the second cut region CT 2 , and the third cut region CT 3 may have depths different from one another.

For example, as shown in FIG. 11 C , the height H 3 of the bottom surface of the third cut region CT 3 from the top surface of the substrate 100 may be different from the height H 1 of the bottom surface of the first cut region CT 1 and the height H 2 of the bottom surface of the second cut region CT 2 . For example, the height H 3 of the bottom surface of the third cut region CT 3 may be higher than the height H 1 of the bottom surface of the first cut region CT 1 , and may be lower than the height H 2 of the bottom surface of the second cut region CT 2 . This may be attributable to characteristics of an etching process for forming the first cut region CT 1 , the second cut region CT 2 and the third cut region CT 3 , but this should not be considered as limiting.

Referring to FIGS. 12 A and 12 B , in the semiconductor device according to some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be different from the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

For example, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be shorter than the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

In this case, as described above in the explanation of FIG. 5 B , the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may increase. In addition, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device with further improved operation performance may be provided.

FIG. 13 is a layout view provided to explain a semiconductor device according to another exemplary embodiment. For convenience of explanation, elements or operations overlapping with those already described above with reference to FIGS. 1 to 12 B will not be described or described as briefly as possible for the sake of brevity.

Referring to FIG. 13 , in the semiconductor device according to some exemplary embodiments, a length L 2 of the second cut region CT 2 may be different from a length L 1 of the first cut region CT 1 .

For example, as shown in the drawing, the length L 2 of the second cut region CT 2 extended in the first direction X may be shorter than the length L 1 of the first cut region CT 1 extended in the first direction X. In this case, operation performance of the transistor including the third active pattern F 3 , which is the PFET region, can be enhanced. This will be described in detail in the explanation of FIGS. 14 A and 14 B .

In some exemplary embodiments, the second cut region CT 2 may not cut the first, second, fifth, and sixth gate electrodes G 1 , G 2 , G 5 , G 6 . For example, a second portion G 2 - 2 of the second gate electrode G 2 may not be cut by the second cut region CT 2 .

In some exemplary embodiments, the first, second, fifth, and sixth gate electrodes G 1 , G 2 , G 5 , G 6 between the first cut region CT 1 and the second cut region CT 2 may not be cut. For example, the semiconductor device of FIG. 13 may not include the third and fourth cut regions CT 3 , CT 4 of FIG. 1 .

FIGS. 14 A and 14 B are graphs provided to explain changes in a threshold voltage and a drain current according to a length of a cut region.

Specifically, FIG. 14 A is an exemplary graph provided to explain changes in a threshold voltage V T of a PFET according to a length of a cut region. In addition, FIG. 14 B is an exemplary graph provided to explain changes in a drain current I D of the PFET according to the length of the cut region.

For convenience of explanation, it is assumed that an exemplary first semiconductor device PFET (L 2 ) of FIGS. 14 A and 14 B includes the third active pattern F 3 and the third gate electrode G 3 of FIG. 13 . In addition, it is assumed that an exemplary second semiconductor device PFET of FIGS. 14 A and 14 B includes the third active pattern F 3 and the third gate electrode G 3 of FIG. 6 . For reference, a point P of FIGS. 14 A and 14 B refers to a case in which the second cut region CT 2 is not included.

Referring to FIG. 14 A , in the case of the PFET, it can be seen that, as the length of the cut region decreases, a change ΔV T of the threshold voltage decreases. For example, as the length of the second cut region CT 2 of FIG. 6 decreases to the length L 2 of the second cut region CT 2 of FIG. 13 , the threshold voltage V T of the transistor including the third gate electrode G 3 and the third active pattern F 3 may decrease.

Likewise, referring to FIG. 14 B , in the case of the PFET, it can be seen that, as the length of the cut region decreases, a change ΔI D of the drain current increases. For example, as the length of the second cut region CT 2 of FIG. 6 decreases to the length L 2 of the second cut region CT 2 of FIG. 13 , the drain current I D of the transistor including the third gate electrode G 3 and the third active pattern F 3 may increase.

As described above, in some exemplary embodiments, the length L 2 of the second cut region CT 2 may be relatively short. Accordingly, when the third active pattern F 3 is the PFET, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may increase. Accordingly, the semiconductor device with enhanced operation performance of the PFET may be provided.

FIGS. 15 and 16 are layout views provided to explain a semiconductor device according to some exemplary embodiments. For convenience of explanation, elements or operations overlapping with those already described above with reference to FIGS. 1 to 14 will not be described or described as briefly as possible for the sake of brevity.

Referring to FIG. 15 , the semiconductor device according to some exemplary embodiments further includes the third and fourth cut regions CT 3 , CT 4 .

In this case, operation performance of the transistor including the second active pattern F 2 , which is the NFET region, can be enhanced. For example, as described above in the explanation of FIGS. 5 A and 5 B , when the third cut region CT 3 is positioned, the drain current I D of the transistor including the third gate electrode G 3 and the second active pattern F 2 may increase. Accordingly, the semiconductor device with further enhanced operation performance of the NFET may be provided.

Referring to FIG. 16 , in the semiconductor device according to some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be different from the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

For example, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be shorter than the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

In this case, as described above in the explanation of FIGS. 5 A and 5 B , the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may increase. In addition, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device with further improved operation performance may be provided.

FIGS. FIGS. 17 A to 17 B , FIGS. 18 A to 18 B , FIGS. 19 A to 19 B are views provided to explain a semiconductor device according to some exemplary embodiments. For reference, FIG. 17 B is a cross-sectional view taken on G-G of FIG. 17 A . FIGS. 18 B and 19 B are cross-sectional views taken on H-H and I-I of FIGS. 18 A and 19 A , respectively.

Referring to FIGS. 17 A and 17 B , in the semiconductor device according to some exemplary embodiments, the width W 2 of the second cut region CT 2 may be different from the width W 1 of the first cut region CT 1 , and the length L 2 of the second cut region CT 2 may be different from the length L 1 of the first cut region CT 1 .

For example, the width W 2 of the second cut region CT 2 may be larger than the width W 1 of the first cut region CT 1 . In addition, for example, the length L 2 of the second cut region CT 2 extended in the first direction X may be shorter than the length L 1 of the first cut region CT 1 extended in the first direction X.

In this case, as described above in the explanation of FIGS. 7 B and 14 B , the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may increase. In addition, the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device with further improved operation performance may be provided.

In some exemplary embodiments, the first cut region CT 1 and the second cut region CT 2 may have depths different from each other. For example, as shown in FIG. 17 B , the height H 1 of the bottom surface of the first cut region CT 1 from the top surface of the substrate 100 may be different from the height H 2 of the bottom surface of the second cut region CT 2 . For example, the height H 1 of the bottom surface of the first cut region CT 1 may be lower than the height H 2 of the bottom surface of the second cut region CT 2 .

Referring to FIGS. 18 A and 18 B , the semiconductor device according to some exemplary embodiments further includes the third and fourth cut regions CT 3 , CT 4 .

In this case, operation performance of the transistor including the second active pattern F 2 , which is the NFET region, can be enhanced. For example, as described above in the explanation of FIGS. 5 A and 5 B , when the third cut region CT 3 is positioned, the drain current I D of the transistor including the third gate electrode G 3 and the second active pattern F 2 may increase. Accordingly, the semiconductor device with further enhanced operation performance of the NFET may be provided.

In some exemplary embodiments, the first cut region CT 1 , the second cut region CT 2 , and the third cut region CT 3 may have depths different from one another. For example, as shown in FIG. 18 B , the height H 3 of the bottom surface of the third cut region CT 3 from the top surface of the substrate 100 may be different from the height H 1 of the bottom surface of the first cut region CT 1 and the height H 2 of the bottom surface of the second cut region CT 2 . For example, the height H 3 of the bottom surface of the third cut region CT 3 may be higher than the height H 1 of the bottom surface of the first cut region CT 1 , and may be lower than the height H 2 of the bottom surface of the second cut region CT 2 .

Referring to FIGS. 19 A and 19 B , in the semiconductor device according to some exemplary embodiments, the distance D 31 between the second active pattern F 2 and the third and fourth cut regions CT 3 , CT 4 may be different from the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

For example, the distance D 31 between the second active pattern F 2 and the third and fourth cut region CT 3 , CT 4 may be shorter than the distance D 32 between the third active pattern F 3 and the third and fourth cut regions CT 3 , CT 4 .

In this case, as described above in the explanation of FIG. 5 B , the drain current I D of the transistor including the second active pattern F 2 and the third gate electrode G 3 may increase. In addition, the drain current I D of the transistor including the third active pattern F 3 and the third gate electrode G 3 may be prevented from decreasing. Accordingly, the semiconductor device with further improved operation performance may be provided.

According to an exemplary embodiment, a semiconductor device is provided, in which, first to fourth active patterns extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction, a first gate electrode is provided on the first to fourth active patterns and extending in the second direction, a first cut region extends in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extends in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, where one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

According to another exemplary embodiment, a semiconductor device is provided. The semiconductor device includes first to third active patterns that extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction, a first gate electrode provided on the first to third active patterns and extending in the second direction, a second gate electrode extended in the second direction adjacent to the first gate electrode on the first to third active patterns, a first cut region that extends in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region that extends in the first direction between the second active pattern and the third active pattern to cut the second gate electrode, and not to cut the first gate electrode, where one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

According to another exemplary embodiment, a semiconductor device is provided. The a semiconductor device includes a substrate comprising an NFET region and a PFET region, a first active pattern provided on the NFET region and extending in a first direction, a second active pattern provided on the PFET region and extending in the first direction, a first gate electrode provided on the first and second active patterns and extending in a second direction intersecting the first direction, a first cut region provided on a first side surface of the first active pattern opposite to the second active pattern and extending in the first direction to cut the first gate electrode and a second cut region provided on a second side surface of the second active pattern opposite to the first active pattern and extending in the first direction to cut the first gate electrode, where one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region.

Those skilled in the art will appreciate that many variations and modifications may be made to the exemplary embodiments without substantially departing from the principles of the disclosure. Therefore, the exemplary embodiments of the disclosure are used in a generic and descriptive sense only and not for purposes of limitation.